CML Semiconductor Products PRODUCT INFORMATION FX469 1200/2400/4800 Baud FFSK Modem Publication D/469/6 April 1998 Features Pin Selected Xtal/Clock Inputs 1.008MHz or 4.032MHz Radio and General Applications Data-Over-Radio PMR and Cellular Signalling Portable Data Terminals Personal/Cordless Telephone Selectable Data Rates 1200, 2400 and 4800 Baud Full-Duplex FFSK Rx and Tx Bandpass Filters Clock Recovery and Carrier Detect Facilities Rx and Tx Enable Functions Tx GENERATOR Tx FILTER Tx SIGNAL O/P Tx DATA I/P Tx ENABLE Tx SYNC O/P CLOCK RATE VDD XTAL/CLOCK CLOCK OSCILLATOR DIVIDER f .. V BIAS n XTAL VSS 1200/2400 BAUD SELECT 4800 BAUD SELECT BANDPASS O/P Rx ENABLE Rx FILTER LIMITER RETRIGGERABLE MONOSTABLE Rx SIGNAL I/P DATA FILTER DIGITAL FILTER RECTIFIER DIGITAL PLL DATA LATCH LIMITER UNCLOCKED DATA O/P FX469 CLOCKED DATA O/P Rx SYNC O/P NOISE FILTER RECTIFIER CARRIER DETECT O/P S/N COMPARATOR CARRIER DETECT TIME CONSTANT Fig.1 Functional Block Diagram Brief Description Rx, Tx and Carrier Detect paths each contain a bandpass filter to ensure the provision of optimum signal conditions both in the modem and for the Tx modulation circuitry. The FX469 demonstrates a high sensitivity and good bit-error-rate under adverse signal conditions; the carrier detect time constant is set by an external capacitor, whose value should be arranged as required to further enhance this product's performance in high noise environments. This low-power device requires few external components and is available in small outline plastic (S.O.I.C) and cerdip DIL packages. The FX469 is a single-chip CMOS LSI circuit which operates as a full-duplex pin-selectable 1200, 2400 or 4800 baud FFSK Modem. The mark and space frequencies are 1200/1800, 1200/2400 and 2400/4800 Hz respectively. Tone frequencies are phase continuous; transitions occur at the zero crossing point. Employing a common Xtal oscillator with a choice of two clock frequencies (1.008MHz or 4.032MHz) to provide baud-rate, transmit frequencies, and Rx and Tx synchronization, the transmitter and receiver operate entirely independently including individual section powersave functions. The FX469 includes on chip circuitry for Carrier Detect and Rx Clock recovery, both of which are made available as output pins. 1 Pin Number Function FX469 DW LG/LS J/P6 1 1 1 Xtal/Clock : The input to the on-chip inverter, for use with either a 1.008MHz or a 4.032MHz Xtal or external clock. Clock frequency selection is by the “Clock Rate” input pin. The selection of this frequency will affect the operational Data Rate of this device. Refer to Baud Selection information on the next page. Operation of any CML microcircuit without a Xtal or clock input may cause device damage. To minimise damage in the event of a Xtal/drive failure. it is recommended that the power rail (VDD) is fitted with a current limiting device (resistor or fast-reaction fuse). 2 2 2 XtalN : Output of the on-chip inverter. 3 3 3 Tx Sync O/P : A squarewave, produced on-chip, to synchronize the input of logic data and transmission of the FFSK signal (See Figure 4). 4 5 5 Tx Signal O/P : When the transmitter is enabled, this pin outputs the (140-step pseudo sinewave) FFSK signal (See Figure 4). With the transmitter disabled, this output is set to a high-impedance state. 5 7 6 Tx Data I/P : Serial logic data to be transmitted is input to this pin. 6 8 7 Tx EnableN : A logic ‘0’ will enable the transmitter (See Figure 4). A logic ‘1’ at this input will put the transmitter into powersave whilst forcing “Tx Sync Out” to a logic ‘1’ and “Tx Signal Out” to a high-impedance state. This pin is internally pulled to VDD. 7 9 8 Bandpass O/P : The output of the Rx Bandpass Filter. This output impedance is typically 10kW and may require buffering prior to use. 8 10 9 Rx Enable : The control of the Rx function. The control of other outputs is given below. Rx Enable = Rx Function Clock Data O/P Carrier Detect Rx Sync Out “1” = Enabled Enabled Enabled Enabled “0” = Powersave “0” “0” 1” or “0” 9 11 10 VBIAS: The output of the on-chip analogue bias circuitry. Held internally at VDD/2, this pin should be decoupled to VSS by a capacitor (C2). (See Figure 2. This bias voltage is maintained under all powersave conditions. 10 12 11 VSS: Negative supply rail (GND). 2 Pin Number Function DW FX469 LG/LS J/P6 11 13 12 Unclocked Data O/P: The recovered asynchronous serial data output from the receiver. 12 14 13 Clocked Data O/P: The recovered synchronous serial data output from the receiver. Data is latched out by the recovered clock, available at the “Rx Sync O/P,” (See Figure 5). 13 15 14 Carrier Detect O/P: When an FFSK signal is being received this output is a logic ‘1.’ 14 16 15 Rx Signal I/P: The FFSK signal input for the receiver. This input should be coupled via a capacitor, C3. 15 18 17 Rx Sync O/P: A flywheel squarewave output. This clock will synchronize to incoming Rx FFSK data (See Figure 5). 16 19 16 1200/2400 Baud Select: A logic ‘1’ on this pin selects the 1200 baud option. Tone frequencies are: one cycle of 1200Hz represents a logic ‘1,’ one-and-a-half cycles of 1800Hz represents a logic ‘0.’ A logic ‘0’ on this pin selects the 2400 baud option. Tone frequencies are: one-half cycle of 1200Hz represents a logic ‘1,’ one cycle of 2400Hz represents a logic ‘0.’ This function is also used, in part, to select the 4800 baud option. This pin has an internal 1MW pullup resistor. Operational Data Rate Configurations are illustrated in the table below. Xtal/Clock Frequency Clock Rate pin 1200/2400 Select pin 4800 Select pin Baud Rate 1.008MHz 0 0 1 0 0 0 1200 2400 1 1 0 1200 4.032MHz 1 1 0 0 0 1 2400 4800 17 20 18 4800 Baud Select: A logic ‘1’ on this pin combined with a logic ‘0’ on the 1200/2400 Baud Select pin will select the 4800 option (1MW pulldown resistor). Tone frequencies are: one-half cycle of 2400Hz represents a logic ‘1,’ one cycle of 4800Hz represents a logic ‘0.’ This state can only be achieved using a 4.032MHz Xtal input. 18 21 19 Clock Rate: A logic input to select and allow the use of either a 1.008MHz or 4.032MHz Xtal/clock. Logic ‘1’ = 4.032MHz, logic ‘0’ = 1.008MHz. This input has an internal pulldown resistor (1.008MHz). 19 22 20 Carrier Detect Time Constant : Part of the carrier detect integration function. The value of C4 connected to this pin will affect the carrier detect response time and hence noise performance (See Figure 2, Note 3). 20 24 22 VDD: Positive supply rail. A single 5-volt supply is required. 4, 6, 17, 23 4, 21 No internal connection, do not use. 3 Application Information VDD XTAL/CLOCK R1 X1 XTAL C1 Tx SYNC O/P C7 Tx SIGNAL O/P Tx DATA I/P BANDPASS O/P C6 22 2 21 3 20 4 19 5 18 FX469J 6 Tx ENABLE VDD 1 Rx ENABLE V BIAS V SS 17 7 16 8 15 9 14 10 13 11 12 C5 VDD V SS C4 CARRIER DETECT TIME CONSTANT CLOCK RATE 4800 BAUD SELECT Rx SYNC O/P 1200/2400 BAUD SELECT C3 Rx SIGNAL I/P CARRIER DETECT O/P CLOCKED DATA O/P UNCLOCKED DATA O/P C2 V SS Component Value Tolerance R1 C1 C2 C3 C4 C5 C6 C7 X1 1.0MW 33.0pF 1.0µF 0.1µF 0.1µF 1.0µF 1.0µF 33.0pF 1.008MHz or 4.032MHz ±10% Notes 1. VBIAS may be decoupled to VSS and VDD using C2 and C6 when input signals are referenced to the VBIAS pin. For input signals referenced to VSS, decouple VBIAS to VSS using C2 only. ±20% 2. Use C5 when input signals are referenced to VSS, to decouple VDD. ±10% ±20% 3. The value of C4 determines the Carrier Detect time constant. A long time constant results in improved noise immunity but increased response time. C4 may be varied to trade-off response time for noise immunity. See ‘Clock-Rate’ Pin 4. C7 reduces Xtal voltage overshoot. Refer to CML Xtal Application Note D/XT/2 December 1991. Fig.2 External Components VDD VDD MILLIAMMETER MILLIAMMETER CLOCKED DATA O/P Tx DATA I/P PREAMBLE & PSEUDO-RANDOM DATA GENERATOR Tx SIGNAL O/P FX469 TRANSMITTER TELEPHONE CHANNEL SIMULATOR BUFFER (INTERFACE) FX469 RECEIVER (with attenuator & 5kHz BW noise gen) CIRCUIT (components as Fig. 2) Rx SIGNAL I/P Rx SYNC ERROR DETECTOR (components as Fig. 2) VSS Tx SYNC OSCILLOSCOPE TRUE RMS VOLTMETER TRUE RMS VOLTMETER Fig.3 Suggested FX469 Test Set-Up 4 VSS CARRIER DETECT O/P CARRIER DETECT O/P HIGH DETECTOR Application Inf ormation ...... Information t ESET Tx ENABLE Tx SYNC t DH t DSET Tx DATA DC = Don’t Care DV = Data Valid DC DC DV t TDR t TDR DV DC DV DC t TxD 1200 BAUD Tx OUTPUT 2400 BAUD Tx OUTPUT OPEN CIRCUIT OPEN CIRCUIT OPEN CIRCUIT OPEN CIRCUIT Fig.4 Transmitter Timing Characteristics Tx Delay, Signal to Disable Time tESET Data Set-Up Time tDSET Data Hold Time tDH Tx Delay to O/P Time tTxD Tx Data Rate Period tTDR Rx Data Rate Period tRDR Undetermined State Internal Rx Delay tID 1. Consider the Xtal/Clock tolerance. 2. All Tx timings are related to the Tx Sync Output. 3. 1200 baud example. Note Min. Typ. Max. Unit 3 1 2.0 2.0 2.0 800 - 1.2 833 1.5 800 865 2.0 - µs µs µs µs µs µs µs ms 3 3 Rx SIGNAL I/P 2400/4800 BAUD LOGIC ’0’ LOGIC ’1’ Rx SIGNAL I/P 1200 BAUD t ID 1 Rx SYNC O/P (1200Hz) 0 Undetermined State t RDR 1 CLOCKED DATA O/P LOGIC ’1’ 0 Fig.5 Rx Timing Diagram 5 LOGIC ’0’ Specification Absolute Maximum Ratings Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage -0.3 to 7.0V Input voltage at any pin (ref VSS = 0V) -0.3 to (VDD + 0.3V) Sink/source current (supply pins) +/- 30mA (other pins) +/- 20mA Total device dissipation @ TAMB 25°C 800mW Max. Derating 10mW/°C Operating temperature range: FX469DW/LG/LS/P6 FX469J -30°C to +70°C (plastic) -30°C to +85°C (cerdip) Storage temperature range: -40°C to +85°C (plastic) -55°C to +125°C (cerdip) FX469DW/LG/LS/P6 FX469J Operating Limits All device characteristics are measured under the following conditions unless otherwise specified: VDD = 5.0V, TAMB = 25°C. Audio Level 0dB ref: = 300mVrms. Xtal/Clock = 4.032MHz. Signal-to-Noise Ratio measured in the Bit-Rate Bandwidth Baud Rate = 1200 baud. Characteristics Static Values Supply Voltage Supply Current Rx Enabled Tx Disabled Rx and Tx Enabled Rx and Tx Disabled Logic ‘1‘ Level Logic ‘0’ Level Digital Output Impedance Analogue and Digital Input Impedance Tx Output Impedance On-Chip Xtal Oscillator RIN ROUT Inverter d.c. Voltage Gain Gain Bandwidth Product Xtal Frequency Xtal Frequency Dynamic Values Receiver Signal Input Dynamic Range SNR = 50dB Bit Error Rate SNR = 12dB 1200 Baud 2400 Baud 4800 Baud SNR = 20dB 1200/2400/4800 Baud See Note 1 1 2 2 3, 4 4 Min. Typ. Max. Unit 4.5 4.0 100 - 5.0 3.6 4.5 650 4.0 0.6 5.5 1.0 1.0 V mA mA µA V V kW kW kW 10.0 5.0 10.0 4.1 - 1.008 4.032 15.0 20.0 - MW kW V/V MHz MHz MHz 100 230 1000 mVrms - 2.5 1.5 1.5 - 104 103 103 - <1.0 - 108 - 0.995 - - - 150 4 Receiver Synchronization SNR =12dB Probability of Bit 16 Being Correct 7 Carrier Detect Sensitivity Probabilty of C.D. Being High After Bit 16 SNR = 12dB 0dB Noise No Signal 5, 10 7, 8 5, 9 9 0.995 0.05 6 mVrms Specification ...... Characteristics See Note Min. Transmitter Output Tx Output Level Output Level Variation 1200/1800Hz or 1200/2400Hz or 2400/4800Hz Output Distortion 3rd Harmonic Distortion Logic ‘1’ Carrier Frequency 1200 Baud 6 2400 Baud 6 4800 Baud 6 Logic ‘0’ Carrier Frequency 1200 Baud 6 2400 Baud 6 4800 Baud 6 Isochronous Distortion 1200Hz - 1800Hz/1800Hz - 1200Hz 1200Hz - 2400Hz/2400Hz - 1200Hz 2400Hz - 4800Hz/4800Hz - 2400Hz Typ. 0 - Max. Unit 775 - mVrms 3.0 2.0 1200 1200 2400 1800 2400 4800 ±1.0 5.0 3.0 - dB % % Hz Hz Hz Hz Hz Hz 25.0 20.0 - 40.0 30.0 10.0 µs µs 20 µs Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. With reference to VDD = 5.0 volts. Xtal frequency, type and tolerance depends upon system requirements. See Figure 5 (variation of BER with Input Signal Level). SNR = Signal-to-Noise Ratio in the Bit-Rate Bandwidth. See Figure 2. Dependent upon Xtal tolerance. 10101010101 ...01 pattern. Measured with a 150mVrms input signal (no noise); 1200/2400 baud operation. Reference (0dB) level for C.D. probability measurements is 230mVrms. For 1200 and 2400 baud operation only; when operating at 4800 baud the Carrier Detect output should be ignored. 1 x 10 -1 * BIT RATE BANDWIDTH 10 dB 12 dB SN R* SN R * 1 x 10 -3 dB 20 BIT ERROR RATE 1 x 10 -2 R SN * 1 x 10 -4 1 x 10 -5 50 100 200 150 250 300 500 700 800 INPUT SIGNAL LEVEL (mVrms) Fig.6 Typical Variation of Bit Error Rate with Input Level 7 Application Information FX469 IDEAL COHERENT FFSK 2 x 10-2 BIT ERROR RATE (log scale) 10 -2 10 -3 10 -4 8 6 4 2 10 -5 0 2 1 3 4 5 6 7 8 9 10 11 12 13 14 SNR (dB) BIT RATE BANDWIDTH 15 16 (lin scale) Fig.7 Rx Bit-Error-Rate vs Signal-to-Noise Ratio Package Outlines Handling Precautions The FX469 is available in the package styles outlined below. Mechanical package diagrams and specifications are detailed in Section 10 of this document. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. The FX469 is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage. FX469DW 20-pin plastic S.O.I.C. FX469J (D3) NOT TO SCALE 22-pin cerdip DIL (J3) NOT TO SCALE Max. Body Length Max. Body Width 12.95mm 7.59mm Max. Body Length Max. Body Width 8 27.38mm 9.75mm Package Outlines ...... FX469LG 24-pin quad plastic encapsulated bent and cropped (L1) FX469LS NOT TO SCALE 24-lead plastic leaded chip carrier (L2) NOT TO SCALE Max. Body Length Max. Body Width 10.25mm 10.25mm Max. Body Length Max. Body Width FX469P6 10.40mm 10.40mm 22-pin plastic DIL Ordering Information FX469DW FX469J FX469LG 20-pin surface mount S.O.I.C. 22-pin cerdip DIL 24-pin quad plastic encapsulated bent and cropped (L1) FX469LS 24-lead plastic leaded chip carrier (L2) FX469P6 22-pin plastic DIL NOT TO SCALE Max. Body Length Max. Body Width CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry. 9 27.94mm 9.14mm