CMLMICRO FX365C

CML Semiconductor Products
PRODUCT INFORMATION
FX365C
Low-Voltage CTCSS Encoder/
Decoder
Publication D/365C/3 October 1995
Applications
Mobile Radio Systems
Features
Low-Voltage (3-Volt) Supply
39 Programmable Sub-Audio
Tones + NOTONE
Community Base Stations
Meets MPT1306 and EIA - 220 B
Sub-Audio Signalling and Selective Calling
“Sports Radio” (Japan)
High Voiceband/CTCSS Isolation
Status and Alarm Systems
Separate Sub-Audio and Rx/Tx
Audio Paths and Filtering
Tx
VOICE-AUDIO PATH
Tx AUDIO
INPUT
Amateur Radio
Tx AUDIO
OUTPUT
Tx
300Hz
Rx AUDIO
INPUT
XTAL/CLOCK
XTAL
Rx AUDIO
OUTPUT
(Rx)
CONTROL
Rx
XTAL/CLOCK
GENERATOR
VDD
SUB-AUDIO PATH
(Rx)
SUB-AUDIO
TONE INPUT
DIGITAL
PERIOD
DETECTOR
fTONE
OUTPUT
LATCH
Rx TONE
DETECT
TONE FREQUENCY
BUS
LOAD/LATCH
VBIAS
SERIAL ENABLE 1/D5
SERIAL ENABLE 2/D4
SERIAL DATA/D3
SERIAL CLOCK/D2
D1
D0
8-BIT
SERIAL
SHIFT
REGISTER
PROGRAM
LOGIC
8-BIT
LATCH
FX365C
TONE
GENERATOR
Tx TONE
OUTPUT
Tx ENABLE
Rx/Tx
PTL
CONTROL
VDD
3
2VDD
3
LOGIC
LOGIC
DECODE
COMPARATOR REF.
DECODE
COMPARATOR
INPUT
VSS
+
-
DECODE COMPARATOR
Rx TONE DECODE
OUTPUT
Fig.1 Functional Block Diagram
Brief Description
The FX365C is a 3-volt, half-duplex predictive
Continuous Tone Controlled Squelch System
(CTCSS) encoder/decoder microcircuit. The FX365C
has integral voice-band filtering for prefiltering of Tx
audio and the rejection of the CTCSS tone in receive.
Under µProcessor control, the FX365C will encode
and decode any one of 39 sub-audio frequencies
(+NOTONE) in the range 67.0Hz to 250.3Hz. Tone
frequencies and all functional commands can be
loaded to the device in either pin-selectable 8-bit
parallel or serial format.
A separate, Rx/Tx voice-audio path is available with
a highpass (sub-audio reject) filter automatically
placed in the relevant Rx or Tx voice line.
The Rx sub-audio (CTCSS) path contains a
(selected tone frequency) bandpass filter and period
detector providing a logic level output (Rx Tone
Detect) to indicate a successful decode operation.
Rx “Press to Listen” (PTL) and Tx “Squelch-Tail
Elimination” functions are available in both command
loading modes. The squelch-tail elimination function
will provide (Tx tone) phase-reversal to minimise the
annoying audio outputs that occur at the receiver on
completion of a transmission.
Tone frequencies and filter accuracies are
maintained by an on-chip 1.0MHz clock oscillator
employing an external crystal or clock pulse input.
The FX365C, which exhibits high audio and subaudio performance with low falsing, is available in 24pin DIL and small outline SMD packages.
Pin Number
FX365C
Function
DW, J, LG and LS package styles
1
VDD: Positive supply rail. A single stable supply is required; levels and voltages within the FX365C are
dependent upon this supply.
This pin should be decoupled to VSS by a capacitor located close to the pin.
2
Xtal/CIock: Input to the on-chip inverter; used with a 1.0MHz Xtal or external clock source.
3
Xtal: Output of the on-chip clock oscillator inverter.
4
Load/Latch: Controls 8 on-chip latches and is used to latch Rx/Tx, PTL, D0 - D5. This pin is internally
pulled to VDD. A logic ‘1’ applied to this input places the 8 latches into a 'transparent' mode. A logic ‘0’
applied to this input places the 8 latches into the ‘latched’ mode.
In parallel mode data is loaded and latched by a logic ‘1’ to ‘0’ transition (see Figure 4a).
In serial mode data is loaded and latched by a ‘0’ to ‘1’ to ‘0’ strobe pulse on this pin (see Figure 4b).
5
D5/Serial Enable 1: Data input D5 (Parallel Mode); Serial Enable 1 (Serial Mode).
A logic ‘l’ applied to this input, together with a logic ‘0’ applied to D4/Serial Enable 2, will put the device
into 'Serial Mode' (see Figure 4b). This pin is internally pulled to VDD.
6
D4/Serial Enable 2: Data input D4 (Parallel Mode); Serial Enable 2 (Serial Mode).
A logic ‘0’ applied to this input, together with a logic ‘1’ applied to D5/Serial Enable 1, will place the
device into ‘Serial Mode’ (see Figure 4b). This pin internally pulled to VDD.
7
D3/Serial Data: Data input D3 (Parallel Mode); Serial Data Input (Serial Mode).
In Serial Mode this pin becomes the serial data input for D5 - D0, Rx/Tx, PTL (see Figure 4b). D5 is
clocked-in first and PTL last. This pin internally pulled to VDD.
8
D2/Serial Clock: Data input D2 (Parallel Mode); Serial Clock Input (Serial Mode).
In Serial Mode this pin becomes the Serial Clock input. Data is clocked on the positive-going edge
(see Figure 4b). This pin is internally pulled to VDD.
9
D1: Data input D1 (Parallel Mode); Not Used (Serial Mode). This pin is internally pulled to VDD.
10
D0: Data input D0 (Parallel Mode); Not Used (Serial Mode). This pin is internally pulled to VDD.
11
VSS: Negative supply (GND).
12
Decode Comparator Ref. (I/P): Internally biased to VDD/3 or 2VDD/3 via 1.0MΩ resistors depending
on the logical state of the Tone Decode Output pin, this input provides the decode comparator
reference voltage; switching of bias voltages provides hysteresis to reduce 'chatter' under marginal
conditions. Tone Decode Output = logic ‘1’ will place this input to 2VDD/3 bias, a logic ‘0’ will bias this
input to VDD/3.
2
Pin Number
FX365C
Function
DW and J package styles.
13
Rx Tone Decoder (O/P): The gated output of the on-chip Decode Comparator.
This output is used to gate the Rx Audio path. A logic ‘0’ output on this pin indicates a successful
decode and indicates that the ‘Decode Comparator Input’ pin is more positive than the ‘Decode
Comparator Ref’ input (see Table 1).
14
Decode Comparator Input: The inverting input of the Decode Comparator. This pin is to be
connected to the Rx Tone Detect pin via external integrating components as shown in Figure 2.
15
Rx Tone Detect (O/P): In the Rx mode this output will go to a logic ‘1’ during a successful decode
(Table 1). This pin is to be connected to the Decode Comparator Input via the external integrating
circuitry as shown in Figure 2.
16
Tx Tone Output: A low-impedance emitter-follower source, under the control of the Rx/Tx pin, of the
CTCSS sinewave. This output, when not transmitting a sub-audio tone, may be set to a VDD/(2-0.7)V
bias or open-circuit as described in Table 1.
17
Rx/Tx: This input (Parallel Mode) selects Rx or Tx modes (see Figure 2). Logic ‘1’ = Rx;
logic ‘0’ = Tx. In Serial Mode this (Rx or Tx) function is serially loaded via pin 7 (Serial Data) and this
pin not used. This pin is internally pulled to VDD via a 1MΩ resistor (Rx operaion).
18
PTL: A dual-function input. In the parallel load mode, Rx operation: A logic ‘1’ provides a “Press To
Listen” function by overriding the tone-squelch and enabling the audio path.
In the parallel load mode, Tx operation: A logic ‘1’ provides a “Squelch Tail Elimination” function by
reversing the phase of the transmitting sub-audio tone; the phase reversal function should be applied
by a suitable timing circuit.
In the serial load mode (Rx and Tx) these functions are loaded via the serial data word at pin 7.
19
Rx Audio Output: The high-pass filtered ‘Received Audio’ output. This pin outputs audio when Rx
Tone Decode = ‘0’, or PTL = ‘1’ or ‘Notone’ is programmed (Table 2). In Tx Mode this pin is biased to
VDD/2.
20
Tx Audio Output: The high-pass filtered ‘Transmit Audio’ output. In Tx mode this pin outputs audio
present at the Tx Audio Input by opening the Tx audio path. In Rx mode this pin is biased to VDD/2.
21
VBIAS: The output of the on-chip analogue bias circuitry. Held internally at VDD/2, this pin should be
externally decoupled to VSS.
22
Tx Audio Input: The Tx Audio Input pin. Tx voice-band audio may be prefiitered, using the Voice
Audio Path, thus helping to avoid talk-off due to the intermodulation of speech frequencies with the
transmitted CTCSS tone. The Tx Audio Path may also be used to pre-filter speech when employing
‘scramblers’ which could introduce noise into the low frequency band. This pin is internally biased to
VDD/2.
23
Rx Audio Input: The input to the Voice Audio high-pass filter in the Rx Mode.
This pin is internally biased to VDD/2.
24
Tone Input: The input to the CTCSS tone detector and is internally biased to VDD/2.
3
Application Information
VDD
XTAL/CLOCK
C8
2
V SS
C1
VDD
R1
X1
XTAL/CLOCK
C2
XTAL
3
V SS
LOAD/LATCH
XTAL
D5
VDD
D4
L/LATCH
S DATA
S CLOCK
4
D3
5
D2
6
D1
7
18
x
8
17
x
x
9
x
10
V SS
1
24
2
23
3
22
4
21
5
20
6
19
FX365C
7
D0
x
C3
17
9
16
10
15
11
14
12
13
SERIAL LOAD
MODE
Rx AUDIO IN
C4
Tx AUDIO IN
C5
VBIAS
Tx AUDIO OUT
Rx AUDIO OUT
PTL (Parallel Load)
18
8
TONE IN
Rx/Tx (Parallel Load)
TONE OUT
R2
C6
D1
R3
DECODE COMP IN
Rx TONE DECODE OUT
PARALLEL LOAD
MODE
C7
[differences]
V SS
V SS
External Components
Component
R1
R2
R3
Value
1.0MΩ
820kΩ
330kΩ
Tolerance
±10%
±10%
±10%
C1
C2
C3
68.0pF
33pF
0.1µF
±20%
±20%
±20%
C4
C5
C6
C7
C8
D1
X1
0.1µF
0.1µF
1.0µF
0.1µF
1.0µF
small signal type
1.0MHz
±20%
±20%
±20%
±20%
±20%
Fig.2 Recommended External Components
Input Pin Condition
D0 to D5
Rx/Tx PTL
Output Pin Condition
Decode
Comp.
Input
Result and/or Function
Tone
Tx Tone Tx Audio Tone
Rx Audio
Tx
Phase
Path
Decoder
Path
Enabled Reversed Enabled Enabled Enabled Notes
Rx Tone Rx Tone
Detect Decode
TONE
0
0
X
0
1
YES
NO
YES
NO
NO (BIAS)
TONE
0
1
X
0
1
YES
YES
YES
NO
NO (BIAS)
NOTONE
0
X
X
0
1
NO (BIAS)
X
YES
NO
NO (BIAS)
1
0
0
0
1
NO(O/C)
X
NO
YES
YES
TONE
TONE
1
1
0
0
1
N O (O / C )
X
NO
YES
YES
TONE
1
X
1
1
0
N O (O / C )
X
NO
YES
YES
NOTONE
1
X
X
X
0
N O (O / C )
X
NO
YES
YES
NOTES
1A Normal tone transmit condition.
1B Tone Tx with phase reversed.
2
NOTONE programmed in Tx mode; tone transmit output set to VDD/2 -(0.7v). Tx audio path enabled.
3A Normal decode standby.
3B Normal decode standby with PTL used to enable audio.
4
Normal ‘decode of correct CTCSS tone’ condition; PTL has no effect.
5
NOTONE programmed in Rx mode; tone transmit output (o/c). Rx audio path enabled.
Table 1 Combinations of Input/Output Conditions
1A
1B
2
3A
3B
4
5
x = don't care
4
Application Information ......
Nominal
Freq (Hz)
FX365C
Freq. (Hz)
67.0
67.05
69.3
69.32
71.9
71.90
74.4
74.35
77.0
76.96
79.7
79.77
82.5
82.59
85.4
85.38
88.5
88.61
91.5
91.58
94.8
94.76
97.4
97.29
100.0
99.96
103.5
103.43
107.2
107.15
110.9
110.77
114.8
114.64
118.8
118.80
123.0
122.80
127.3
127.08
131.8
131.67
136.5
136.61
141.3
141.32
146.2
146.37
151.4
151.09
156.7
156.88
162.2
162.31
167.9
168.14
173.8
173.48
179.9
180.15
186.2
186.29
192.8
192.86
203.5
203.65
210.7
210.17
218.1
218.58
225.7
226.12
233.6
234.19
241.8
241.08
250.3
250.28
NOTONE
NOTONE
Serial Input Mode
∆fo %
D0
D1
D2
D3
D4
D5
+0.7
+0.03
0.0
-0.07
-0.05
+0.09
+0.10
-0.02
+0.13
+0.09
-0.04
-0.11
-0.04
-0.07
-0.05
-0.12
-0.14
0.0
-0.17
-0.17
-0.10
+0.08
+0.02
+0.12
-0.20
+0.11
+0.07
+0.14
-0.19
+0.14
+0.05
+0.03
+0.07
-0.25
+0.22
+0.18
+0.25
-0.30
-0.01
1
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
x
1
0
1
1
1
0
1
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
x
1
0
1
1
1
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
Clock
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data
1
1
1
1
0
1
1
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Table 2 Tone Programming Information
Gain (dB)
5
Passband
0
VDD = 3.5V
-5
-10
-15
-20
-25
Stopband
-30
-35
-40
-45
100
300
1000
Fig.3 Voiceband Filter Response
5
Frequency (Hz)
3000
Specification
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits
is not implied.
Supply voltage
-0.3 to 7.0V
Input voltage at any pin (ref VSS = 0V)
-0.3 to (VDD + 0.3V)
Sink/source current (supply pins)
+/- 30mA
(other pins)
+/- 20mA
Total device dissipation @ TAMB 25°C
800mW Max.
Derating
10mW/°C
Operating temperature range: FX365C J
-40°C to +85°C (cerdip)
FX365C DW
-40°C to +85°C (plastic)
Storage temperature range:
FX365C J
-55°C to +125°C (cerdip)
FX365C DW
-40°C to +85°C (plastic)
Operating Limits
All device characteristics are measured under the following conditions unless otherwise specified:
VDD = 3.3V. TAMB = 25°C. Xtal/Clock f0 = 1.0MHz. Signal 0dB ref: = 180mVrms.
Composite Signal = 1.0kHz Audio Tone at 0dB, Noise at –12.0dB (gaussian white noise, band-limited to
6.0kHz), Programmed CTCSS Tone at -20dB.
Characteristics
Static Characteristics
Supply Voltage (VDD)
Supply Current
(Tx)
(Rx)
Sub-Audio Tone Input Impedance
Tx Tone Output Impedance
Voice-Audio Input Impedance
Voice-Audio Output Impedance
Digital Input Impedance
Input Logic ‘1’
Input Logic ‘0’
Output Logic ‘1’, source = 0.1mA
Output Logic ‘0’, sink = 0.1 mA
Dynamic Characteristics
Tone Decoder
Decode Input Signal Level
Decode Response Time
De-Response Time
Decode Selectivity
Tone Encoder
Tx Tone Output Level
Tx Tone Frequency Accuracy (fO error)
Risetime to 90% (nominal output)
fO > 100Hz
fO < 100Hz
Tone Output Load Current
Total Harmonic Distortion
Output Level Variation Between Tones
Spurious Emissions
Voice-Audio Filter and Path
Passband Frequencies
Passband Gain
at 1.0kHz
w.r.t. 1.0kHz
Total Harmonic Distortion
Stopband Frequencies
Stopband Attenuation
Output Noise Level (Input a.c. Short Cct)
SINAD
Audio Switch Isolation
See Note
Min.
Typ.
Max.
Unit
3.0
3.3
5.5
V
1
1
1
2
2
70.0
80.0
-
1.5
1.5
1.0
4.0
1.0
1.0
1.0
-
30.0
20.0
mA
mA
MΩ
kΩ
MΩ
kΩ
MΩ
%VDD
%VDD
%V DD
%V DD
3
3, 6
3, 6
3
-20.0
±0.5
-
250
250
±3.0
dB
ms
ms
%fO
-0.3
627
-
+0.3
mVrms
%fO
-
55.0
70.0
2.0
0.1
-
5.0
5.0
-48.0
ms
ms
mA
%
dB
dB
3000
Hz
0.5
5.0
250
-48.0
-
dB
dB
%
Hz
dB
dB
dB
dB
4
4
300
-2.0
33.0
36.0
-
5
7
8
5
6
0
2.0
36.0
-54.0
40.0
60.0
Specification ......
Characteristics
See Note
Serial/Parallel Inputs
Parallel Set-Up Time (tSP)
Load/Latch Pulse Width (tL)
Serial Clock Pulse Width (tC)
Serial Set-Up Time (tSS)
Serial Enable Time (t1)
Serial Load/Latch Set-Up Time (t2)
Serial Clock Frequency
Min.
Typ.
Max.
Unit
400
400
400
400
400
400
-
1.0
-
ns
ns
ns
ns
ns
ns
MHz
Notes
1.
2.
3.
4.
5.
6.
7.
8.
Refers to Rx/Tx, PTL, Decode Comparator Input, D0, D1, D2, D3, D4, D5 inputs.
All logic outputs.
Composite Signal test condition.
Any programme tone and RL = 600Ω. CL = 15pF. Includes response to a phase-reversal instruction.
1kHz reference = 0dB.
fO > 100Hz, (for 100Hz >f O >67Hz: t = (100/fO Hz) x 250ms).
Measured in a 30kHz bandwidth.
For an input level of 180mVrms at 1.0kHz, in a 30kHz measurement bandwidth.
(a) Parallel Mode Timing
D0 to D5, Rx/Tx and PTL
tL
For wired, non-µP applications,
Load/Latch should be connected to VDD.
LOAD/LATCH
tSP
(b) Serial Mode Timing
D5
SERIAL
ENABLE
FUNCTION
D4
Data load sequence: D5, D4, D3, D2, D1, D0, Rx/Tx and PTL/Phase Reverse
t1
SERIAL
DATA
D3
tW
DATA D5
DATA D4
D
3
Rx/Tx
(Rx) PTL or
(Tx) Phase Reverse
tC
SERIAL
CLOCK
D2
tSS
D1 and D0
NOT USED
1.0MΩ INTERNAL PULLUP
t2
tL
LOAD/LATCH
LOAD DATA
LATCH DATA
DATA LATCHED
Fig.4 Serial and Parallel Timing Diagrams
7
Package Outlines
Handling Precautions
The FX365C is available in the package styles
outlined below. Mechanical package diagrams and
specifications are detailed in Section 10 of this
document.
Pin 1 identification marking is shown on the relevant
diagram and pins on all package styles number
anti-clockwise when viewed from the top.
The FX365C is a CMOS LSI circuit which includes
input protection. However precautions should be taken
to prevent static discharges which may cause damage.
FX365C DW
FX365C J 24-pin cerdip DIL
24-pin plastic S.O.I.C
(D2)
(J4)
NOT TO SCALE
NOT TO SCALE
Max. Body Length
Max. Body Width
15.57mm
7.59mm
Max. Body Length
Max. Body Width
Ordering Information
FX365C DW 24-pin plastic S.O.I.C.
(D2)
FX365C J
(J4)
24-pin cerdip DIL
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied
and CML reserves the right at any time without notice to change the said circuitry.
32.00mm
13.36mm
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor
companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc
(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst
maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)
Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits.
These companies are all 100% owned operating companies of the CML Microsystems Plc
Group and these changes are purely changes of name and do not change any underlying legal
entities and hence will have no effect on any agreements or contacts currently in force.
CML Microcircuits Product Prefix Codes
Until the latter part of 1996, the differentiator between products manufactured and sold from
MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX
respectively. These products use the same silicon etc. and today still carry the same prefixes.
In the latter part of 1996, both companies adopted the common prefix: CMX.
This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits
(UK)Ltd
CML Microcircuits
(USA) Inc.
CML Microcircuits
(Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon,
Essex, CM9 6WG, England
Tel: +44 (0)1621 875500
Fax: +44 (0)1621 875600
[email protected]
www.cmlmicro.com
4800 Bethania Station Road,
Winston-Salem, NC 27105, USA
Tel: +1 336 744 5050,
0800 638 5577
Fax: +1 336 744 5054
[email protected]
www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/
06 Mactech Industrial Building,
Singapore 349307
Tel: +65 7450426
Fax: +65 7452917
[email protected]
www.cmlmicro.com
D/CML (D)/1 February 2002