a Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD807 frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition. FEATURES Meets CCITT G.958 Requirements for STM-1 Regenerator—Type A Meets Bellcore TR-NWT-000253 Requirements for OC-3 Output Jitter: 2.0 Degrees RMS 155 Mbps Clock Recovery and Data Retiming Accepts NRZ Data, No Preamble Required Phase-Locked Loop Type Clock Recovery— No Crystal Required Quantizer Sensitivity: 2 mV Level Detect Range: 2.0 mV to 30 mV Single Supply Operation: +5 V or –5.2 V Low Power: 170 mW 10 KH ECL/PECL Compatible Output Package: 16-Pin Narrow 150 mil SOIC The AD807 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD807. The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is 2.0 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance. PRODUCT DESCRIPTION The AD807 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 155 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-3 or SDH STM-1 fiber optic receiver. The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater. The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output. Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency. The AD807 consumes 140 mW and operates from a single power supply at either +5 V or –5.2 V. The PLL has a factory trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee FUNCTIONAL BLOCK DIAGRAM CF1 CF2 PIN QUANTIZER ΦDET NIN COMPENSATING ZERO ∑ LOOP FILTER PHASE-LOCKED LOOP VCO THRADJ SIGNAL LEVEL DETECTOR CLKOUTP CLKOUTN FDET LEVEL DETECT COMPARATOR/ BUFFER RETIMING DEVICE DATAOUTP DATAOUTN AD807 SDOUT REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 AD807–SPECIFICATIONS (T = T A Parameter QUANTIZER–DC CHARACTERISTICS Input Voltage Range Input Sensitivity, VSENSE Input Overdrive, VOD Input Offset Voltage Input Current Input RMS Noise Input Pk-Pk Noise QUANTIZER–AC CHARACTERISTICS Upper –3 dB Bandwidth Input Resistance Input Capacitance Pulse Width Distortion LEVEL DETECT Level Detect Range Response Time Hysteresis (Electrical) SDOUT Output Logic High SDOUT Output Logic Low PHASE-LOCKED LOOP NOMINAL CENTER FREQUENCY CAPTURE RANGE MIN to TMAX, VS = VMIN to VMAX, CD = 0.1 mF, unless otherwise noted) Condition Min @ PIN or NIN PIN–NIN, Figure 1, BER = ≤ 1 × 10–10 Figure 1, BER = ≤ 1 × 10–10 2.5 2 0.001 RTHRESH = INFINITE RTHRESH = 49.9 kΩ RTHRESH = 3.4 kΩ DC Coupled RTHRESH = INFINITE RTHRESH = 49.9 kΩ RTHRESH = 3.4 kΩ Load = +4 mA Load = –1.2 mA JITTER 27–1 PRN Sequence 223–1 PRN Sequence PECL OUTPUT VOLTAGE LEVELS Output Logic High, VOH Output Logic Low, VOL SYMMETRY (Duty Cycle) Recovered Clock Output, Pin 5 OUTPUT RISE / FALL TIMES Rise Time (tR) Fall Time (tF) Units VS V mV V µV µA µV µV 2.5 500 10 2 5 20 4.0 5.0 7.0 MHz MΩ pF ps 4.0 7.4 25 1.5 10.0 9.0 10.0 0.4 mV mV mV µs dB dB dB V V 156 MHz MHz 156 20 3.5 MHz Degrees ns 3.3 40 ns Degrees 2.7 Degrees RMS Degrees RMS 155.52 Figure 2 240 Bits, No Transitions POWER SUPPLY CURRENT 0.8 4 14 0.1 2.3 3.0 3.0 3.6 155 HOLD TIME (tH) PHASE DRIFT Bandwidth Acquisition Time CD = 0.1 µF CD = 0.33 µF POWER SUPPLY VOLTAGE Max 180 1 2 100 27–1 PRN Sequence Figure 2 JITTER TRANSFER Peaking (Figure 20) 50 5 50 650 BER = ≤ 1 × 10–10 BER = ≤ 1 × 10–10 TRACKING RANGE STATIC PHASE ERROR SETUP TIME (tSU) JITTER TOLERANCE Typ 155 f = 10 Hz f = 6.5 kHz f = 65 kHz f = 1.3 MHz 3.0 4 3.2 3.0 3.1 2.0 2.0 4.5 0.45 0.45 3000 7.6 1.0 0.67 Unit Intervals Unit Intervals Unit Intervals Unit Intervals 65 0.08 0.04 92 dB dB kHz CD = 0.15 µF CD = 0.33 µF 4 × 105 2 × 106 223–1 PRN Sequence, T A = +25°C VCC = 5 V, VEE = GND VMIN to VMAX 4.5 VCC = 5.0 V, VEE = GND, TA = +25°C 25 –1.2 –2.0 Referenced to VCC ρ = 1/2, TA = +25°C, VCC = 5 V, VEE = GND 20%–80% 80%–20% 130 2 × 106 5.5 Bit Periods Bit Periods Volts 34.5 39.5 mA –1.0 –1.8 –0.7 –1.7 Volts Volts 54.1 % 1.5 1.5 ns ns 50.1 1.1 1.1 Specifications subject to change without notice. –2– REV. A AD807 ABSOLUTE MAXIMUM RATINGS 1 PIN FUNCTION DESCRIPTIONS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V Input Voltage (Pin 12 or Pin 13) . . . . . . . . . . . . . . VCC + 0.6 V Maximum Junction Temperature . . . . . . . . . . . . . . . . . +165°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . 500 V NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics: 16-Pin Narrow Body SOIC Package: θJA = 110°C/Watt. OUTPUT NOISE 1 0 INPUT (V) OFFSET OVERDRIVE SENSITIVITY Figure 1. Input Sensitivity, Input Overdrive SETUP HOLD t SU tH Pin No. Mnemonic Description 1 DATAOUTN Differential Retimed Data Output 2 DATAOUTP Differential Retimed Data Output 3 VCC2 Digital VCC for ECL Outputs 4 CLKOUTN Differential Recovered Clock Output 5 CLKOUTP Differential Recovered Clock Output 6 VCC1 Digital VCC for Internal Logic 7 CF1 Loop Damping Capacitor 8 CF2 Loop Damping Capacitor 9 AVEE Analog VEE 10 THRADJ Level Detect Threshold Adjust 11 AVCC1 Analog VCC for PLL 12 NIN Quantizer Differential Input 13 PIN Quantizer Differential Input 14 AVCC2 Analog VCC for Quantizer 15 SDOUT Signal Detect Output 16 VEE Digital VEE for Internal Logic PIN CONFIGURATION DATAOUTP (PIN 2) DATAOUTN 1 16 VEE DATAOUTP 2 15 SDOUT 3 14 AVCC2 VCC2 CLKOUTP (PIN 5) Figure 2. Setup and Hold Time CLKOUTN 4 AD807 13 PIN CLKOUTP 5 TOP VIEW (NOT TO SCALE) 12 NIN 6 11 AVCC1 CF1 7 10 THRADJ CF2 8 9 VCC1 AVEE ORDERING GUIDE Model Temperature Range Package Description Package Option AD807-155BR or AD807A-155BR AD807-155BR-REEL7 or AD807A-155BRRL7 AD807-155BR-REEL or AD807A-155BRRL –40°C to +85°C –40°C to +85°C –40°C to +85°C 16-Pin Narrowbody SOIC 750 Pieces, 7" Reel 2500 Pieces, 13" Reel R-16A R-16A R-16A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD807 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– WARNING! ESD SENSITIVE DEVICE AD807 Tracking Range DEFINITION OF TERMS Maximum, Minimum and Typical Specifications This is the range of input data rates over which the AD807 will remain in lock. Specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. Typical specifications are the mean of the distribution of the data for that parameter. If a parameter has a maximum (or a minimum), that value is calculated by adding to (or subtracting from) the mean six times the standard deviation of the distribution. This procedure is intended to tolerate production variations: if the mean shifts by 1.5 standard deviations, the remaining 4.5 standard deviations still provide a failure rate of only 3.4 parts per million. For all tested parameters, the test limits are guardbanded to account for tester variation to thus guarantee that no device is shipped outside of data sheet specifications. Capture Range This is the range of input data rates over which the AD807 will acquire lock. Static Phase Error This is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. Gate delays between the signals that define static phase error, and IC input and output signals prohibit direct measurement of static phase error. Input Sensitivity and Input Overdrive Data Transition Density, ρ Sensitivity and Overdrive specifications for the Quantizer involve offset voltage, gain and noise. The relationship between the logic output of the quantizer and the analog voltage input is shown in Figure 1. This is a measure of the number of data transitions, from “0” to “1” and from “1” to “0,” over many clock periods. ρ is the ratio (0 ≤ ρ ≤ 1) of data transitions to bit periods. Jitter For sufficiently large positive input voltage the output is always Logic 1 and similarly, for negative inputs, the output is always Logic 0. However, the transitions between output Logic Levels 1 and 0 are not at precisely defined input voltage levels, but occur over a range of input voltages. Within this Zone of Confusion, the output may be either 1 or 0, or it may even fail to attain a valid logic state. The width of this zone is determined by the input voltage noise of the quantizer (650 µV at the 1 × 10–10 confidence level). The center of the Zone of Confusion is the quantizer input offset voltage (± 500 µV maximum). Input Overdrive is the magnitude of signal required to guarantee correct logic level with 1 × 10–10 confidence level. This is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms or Unit Intervals (UI). Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. Jitter on the recovered clock causes jitter on the retimed data. Output Jitter This is the jitter on the retimed data, in degrees rms, due to a specific pattern or some pseudorandom input data sequence (PRN Sequence). Jitter Tolerance Jitter Tolerance is a measure of the AD807’s ability to track a jittery input data signal. Jitter on the input data is best thought of as phase modulation, and is usually specified in unit intervals. With a single-ended PIN-TIA (Figure 3), ac coupling is used and the inputs to the Quantizer are dc biased at some commonmode potential. Observing the Quantizer input with an oscilloscope probe at the point indicated shows a binary signal with average value equal to the common-mode potential and instantaneous values both above and below the average value. It is convenient to measure the peak-to-peak amplitude of this signal and call the minimum required value the Quantizer Sensitivity. Referring to Figure 1, since both positive and negative offsets need to be accommodated, the Sensitivity is twice the Overdrive. The AD807 Quantizer has 2 mV Sensitivity. The PLL must provide a clock signal that tracks the phase modulation in order to accurately retime jittered data. In order for the VCO output to have a phase modulation that tracks the input jitter, some modulation signal must be generated at the output of the phase detector. The modulation output from the phase detector can only be produced by a phase error between its data input and its clock input. Hence, the PLL can never perfectly track jittered data. However, the magnitude of the phase error depends on the gain around the loop. At low frequencies, the integrator of the AD807 PLL provides very high gain, and thus very large jitter can be tracked with small phase errors between input data and recovered clock. At frequencies closer to the loop bandwidth, the gain of the integrator is much smaller, and thus less input jitter can be tolerated. The AD807 output will have a bit error rate less than 1 × 10–10 when in lock and retiming input data that has the CCITT G.958 specified jitter applied to it. With a differential TIA (Figure 3), Sensitivity seems to improve from observing the Quantizer input with an oscilloscope probe. This is an illusion caused by the use of a single-ended probe. A 1 mV peak-to-peak signal appears to drive the AD807 Quantizer. However, the single-ended probe measures only half the signal. The true Quantizer input signal is twice this value since the other Quantizer input is a complementary signal to the signal being observed. Jitter Transfer (Refer to Figure 20) Response Time The AD807 exhibits a low-pass filter response to jitter applied to its input data. Response time is the delay between removal of the input signal and indication of Loss of Signal (LOS) at SDOUT. The response time of the AD807 (1.5 µs maximum) is much faster than the SONET/SDH requirement (3 µs ≤ response time ≤ 100 µs). In practice, the time constant of the ac coupling at the Quantizer input determines the LOS response time. Bandwidth This describes the frequency at which the AD807 attenuates sinusoidal input jitter by 3 dB. Peaking This describes the maximum jitter gain of the AD807 in dB. Nominal Center Frequency This is the frequency at which the VCO will oscillate with the loop damping capacitor, CD, shorted. –4– REV. A AD807 Damping Factor, ζ AVCC2 Damping factor, ζ describes the compensation of the second order PLL. A larger value of ζ corresponds to more damping and less peaking in the jitter transfer function. DIFFERENTIAL INPUT 400Ω 400Ω 1mA 0.5mA VBE ù 0.8V CURRENT SOURCES HEADROOM ≥ 0.7V 0.5mA Acquisition Time This is the transient time, measured in bit periods, required for the AD807 to lock onto input data from its free-running state. AVEE Symmetry—Recovered Clock Duty Cycle a. Quantizer Differential Input Stage Symmetry is calculated as (100 × on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its “0” level and its “1” level. 1.2V +VBE Bit Error Rate vs. Signal-to-Noise Ratio AD807 Bit Error Rate vs. Signal-to-Noise Ratio performance is shown in Figure 11. Wideband amplitude noise is summed with the input data signal as shown in Figure 4. Performance is shown for input data levels of 5 mV and 10 mV. 5.9kΩ THRADJ 94.6kΩ AVEE b. Threshold Adjust 2mVp-p VCM VCC1 EPITAXX ERM504 SCOPE PROBE AD807 QUANTIZER IOH 150Ω BINARY OUTPUT SDOUT 150Ω IOL VCM VEE c. Signal Detect Output (SDOUT) a. Single-Ended Input Application AD8015 DIFFERENTIAL OUTPUT TIA +OUT VCC2 1mVp-p VCM 450Ω SCOPE PROBE AD807 QUANTIZER 450Ω DIFFERENTIAL OUTPUT BINARY OUTPUT 2.5mA –OUT VEE d. PLL Differential Output Stage—DATAOUT(N), CLKOUT(N) Figure 5. (a–d) Simplified Schematics VCM b. Differential Input Application Figure 3. (a–b) Single-Ended and Differential Input Applications POWER COMBINER + ∑ DIFFERENTIAL SIGNAL SOURCE 0.47µF PIN + 50Ω D.U.T. AD807 POWER COMBINER + ∑ 0.47µF 50Ω NIN – POWER SPLITTER 100MHz 75Ω 1.0µF 100Ω +5V FILTER GND NOISE SOURCE Figure 4. Bit Error Rate vs. Signal-to-Noise Ratio Test: Block Diagram REV. A –5– AD807–Typical Characteristic Curves 200.0E+3 35.000E–3 RTHRESH = 0Ω 180.0E+3 30.000E–3 SIGNAL DETECT LEVEL – Volts 160.0E+3 RTHRESH – Ω 140.0E+3 120.0E+3 100.0E+3 80.0E+3 60.0E+3 40.0E+3 25.000E–3 20.000E–3 15.000E–3 10.000E–3 RTHRESH = 49.9k 5.000E–3 20.0E+3 0.0E+0 000.0E+0 RTHRESH = OPEN 000.000E+0 5.0E–3 10.0E–3 15.0E–3 20.0E–3 25.0E–3 30.0E–3 4.4 35.0E–3 4.6 4.8 5.0 5.2 SUPPLY VOLTAGE – Volts SIGNAL DETECT LEVEL – Volts Figure 6. Signal Detect Level vs. RTHRESH 8.00 RTHRESH = 0Ω 7.00 ELECTRICAL HYSTERESIS – dB SIGNAL DETECT LEVEL – Volts 30.0E–3 25.0E–3 20.0E–3 15.0E–3 10.0E–3 RTHRESH = 49.9k 5.0E–3 –20 0 20 40 60 TEMPERATURE – °C 80 5.00 RTHRESH = 49.9kΩ 4.00 RTHRESH = OPEN 3.00 2.00 4.8 5.0 5.2 POWER SUPPLY – V 4.6 9.00 1E-1 8.00 5E-2 3E-2 2E-2 RTHRESH = 0Ω 7.00 RTHRESH = 49.9k 5.00 RTHRESH = OPEN S 1 1 erfc 2 2 N 2 1E-3 1E-4 1278 NSN 1279 1276 1E-8 1E-10 1E-12 0 20 40 60 TEMPERATURE – °C 80 5.6 1E-2 1E-5 1E-6 4.00 –20 5.4 Figure 10. Signal Detect Hysteresis vs. Power Supply BIT ERROR RATE ELECTRICAL HYSTERESIS – dB 6.00 0.00 4.4 100 Figure 7. Signal Detect Level vs. Temperature 6.00 RTHRESH = 0Ω 1.00 RTHRESH = OPEN 3.00 –40 5.6 Figure 9. Signal Detect Level vs. Supply Voltage 35.0E–3 000.0E+0 –40 5.4 1277 100 10 Figure 8. Signal Detect Hysteresis vs. Temperature 12 14 16 18 S/N – dB 20 22 24 Figure 11. Bit Error Rate vs. Signal-to-Noise Ratio –6– REV. A AD807 30 25 PERCENTAGE – % XFCB’s dielectric isolation allows the different blocks within this mixed-signal IC to be isolated from each other, hence the 2 mV Sensitivity is achieved. Traditionally, high speed comparators are plagued by crosstalk between outputs and inputs, often resulting in oscillations when the input signal approaches 10 mV. The AD807 quantizer toggles at ± 650 µV (1.3 mV sensitivity) at the input without making bit errors. When the input signal is lowered below ± 650 µV, circuit performance is dominated by input noise, and not crosstalk. TEST CONDITIONS WORST CASE: – 40°C, 4.5V 20 15 10 0.1µF 5 PIN 13 0 1.4 500Ω 0.1µF 500Ω 1.5 1.6 1.7 1.8 1.9 2.0 RMS JITTER – Degrees 2.1 2.2 QUANTIZER INPUT NIN 12 2.3 50Ω 50Ω 309Ω OPTIONAL FILTER FERRITE BEAD 0.1µF 0.1µF 0.1µF 50Ω AD807 Figure 12. Output Jitter Histogram 3.65kΩ AVCC2 14 1E+3 311MHz NOISE INPUT CHOKE "BIAS TEE" 10µF 0.1µF +5V AVCC1 11 JITTER TOLERANCE – UI 0.1µF 100E+0 VCC1 6 VCC2 3 0.1µF 0.1µF 10E+0 AD807 Figure 15. Power Supply Noise Sensitivity Test Circuit 1E+0 0.1µF PIN 13 500Ω 0.1µF 500Ω SONET MASK QUANTIZER INPUT NIN 12 100E–3 10E+0 100E+0 10E+3 100E+3 1E+3 FREQUENCY – Hz 1E+6 10E+6 50Ω 50Ω 0.1µF 309Ω AD807 3.65kΩ Figure 13. Jitter Tolerance 0.1µF CHOKE "BIAS TEE" 50Ω AVCC2 14 3.0 0.1µF AVCC1 11 311MHz NOISE INPUT +5V 10µF 0.1µF JITTER – ns p-p PSR – NO FILTER 6 VCC2 3 0.1µF 2.0 0.1µF CMR Figure 16. Common-Mode Rejection Test Circuit 1.0 Signal Detect The input to the signal detect circuit is taken from the first stage of the quantizer. The input signal is first processed through a gain stage. The output from the gain stage is fed to both a positive and a negative peak detector. The threshold value is subtracted from the positive peak signal and added to the negative peak signal. The positive and negative peak signals are then compared. If the positive peak, POS, is more positive than the negative peak, NEG, the signal amplitude is greater than the threshold, and the output, SDOUT, will indicate the presence of signal by remaining low. When POS becomes more negative than NEG, the signal amplitude has fallen below the threshold, and SDOUT will indicate a loss of signal (LOS) by going high. The circuit provides hysteresis by adjusting the threshold level higher by a factor of two when the low signal level is detected. This means that the input data amplitude needs to reach twice the set LOS threshold before SDOUT will signal that the data is again valid. This corresponds to a 3 dB optical hysteresis. PSR – WITH FILTER 0 0 0.1 0.2 0.4 0.6 0.3 0.5 0.7 NOISE – Vp-p @311MHz 0.8 0.9 1.0 Figure 14. Output Jitter vs. Supply Noise and Output Jitter vs. Common Mode Noise THEORY OF OPERATION Quantizer The quantizer (comparator) has three gain stages, providing a net gain of 350. The quantizer takes full advantage of the Extra Fast Complementary Bipolar (XFCB) process. The input stage uses a folded cascode architecture to virtually eliminate pulse width distortion, and to handle input signals with commonmode voltage as high as the positive supply. The input offset voltage is factory trimmed and guaranteed to be less than 500 µV. REV. A VCC1 –7– AD807 AD807 PIN COMPARATOR STAGES & CLOCK RECOVERY PLL NIN THRESHOLD BIAS + + ∑ ITHR POSITIVE PEAK DETECTOR LEVEL SHIFT DOWN NEGATIVE PEAK DETECTOR LEVEL SHIFT UP A lower damping ratio allows a faster frequency acquisition; generally the acquisition time scales directly with the capacitor value. However, at damping ratios approaching one, the acquisition time no longer scales directly with capacitor value. The acquisition time has two components: frequency acquisition and phase acquisition. The frequency acquisition always scales with capacitance, but the phase acquisition is set by the loop bandwidth of the PLL and is independent of the damping ratio. Thus, the 0.06% fractional loop bandwidth sets a minimum acquisition time of 2000 bit periods. Note the acquisition time for a damping factor of one is 15,000 bit periods. This comprises 13,000 bit periods for frequency acquisition and 2,000 bit periods for phase acquisition. Compare this to the 400,000 bit periods acquisition time specified for a damping ratio of 5; this consists entirely of frequency acquisition, and the 2,000 bit periods of phase acquisition is negligible. IHYS SDOUT Figure 17. Signal Level Detect Circuit Block Diagram Phase-Locked Loop The phase-locked loop recovers clock and retimes data from NRZ data. The architecture uses a frequency detector to aid initial frequency acquisition; refer to Figure 18 for a block diagram. Note the frequency detector is always in the circuit. When the PLL is locked, the frequency error is zero and the frequency detector has no further effect. Since the frequency detector is always in the circuit, no control functions are needed to initiate acquisition or change mode after acquisition. DATA INPUT ΦDET S+1 ∑ While a lower damping ratio affords faster acquisition, it also allows more peaking in the jitter transfer response (jitter peaking). For example, with a damping ratio of 10, the jitter peaking is 0.02 dB, but with a damping ratio of 1, the peaking is 2 dB. Center Frequency Clamp (Figure 19) An N-channel FET circuit can be used to bring the AD807 VCO center frequency to within ± 10% of 155 MHz when SDOUT indicates a Loss of Signal (LOS). This effectively reduces the frequency acquisition time by reducing the frequency error between the VCO frequency and the input data frequency at clamp release. The N-FET can have “on” resistance as high as 1 kΩ and still attain effective clamping. However, the chosen N-FET should have greater than 10 MΩ “off” resistance and less than 100 nA leakage current (source and drain) so as not to alter normal PLL performance. 1 S VCO RECOVERED CLOCK OUTPUT FDET RETIMING DEVICE RETIMED DATA OUTPUT Figure 18. PLL Block Diagram The frequency detector delivers pulses of current to the charge pump to either raise or lower the frequency of the VCO. During the frequency acquisition process the frequency detector output is a series of pulses of width equal to the period of the VCO. These pulses occur on the cycle slips between the data frequency and the VCO frequency. With a maximum density data pattern (1010 . . . ), every cycle slip will produce a pulse at the frequency detector output. However, with random data, not every cycle slip produces a pulse. The density of pulses at the frequency detector output increases with the density of data transitions. The probability that a cycle slip will produce a pulse increases as the frequency error approaches zero. After the frequency error has been reduced to zero, the frequency detector output will have no further pulses. At this point the PLL begins the process of phase acquisition, with a settling time of roughly 2000 bit periods. N_FET CD 1 DATAOUTN VEE 16 2 DATAOUTP SDOUT 15 3 VCC2 AVCC2 14 4 CLKOUTN PIN 13 5 CLKOUTP NIN 12 6 VCC1 7 CF1 8 CF2 AVCC1 11 THRADJ 10 AVEE 9 AD807 Figure 19. Center Frequency Clamp Schematic CD 0.1 0.15 0.22 0.33 0.02dB/DIV Jitter caused by variations of density of data transitions (pattern jitter) is virtually eliminated by use of a new phase detector (patented). Briefly, the measurement of zero phase error does not cause the VCO phase to increase to above the average run rate set by the data frequency. The jitter created by a 27–1 pseudorandom code is 1/2 degree, and this is small compared to random jitter. The jitter bandwidth for the PLL is 0.06% of the center frequency. This figure is chosen so that sinusoidal input jitter at 92 kHz will be attenuated by 3 dB. 10 The damping ratio of the PLL is user programmable with a single external capacitor. At 155 MHz, a damping ratio of 5 is obtained with a 0.15 µF capacitor. More generally, the damping ratio scales as (fDATA × CD)1/2. 100 PEAK 0.12 0.08 0.06 0.04 1k FREQUENCY IN kHz 10k 20k Figure 20. Jitter Transfer vs. CD –8– REV. A AD807 C1 0.1µF R1 100Ω J1 C3 0.1µF DATAOUTN R2 100Ω R9 154Ω R5 100Ω R7 100Ω CLKOUTP J4 C6 0.1µF C8 R4 100Ω R11 154Ω C2 0.1µF SDOUT 1 DATAOUTN 2 DATAOUTP 3 VCC2 4 CLKOUTN PIN 13 5 CLKOUTP NIN 12 C7 R8 100Ω R3 100Ω J5 C12 0.1µF R6 100Ω DATAOUTP J2 C4 0.1µF J3 C5 0.1µF CLKOUTN TP7 TP8 50Ω STRIP LINE EQUAL LENGTH R10 154Ω TP1 R12 CD 154Ω TP2 6 VCC1 7 CF1 8 CF2 VEE 16 SDOUT 15 AVCC2 AVCC1 11 THRADJ 10 AVEE 9 AD807 R13 301Ω 14 R14 49.9Ω C9 PIN NIN C14 0.1µF J7 C10 TP5 VECTOR PINS SPACED FOR RN55C TYPE RESISTOR; COMPONENT SHOWN FOR REFERENCE ONLY TP6 NOTE: RTHRESH NOTE: INTERCONNECT RUN UNDER DUT C11 TP3 10µF TP4 +5V GND R16 3.65kΩ R15 49.9Ω C13 0.1µF J6 C7–C10 ARE 0.1µF BYPASS CAPACITORS RIGHT ANGLE SMA CONNECTOR OUTER SHELL TO GND PLANE VECTOR PINS SPACED THROUGH-HOLE CAPACITOR ON VECTOR CUPS; COMPONENT SHOWN FOR REFERENCE ONLY ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT TPxo TEST POINTS ARE VECTORBOARD K24A/M PINS Figure 21. Evaluation Board Schematic CIRCUIT SIDE 08-002901-02 REV A INT2 08-002901-08 REV A INT1 08-002901-07 REV A SILKSCREEN TOP 08-002901-03 REV A COMPONENT SIDE 08-002901-01 REV A SOLDERMASK TOP 08-002901-04 REV A Figure 22. Evaluation Board Pictorials REV. A –9– AD807 C1 0.1µF SDOUT TP7 DATAOUTN DATAOUTP C2 R1 R2 0.1µF 100 100 C3 0.1µF C4 0.1µF R5 100 R9 R10 154 154 R6 100 CLKOUTN R8 100 CLKOUTP C5 0.1µF R3 100 R4 100 C8 TP1 R11 154 R12 154 C6 0.1µF R17 3.65k SDOUT 15 C11 DATAOUTN 2 DATAOUTP 3 VCC2 4 CLKOUTN PIN 13 5 CLKOUTP NIN 12 6 VCC1 AVCC 11 7 CF1 THRADJ 10 8 CF2 AVEE 9 C7 R7 100 16 1 VEE AD807 TP6 R13 THRADJ TP5 0.8 A/W, 0.7pF 2.5GHz 0.01µF 10µF 1 NC +VS 8 2 IIN +OUT 7 3 NC –OUT 6 –VS 5 4 0.1µF C15 0.1µF 0.1µF ABB HAFO 1A227 FC HOUSING R15 50 C10 5V TP3 NOTES 1. ALL CAPS ARE CHIP, 15pF ARE MICA. 2. 150nH ARE SMT C13 0.1µF R14 50 C9 10µF GND TP4 R16 301 14 AVCC CD TP2 C12 2.2µF C14 0.1µF 50Ω LINE 50Ω LINE 150nH 15pF VBYP 150nH 15pF AD8015 NC = NO CONNECT Figure 23. Low Cost 155 Mbps Fiber Optic Receiver Schematic Table I. AD807—AD8015 Fiber Optic Receiver Circuit: Output Bit Error Rate & Output Jitter vs. Input Power Average Optical Input Power (dBm) Output Bit Error Rate –6.4 –6.5 –6.6 –6.7 Loses Lock 7.5 × 10–3 9.4 × 10–4 0 × 10–14 –7.0 to –35.5 –36.0 0 × 10–14 3 × 10–12 –36.5 –37.0 –38.0 –39.0 –39.2 –39.3 4.8 × 10–10 2.8 × 10–8 1.3 × 10–5 1.0 × 10–3 1.9 × 10–3 Loses Lock Output Jitter (ps rms) <40 <40 Figure 24. Receiver Output (Data) Eye Diagram, –7.0 dBm Optical Input APPLICATIONS Low Cost 155 Mbps Fiber Optic Receiver The AD807 and AD8015 can be used together for a complete 155 Mbps Fiber Optic Receiver (Quantizer and Clock Recovery, and Transimpedance Amplifier) as shown in Figure 23. The PIN diode front end is connected to a single mode 1300 nm laser source. The PIN diode has 3.3 V reverse bias, 0.8 A/W responsively, 0.7 pF capacitance, and 2.5 GHz bandwidth. The AD8015 outputs (POUT and NOUT) drive a differential, constant impedance (50 Ω) low-pass filter with a 3 dB cutoff of 100 MHz. The outputs of the low-pass filter are ac coupled to the AD807 inputs (PIN and NIN). The AD807 PLL damping factor is set at 7 using a 0.22 µF capacitor. –10– Figure 25. Receiver Output (Data) Eye Diagram, –36.0 dBm Optical Input REV. A AD807 C1 0.1µF SDOUT J1 J2 C2 R1 R2 0.1µF 100 100 C3 0.1µF C4 0.1µF R9 R10 154 154 R5 100 R6 100 R7 100 C7 0.1µF J3 R8 100 J4 C5 0.1µF R3 100 R4 100 R11 150 C8 0.1µF R12 150 CD 0.1µF C12 0.1 1 DATAOUTN 2 DATAOUTP VEE 16 3 VCC2 4 CLKOUTN PIN 13 5 CLKOUTP NIN 12 6 VCC1 AVCC1 11 7 CF1 THRADJ 10 8 CF2 AVEE 9 R14 47 14 AVCC2 C11 0.1 AD807 C6 0.1µF R16 330 SDOUT 15 C13 0.1 R15 47 C14 0.1 C10 R17 3.9k 120nH 30pF PIN TIA EPITAXX ERM504 2 1 1µF 30pF 0.1 3 NOISE FILTER NOTE PIN TIA PIN 4 (CASE) IS CONNECTED TO GROUND R13 THRADJ C9 10 +5V Figure 26. AD807 Application with Epitaxx PIN—Transimpedance Amplifier Module The entire circuit was enclosed in a shielded box. Table I summarizes results of tests performed using a 223-1 PRN Sequence, and varying the average power at the PIN diode. 250mV The circuit acquires and maintains lock with an average input power as low as –39.25 dBm. 50mV/ DIV Table II. AD807—Epitaxx ERM504 PIN TIA 155 Mbps Fiber Optic Receiver Circuit: Output Bit Error Rate & Output Jitter vs. Average Input Power Average Optical Input Power (dBm) Output Bit Error Rate Output Jitter (ps rms) 0 –3 –10 –20 –30 –32 –34 –35 –35.5 –36 –37.0 –37.6 –38.0 0.0 × 10 0.0 × 10–10 0.0 × 10–10 0.0 × 10–10 0.0 × 10–10 0.0 × 10–10 0.0 × 10–10 0.0 × 10–10 0.0 × 10–10 0.0 × 10–10 0.0 × 10–10 0.5 × 10–10 4 × 10–6 29 35 40 37 33 35 36 39 40 41 42 43 50 –10 –250mV 38.12ns 1ns/DIV 48.12ns Figure 27. Receiver Output (Data) Eye Diagram, 0 dBm Optical Input 250mV 50mV/ DIV SONET (OC-3)/SDH (STM-1) Fiber Optic Receiver Circuit A light wave receiver circuit for SONET/SDH application at 155 Mbps is shown in Figure 26, with test results given in Table II. The circuit operates from a single +5 V supply, and uses two major components: an Epitaxx ERM504 PIN-TIA module with AGC, and the AD807 IC. A 120 MHz, third order, low-pass Butterworth filter at the output of the PIN-TIA module provides adequate bandwidth (70% of the bit rate), and attenuates high frequency (out of band) noise. REV. A –11– –250mV 38.12ns 1ns/DIV 48.12ns Figure 28. Receiver Output (Data) Eye Diagram, –38 dBm Optical Input AD807 A simple P-channel FET circuit can be used in series with the Output Signal ECL Supply (VCC2, Pin 3) to squelch clock and data outputs when SDOUT indicates a loss of signal (Figure 29). The VCC2 supply pin draws roughly 61 mA (14 mA for each of 4 ECL loads, plus 5 mA for all 4 ECL output stages). This means that selection of a FET with ON RESISTANCE of 0.5 Ω will affect the common mode of the ECL outputs by only 31 mV. Use of one ground plane for connections to both analog and digital grounds is recommended. Power Supply Connections Use of a 10 µF capacitor between VCC and ground is recommended. Care should be taken to isolate the +5 V power trace to VCC2 (Pin 3). The VCC2 pin is used inside the device to provide the CLKOUT and DATAOUT signals. Use of 0.1 µF capacitors between IC power supply and ground is recommended. Power supply decoupling should take place as close to the IC as possible. Refer to the schematic, Figure 21, for recommended connections. TO VCC1, AVCC, AVCC2 5V P_FET Transmission Lines Use of 50 Ω transmission lines are recommended for PIN, NIN, CLKOUT, and DATAOUT signals. BYPASS CAP Terminations Termination resistors should be used for PIN, NIN, CLKOUT, and DATAOUT signals. Metal, thick film, 1% tolerance resistors are recommended. Termination resistors for the PIN, NIN signals should be placed as close as possible to the PIN, NIN pins. 1 DATAOUTN VEE 16 2 DATAOUTP SDOUT 15 3 VCC2 AVCC2 14 4 CLKOUTN PIN 13 5 CLKOUTP NIN 12 6 VCC1 7 CF1 8 CF2 AVCC1 11 THRADJ 10 AVEE 9 AD807 Connections from +5 V to load resistors for PIN, NIN, CLKOUT, and DATAOUT signals should be individual, not daisy chained. This will avoid crosstalk on these signals. C2044a–2–3/97 AD807 Output Squelch Circuit USING THE AD807 Ground Planes Figure 29. Squelch Circuit Schematic Loop Damping Capacitor, C D A ceramic capacitor may be used for the loop damping capacitor. Using a 0.15 µF, +20% capacitor for a damping factor of five provides < 0.1 dB jitter peaking. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Small Outline IC Package (R-16A) 16 9 0.1574 (4.00) 0.1497 (3.80) PIN 1 8 1 0.2440 (6.20) 0.2284 (5.80) 0.3937 (10.00) 0.3859 (9.80) 0.0196 (0.50) x 45 ° 0.0099 (0.25) 0.0098 (0.25) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) –12– 8° 0° PRINTED IN U.S.A. 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) 0.0160 (0.41) REV. A