SN54F299, SN74F299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS SDFS071A – MARCH 1987 – REVISED OCTOBER 1993 • • • • • description These 8-bit universal shift /storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1, OE2) inputs can be used to choose the modes of operation listed in the function table. SN54F299 . . . J PACKAGE SN74F299 . . . DW OR N PACKAGE (TOP VIEW) S0 OE1 OE2 G/QG E/QE C/QC A/QA QA′ CLR GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC S1 SL QH′ H/QH F/QF D/QD B/QB CLK SR SN54F299 . . . FK PACKAGE (TOP VIEW) OE2 OE1 S0 VCC S1 • Four Modes of Operation: Hold (Store) Shift Right Shift Left Load Data Operates With Outputs Enabled or at High Impedance 3-State Outputs Drive Bus Lines Directly Can Be Cascaded for N-Bit Word Lengths Direct Overriding Clear Applications: Stacked or Push-Down Registers Buffer Storage Accumulator Registers Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs G/QG E/QE C/QC A/QA QA′ 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 SL QH′ H/QH F/QF D/QD CLR GND SR CLK B/QB • Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but has no effect on clearing, shifting, or storage of data. The SN54F299 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74F299 is characterized for operation from 0°C to 70°C. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 SN54F299, SN74F299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS SDFS071A – MARCH 1987 – REVISED OCTOBER 1993 FUNCTION TABLE INPUTS MODE I/O PORTS CLR S1 S0 OE1† OE2† CLK SL SR A/QA B/QB C/QC D/QD Clear L L L X L H L X H L L X L L X X X X X X X X X X L L X L L X L L X Hold H H L X L X L L L L X L X X X X QA0 QA0 QB0 QB0 Shift Right H H L L H H L L L L ↑ ↑ X X H L H L Shift Left H H H H L L L L L L ↑ ↑ H L X X Load H H H X X ↑ X X OUTPUTS F/QF L L X G/QG H/QH QA′ QH′ L L X E/QE L L X L L X L L X L L L L L L QC0 QC0 QD0 QD0 QE0 QE0 QF0 QF0 QG0 QG0 QH0 QH0 QA0 QA0 QH0 QH0 QAn QAn QBn QBn QCn QCn QDn QDn QEn QEn QFn QFn QGn QGn H L QGn QGn QBn QBn QCn QCn QDn QDn QEn QEn QFn QFn QGn QGn QHn QHn H L QBn QBn H L a b c d e f g h a h NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputs are isolated from the I/O terminals. † When one or both output-enable inputs are high the eight I/O terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. logic symbol‡ 9 CLR OE1 OE2 S0 S1 CLK SR 2 & 3 1 19 SRG8 R 3EN5 0 M 1 0 3 12 C4/1→/2→ 11 7 A /QA 1,4D 8 3,4D QA′ 5 B/QB 13 3,4D 5 C/QC D/QD E/QE F/QF G/QG H/QH SL 6 14 5 15 4 16 18 3,4D 17 QH′ 5 2,4D ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54F299, SN74F299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS SDFS071A – MARCH 1987 – REVISED OCTOBER 1993 logic diagram (positive logic) S0 S1 SR (shift right serial input) CLK 1 19 18 11 Six Identical Channels Not Shown† 12 1D 1D C1 C1 R QA′ CLR OE1 OE2 SL (shift left serial input) R 8 17 QH′ 9 2 3 7 16 A /QA H /QH † I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4). absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . – 0.5 V to 5.5 V Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC Current into any output in the low state: QA′ or QH′ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA SN54F299 (QA thru QH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA SN74F299 (QA thru QH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Operating free-air temperature range: SN54F299 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74F299 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 SN54F299, SN74F299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS SDFS071A – MARCH 1987 – REVISED OCTOBER 1993 recommended operating conditions SN54F299 VCC VIH Supply voltage VIL IIK Low-level input voltage IOH High level output current High-level IOL Low level output current Low-level TA Operating free-air temperature High-level input voltage SN74F299 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 UNIT V V 0.8 0.8 V – 18 – 18 mA QA′ or QH′ –1 –1 QA thru QH –3 –3 QA′ or QH′ 20 20 QA thru QH 20 24 Input clamp current – 55 125 0 70 mA mA °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 4.5 V, II = – 18 mA IOH = – 1 mA VCC = 4.5 V IOH = – 1 mA IOH = – 3 mA QA′ or QH′ VOH QA thru QH Any output VCC = 4.75 V, QA′ or QH′ VOL II IIH‡ QA thru QH A thru H Any other A thru H Any other SN54F299 TYP† MAX TEST CONDITIONS VCC = 4.5 V MIN – 1.2 3.4 2.5 3.4 2.5 3.4 2.5 3.4 2.4 3.3 2.4 3.3 IOL = 20 mA IOL = 24 mA VI = 5.5 V VI = 7 V 5V VCC = 5 5.5 V, 7V VI = 2 2.7 VCC = 5.5 V, VI = 0.5 V A thru H IIL‡ S0 or S1 – 1.2 2.5 IOH = – 1 mA to – 3 mA IOL = 20 mA VCC = 5 5.5 5V SN74F299 TYP† MAX MIN Any other POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V 2.7 0.3 0.5 0.3 0.5 0.3 0.5 0.35 0.5 V 1 1 0.1 0.1 70 70 20 20 – 0.65 – 0.65 – 1.2 – 1.2 – 0.6 – 0.6 IOS§ VCC = 5.5 V, VO = 0 – 60 –150 – 60 ICC VCC = 5.5 V, See Note 2 68 95 68 † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: ICC is measured with OE1, OE2, and CLK at 4.5 V. 2–4 UNIT mA µA mA –150 mA 95 mA SN54F299, SN74F299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS SDFS071A – MARCH 1987 – REVISED OCTOBER 1993 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C SN54F299 SN74F299 UNIT ′F299 fclock tw tsu th Clock frequency Pulse duration Setu time before Setup CLK↑ Inactive-state setup time before CLK↑† Hold time after CLK↑ MIN MAX MIN MAX MIN MAX 0 70 0 65 0 70 CLK high or low 7 8 7 CLR low 7 8 7 S0 or S1 High or low 8.5 9.5 8.5 A/QA thru H/QH, SR, or SL High or low 5.5 6.5 5.5 CLR High 7 13 7 S0 or S1 High or low 0 0 0 A /QA thru H /QH, SR, or SL High or low 2 2 2 MHz ns ns ns † Inactive-state setup time is also referred to as recovery time. switching characteristics (see Note 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX‡ ′F299 fmax tPLH tPHL CLK QA′′ or QH′′ tPLH tPHL CLK QA thru QH tPHL CLR tPZH tPZL OE1 or OE2 QA thru QH tPHZ tPLZ OE1 or OE2 QA thru QH MIN TYP UNIT SN54F299 SN74F299 MAX MIN MAX MIN 65 MAX 70 100 3.2 6.6 9 2.7 10.5 3.2 70 10 MHz 2.7 6.1 8.5 2.2 10 2.7 9.5 3.2 6.6 9 2.7 11 3.2 10 4.2 8.1 11 3.7 12.5 4.2 12 QA′ or QH′ 3.7 7.1 9.5 3.2 11.5 3.7 10.5 QA thru QH 5.7 10.6 14 5 15.5 5.7 15 2.7 5.6 8 2.2 10.5 2.7 9 3.2 6.6 10 2.7 12 3.2 11 1.7 4.1 6 1.7 9 1.7 7 1.2 3.6 5.5 1.2 7.5 1.2 6.5 ns ns ns ns ns ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 3: Load circuits and waveforms are shown in Section 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5 SN54F299, SN74F299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS SDFS071A – MARCH 1987 – REVISED OCTOBER 1993 2–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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