SN54F175, SN74F175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993 • • • • SN54F175 . . . J PACKAGE SN74F175 . . . D OR N PACKAGE (TOP VIEW) Contain Four Flip-Flops With Double-Rail Outputs Buffered Clock and Direct Clear Inputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs CLR 1Q 1Q 1D 2D 2Q 2Q GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4Q 4Q 4D 3D 3Q 3Q CLK description SN54F175 . . . FK PACKAGE (TOP VIEW) 1Q CLR NC VCC 4Q These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR) input. Information at the data (D) inputs meeting setup time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4Q 4D NC 3D 3Q 2Q GND NC CLK 3Q 1Q 1D NC 2D 2Q The SN54F175 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74F175 is characterized for operation from 0°C to 70°C. NC – No internal connection FUNCTION TABLE OUTPUTS INPUTS CLR CLK D Q Q L X X L H H ↑ H H L H ↑ L L H H L X Q0 Q0 Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 SN54F175, SN74F175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993 logic symbol† CLR CLK 1 R 9 C1 2 1D 4 3 1D 7 2D 5 6 10 3D 12 1Q 2Q 2Q 3Q 11 15 4D 1Q 13 14 3Q 4Q 4Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) CLR CLK 1D 1 9 4 1D 2 1Q C1 3 R 1Q Two Identical Channels Not Shown 4D 13 1D 15 4Q C1 R Pin numbers shown are for the D, J, and N packages. 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14 4Q SN54F175, SN74F175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Operating free-air temperature range: SN54F175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74F175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed. recommended operating conditions SN54F175 VCC VIH Supply voltage VIL IIK Low-level input voltage IOH IOL High-level output current Low-level output current TA Operating free-air temperature High-level input voltage SN74F175 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 Input clamp current – 55 UNIT V V 0.8 0.8 V – 18 – 18 mA –1 –1 mA 20 20 mA 70 °C 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IIH IIL IOS§ ICC TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = – 18 mA IOH = – 1 mA VCC = 4.75 V, VCC = 4.5 V, IOH = – 1 mA IOL = 20 mA VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V VCC = 5.5 V, VCC = 5.5 V, VI = 0.5 V VO = 0 SN54F175 TYP‡ MAX MIN SN74F175 TYP‡ MAX MIN – 1.2 2.5 3.4 – 1.2 2.5 3.4 0.5 0.3 0.5 V 0.1 0.1 mA 20 20 µA – 0.6 mA –150 mA – 0.6 – 60 V V 2.7 0.3 UNIT –150 – 60 VCC = 5.5 V, See Note 2 22.5 34 22.5 34 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: ICC is measured with outputs open with 4.5 V applied to all data inputs after a momentary ground followed by 4.5 V applied to CLK. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 SN54F175, SN74F175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C SN54F175 SN74F175 UNIT ′F175 fclock tw tsu Clock frequency Pulse duration MIN MAX MIN MAX MIN MAX 0 100 0 100 0 100 CLK high 4 4 4 CLK low 5 5 5 CLR low 5 5 5 Setup time, data before CLK↑ High or low 3 3 3 Setup time, inactive state, data before CLK↑† CLR high 5 5 5 1 1 1 th Hold time, data after CLK↑ High or low † Inactive-state setup time is also referred to as recovery time. MHz ns ns ns switching characteristics (see Note 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX‡ ′F175 fmax tPLH tPHL tPLH tPHL CLK CLR SN54F175 SN74F175 MIN MIN MIN TYP 100 140 3.2 4.6 6.5 2.7 8.5 3.2 7.5 3.2 6.1 8.5 3.2 10.5 3.2 9.5 Q 3.2 6.1 8.5 3.2 10 3.2 9 Q 3.7 8.6 11.5 3.7 15 3.7 13 Q or Q MAX MAX 100 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 100 ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 3: Load circuits and waveforms are shown in Section 1. 2–4 UNIT MHz ns ns IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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