TI SN74LVT16245BDL

SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
D Members of the Texas Instruments
D
D
D
D
D
D
D
D
D
SN54LVT16245B . . . WD PACKAGE
SN74LVT16245B . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Widebus  Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC )
Support Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot
Insertion
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
description/ordering information
The ’LVT16245B devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
ORDERING INFORMATION
TOP-SIDE
MARKING
Tube
SN74LVT16245BDL
Tape and reel
SN74LVT16245BDLR
TSSOP − DGG
Tape and reel
SN74LVT16245BDGGR
LVT16245B
TVSOP − DGV
Tape and reel
SN74LVT16245BDGVR
VD245B
SSOP − DL
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
VFBGA − GQL
LVT16245B
SN74LVT16245BGQLR
VFBGA − ZQL (Pb-free)
Tape and reel
SN74LVT16245BZQLR
VD245B
−55°C to 125°C
CFP − WD
Tube
SNJ54LVT16245BWD
SNJ54LVT16245BWD
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright  2003, Texas Instruments Incorporated
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+&#)#("' +&* & &*% ") &.( '*$%&' ('!(*! /(**('0
*"!$#"' +*"#&'1 !"& '" '&#&(*-0 '#-$!& &'1 ") (-+(*(%&&*
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1
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
description/ordering information (continued)
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the devices so that the buses are
effectively isolated.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
GQL OR ZQL PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
1
2
3
4
5
6
A
A
1DIR
NC
NC
NC
NC
1OE
B
B
1B2
1B1
GND
GND
1A1
1A2
C
C
1B4
1B3
1A4
D
1B6
1B5
VCC
GND
1A3
D
VCC
GND
1A5
1A6
E
1B8
1B7
1A7
1A8
F
2B1
2B2
2A2
2A1
G
2B3
2B4
GND
GND
2A4
2A3
H
2B5
2B6
2A5
2B7
2B8
VCC
GND
2A6
J
VCC
GND
2A8
2A7
2DIR
NC
NC
NC
NC
2OE
E
F
G
H
J
K
K
NC − No internal connection
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
2
OPERATION
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
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•
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
1DIR
1
2DIR
48
1A1
25
1OE
47
2A1
2
24
2OE
36
13
1B1
2B1
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG, DGV, DL, and WD packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO: SN54LVT16245B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVT16245B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVT16245B . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVT16245B . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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•
3
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 4)
SN54LVT16245B
SN74LVT16245B
MIN
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0.8
0.8
Input voltage
5.5
5.5
V
IOH
IOL
High-level output current
−24
−32
mA
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
−55
High-level input voltage
2
Low-level output current
Outputs enabled
2
V
−40
V
µs/V
200
125
V
85
°C
NOTE 4: All unused inputs of the device must at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
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4
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•
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VCC = 2.7 V,
VCC = 2.7 V to 3.6 V,
II = −18 mA
IOH = −100 µA
VCC = 2.7 V,
IOH = −8 mA
IOH = −24 mA
VCC = 3 V
VOL
VCC = 3 V
VCC = 3.6 V,
VCC = 0 or 3.6 V,
Ioff
VCC = 3.6 V
SN74LVT16245B
TYP†
MAX
MIN
−1.2
VCC−0.2
2.4
−1.2
UNIT
V
VCC−0.2
2.4
V
2
2
0.2
0.2
IOL = 24 mA
IOL = 16 mA
0.5
0.5
0.4
0.4
IOL = 32 mA
IOL = 48 mA
0.5
0.5
V
0.55
IOL = 64 mA
VI = VCC or GND
II
A or B ports‡
MIN
IOH = −32 mA
IOL = 100 µA
VCC = 2.7 V
Control inputs
SN54LVT16245B
TYP†
MAX
TEST CONDITIONS
0.55
±1
±1
VI = 5.5 V
VI = 5.5 V
10
10
20
20
VI = VCC
VI = 0
5
1
−5
IOZPU
VCC = 0,
VI or VO = 0 to 4.5 V
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don’t care
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don’t care
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
∆ICC§
VCC = 3 V to 3.6, One input at VCC − 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
VO = 3 V or 0
Outputs high
Outputs low
Outputs disabled
4
µA
−5
±100
µA
±100*
±100
µA
±100*
±100
µA
0.19
0.19
5
5
0.19
0.19
0.2
0.2
mA
mA
4
pF
Cio
10
10
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ Unused pins at VCC or GND.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
pF
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+&#)#("' (*& !&1' 1"(- &.( '*$%&' *&&*2& & *1 "
#('1& "* !#"''$& && +*"!$# /"$ '"#&
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5
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVT16245B
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
OE
A or B
tPHZ
tPLZ
OE
A or B
VCC = 3.3 V
± 0.3 V
SN74LVT16245B
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
MIN
TYP†
MAX
4.5
4.6
1.5
2.3
3.3
3.7
4.4
3.9
1.3
2.1
3.3
3.5
0.5
6.5
6.6
1.5
2.8
4.5
5.3
0.5
5.4
6.2
1.6
2.9
4.6
5.2
1
6.8
7
2.3
3.7
5.1
5.5
1
6.2
6.3
2.2
3.5
5.1
5.4
MIN
MAX
0.5
0.5
MIN
tsk(o)
† All typical values are at VCC = 3.3 V, TA = 25°C.
0.5
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6
VCC = 2.7 V
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•
MIN
UNIT
MAX
ns
ns
ns
ns
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6V
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Open
500 Ω
2.7 V
LOAD CIRCUIT
1.5 V
Timing Input
0V
tw
tsu
2.7 V
1.5 V
Input
th
2.7 V
1.5 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
Input
1.5 V
0V
tPHL
tPLH
Output
Waveform 1
S1 at 6 V
(see Note B)
VOH
1.5 V
Output
1.5 V
VOL
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPLZ
tPZL
3V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOH
Output
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
tPHL
2.7 V
Output
Control
1.5 V
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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•
7
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74LVT16245BDGGRE4
ACTIVE
TSSOP
DGG
48
2000
74LVT16245BDGVRE4
ACTIVE
TVSOP
DGV
48
74LVT16245BDLRG4
ACTIVE
SSOP
DL
SN74LVT16245BDGGR
ACTIVE
TSSOP
SN74LVT16245BDGVR
ACTIVE
SN74LVT16245BDL
Pb-Free
(RoHS)
Lead/Ball Finish
MSL Peak Temp (3)
CU NIPDAU
Level-1-250C-UNLIM
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DGG
48
2000
CU NIPDAU
Level-1-250C-UNLIM
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT16245BDLG4
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT16245BDLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Pb-Free
(RoHS)
SN74LVT16245BGQLR
ACTIVE
VFBGA
GQL
56
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74LVT16245BGRDR
ACTIVE
LFBGA
GRD
54
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74LVT16245BZQLR
ACTIVE
VFBGA
ZQL
56
1000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
SN74LVT16245BZRDR
ACTIVE
LFBGA
ZRD
54
1000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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