SN74LVC1GU04 SINGLE INVERTER GATE www.ti.com SCES215T – APRIL 1999 – REVISED JANUARY 2007 FEATURES • • • • • • • • Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Unbuffered Output Max tpd of 3.7 ns at 3.3 V Low Power Consumption, 10-µA Max ICC • DBV PACKAGE (TOP VIEW) NC 1 A 2 GND 3 ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCK PACKAGE (TOP VIEW) NC 1 A 2 GND 3 VCC 5 DRL PACKAGE (TOP VIEW) NC 1 A 2 GND 3 VCC 5 5 VCC 4 Y Y 4 Y 4 YZP PACKAGE (BOTTOM VIEW) GND A DNU 3 4 Y YZV PACKAGE (BOTTOM VIEW) GND 2 3 Y A 1 4 VCC 2 1 5 VCC See mechanical drawings for dimensions. NC – No internal connection DNU – Do not use DESCRIPTION/ORDERING INFORMATION This single inverter gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1GU04 contains one inverter with an unbuffered output and performs the Boolean function Y = A. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2007, Texas Instruments Incorporated SN74LVC1GU04 SINGLE INVERTER GATE www.ti.com SCES215T – APRIL 1999 – REVISED JANUARY 2007 ORDERING INFORMATION PACKAGE (1) TA NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) –40°C to 85°C SOT (SOT-23) – DBV SOT (SC-70) – DCK SOT (SOT-553) – DRL (2) _ _ _CD_ SN74LVC1GU04YZVR ____ CD Reel of 3000 SN74LVC1GU04DBVR Reel of 250 SN74LVC1GU04DBVT Reel of 3000 SN74LVC1GU04DCKR Reel of 250 SN74LVC1GU04DCKT Reel of 4000 SN74LVC1GU04DRLR CU4_ CD_ CD_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). YZV: The actual top-side marking is on two lines. Line 1 has four characters to denote year, month, day, and assembly/test site. Line 2 has two characters which show the family and function code. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUT A OUTPUT Y H L L H LOGIC DIAGRAM (POSITIVE LOGIC) DBV, DCK, DRL, and YZP PACKAGE A 2 4 Y YZV PACKAGE A 2 TOP-SIDE MARKING (2) SN74LVC1GU04YZPR Reel of 3000 NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZV (Pb-free) (1) ORDERABLE PART NUMBER 1 3 Submit Documentation Feedback Y SN74LVC1GU04 SINGLE INVERTER GATE www.ti.com SCES215T – APRIL 1999 – REVISED JANUARY 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range VI Input voltage range (2) (2) (3) RATING UNIT –0.5 to 6.5 V 0.5 to 6.5 V VO Voltage range applied to any output in the high or low state –0.5 to VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCC or GND ±100 mA θJA Tstg (1) (2) (3) (4) Package thermal impedance (4) DBV package 206 DCK package 252 DRL package 142 YZP package 132 YZV package 116 Storage temperature range °C/W °C –65 to 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) MIN MAX 1.65 5.5 UNIT VCC Supply voltage VIH High-level input voltage IO = –100 µA VIL Low-level input voltage IO = 100 µA 0.25 × VCC V VI Input voltage 0 5.5 V VO Output voltage 0 VCC V 0.75 × VCC VCC = 1.65 V High-level output current –8 –16 VCC = 3 V Low-level output current –32 VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 3 V (1) Operating free-air temperature mA 24 VCC = 4.5 V TA mA –24 VCC = 4.5 V IOL V –4 VCC = 2.3 V IOH V 32 –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback 3 SN74LVC1GU04 SINGLE INVERTER GATE www.ti.com SCES215T – APRIL 1999 – REVISED JANUARY 2007 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –100 µA VOH VIL = 0 V 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 VOL VIH = VCC 4.5 V IOL = 100 µA 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 32 mA A input VI = 5.5 V or GND, Ci VI = VCC or GND (1) 0.4 IO = 0 V 0.55 4.5 V 0.55 0 to 5.5 V ±5 µA 1.65 V to 5.5 V 10 µA VI = 5.5 V or GND ICC 3.8 3V IOL = 24 mA II 2.3 IOH = –32 mA IOL = 16 mA UNIT V 2.4 3V IOH = –24 mA MAX VCC – 0.1 IOH = –4 mA IOH = –16 mA TYP (1) MIN 3.3 V 7 pF All typical values are at VCC = 3.3 V, TA = 25°C. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (See Figure 1) PARAMETER FROM (INPUT) TO (INPUT) A Y tpd VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 1.3 5 1 4 1.1 3.7 1 3 ns Operating Characteristics TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 9 11 13 27 Submit Documentation Feedback UNIT pF SN74LVC1GU04 SINGLE INVERTER GATE www.ti.com SCES215T – APRIL 1999 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 5 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74LVC1GU04DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC1GU04DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC1GU04DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC1GU04DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC1GU04DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC1GU04DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC1GU04DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC1GU04DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC1GU04DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1GU04DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1GU04DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1GU04DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1GU04DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1GU04DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1GU04YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74LVC1GU04YZVR ACTIVE DSBGA YZV 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2008 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Sep-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ SN74LVC1GU04DBVR SOT-23 3000 178.0 9.0 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1GU04DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1GU04DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1GU04DCKR SC70 DCK 5 3000 180.0 9.2 2.24 2.34 1.22 4.0 8.0 Q3 SN74LVC1GU04DCKT SC70 DCK 5 250 180.0 9.2 2.24 2.34 1.22 4.0 8.0 Q3 SN74LVC1GU04DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1GU04DRLR SOT DRL 5 4000 180.0 9.2 1.78 1.78 0.69 4.0 8.0 Q3 SN74LVC1GU04YZPR DSBGA YZP 5 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1 SN74LVC1GU04YZVR DSBGA YZV 4 3000 180.0 8.4 1.02 1.02 0.63 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Sep-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1GU04DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1GU04DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1GU04DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1GU04DCKR SC70 DCK 5 3000 205.0 200.0 33.0 SN74LVC1GU04DCKT SC70 DCK 5 250 205.0 200.0 33.0 SN74LVC1GU04DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1GU04DRLR SOT DRL 5 4000 202.0 201.0 28.0 SN74LVC1GU04YZPR DSBGA YZP 5 3000 220.0 220.0 34.0 SN74LVC1GU04YZVR DSBGA YZV 4 3000 220.0 220.0 34.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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