[ /Title (CD74H C42, CD74H CT42) /Subject (High Speed CMOS Logic BCD To Deci- CD54HC42, CD74HC42, CD74HCT42 Data sheet acquired from Harris Semiconductor SCHS133C High-Speed CMOS Logic BCD-to-Decimal Decoders (1 of 10) August 1997 - Revised May 2003 Features Description • Buffered Inputs and Outputs The ’HC42 and CD74HCT42 BCD-to-Decimal Decoders utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL decoders with the low power consumption of standard CMOS integrated circuits. These devices have the capability of driving 10 LSTLL loads and are compatible with the standard LS logic family. One of ten outputs (low on select) is selected in accordance with the BCD input. Non-valid BCD inputs result in none of the outputs being selected (all outputs are high). • Typical Propagation Delay: 12ns at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times Ordering Information • Significant Power Reduction Compared to LSTTL Logic ICs PART NUMBER TEMP. RANGE (oC) PACKAGE • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V CD54HC42F3A -55 to 125 16 Ld CERDIP CD74HC42E -55 to 125 16 Ld PDIP CD74HC42M -55 to 125 16 Ld SOIC • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HCT42E -55 to 125 16 Ld PDIP Pinout CD54HC42 (CERDIP) CD74HC42 (PDIP, SOIC) CD74HCT42 (PDIP) TOP VIEW Y0 1 16 VCC Y1 2 15 A0 Y2 3 14 A1 Y3 4 13 A2 Y4 5 12 A3 Y5 6 11 Y9 Y6 7 10 Y8 GND 8 9 Y7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003 Texas Instruments Incorporated. 1 CD54HC42, CD74HC42, CD74HCT42 Functional Diagram 1 A0 A1 A2 A3 15 2 14 3 13 4 12 5 6 7 9 10 11 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 TRUTH TABLE INPUTS OUTPUTS A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 L L L L L H H H H H H H H H L L L H H L H H H H H H H H L L H L H H L H H H H H H H L L H H H H H L H H H H H H L H L L H H H H L H H H H H L H L H H H H H H L H H H H L H H L H H H H H H L H H H L H H H H H H H H H H L H H H L L L H H H H H H H H L H H L L H H H H H H H H H H L H L H L H H H H H H H H H H H L H H H H H H H H H H H H H H L L H H H H H H H H H H H H L H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H H H H H H H = High Voltage Level, L = Low Voltage Level 2 CD54HC42, CD74HC42, CD74HCT42 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 CD54HC42, CD74HC42, CD74HCT42 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS All 1 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g. 360µA max at 25oC. Switching Specifications Input tr, tf = 6ns PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns 6 - - 26 - 33 - 38 ns HC TYPES Propagation Delay, Input to Y (Figure 1) Any Input to Y tPLH, tPHL CL = 15pF 5 - 12 - - - - - ns Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns - - - 10 - 10 - 10 pF Input Capacitance CIN - 4 CD54HC42, CD74HC42, CD74HCT42 Switching Specifications Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC -55oC TO 125oC PARAMETER SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Power Dissipation Capacitance (Notes 3, 4) CPD - 5 - 65 - - - - - pF Propagation Delay, Input to Y (Figure 2) tPLH, tPHL CL = 50pF 4.5 - - 35 - 44 - 53 ns Any Input to Y tPLH, tPHL CL = 15pF 5 - 14 - - - - - ns Output Transition Time (Figure 2) tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns Input Capacitance CIN - - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD - 5 - 70 - - - - - pF HCT TYPES NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPLH tPHL FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 5 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type CD54HC42F3A ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC CD74HC42E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC42M ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HCT42E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. 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