ETC CD54HCT30F3A

[ /Title
(CD54H
C30,
CD74H
C30,
CD74H
CT30)
/Subject
(High
Speed
CMOS
Logic 8-
CD54/74HC30,
CD54/74HCT30
Data sheet acquired from Harris Semiconductor
SCHS121B
High Speed CMOS Logic
8-Input NAND Gate
August 1997 - Revised March 2002
Features
Description
• Buffered Inputs
The ’HC30 and ’HCT30 each contain an 8-input NAND gate
in one package. They provide the system designer with the
direct implementation of the positive logic 8-input NAND
function. Logic gates utilize silicon gate CMOS technology to
achieve operating speeds similar to LSTTL gates with the
low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads.
The HCT logic family is functionally pin compatible with the
standard LS logic family.
• Typical Propagation Delay: 10ns at VCC = 5V,
CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
PART NUMBER
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
TEMP. RANGE
(oC)
PACKAGE
CD54HC30F
-55 to 125
14 Ld CERDIP
CD54HC30F3A
-55 to 125
14 Ld CERDIP
CD74HC30E
-55 to 125
14 Ld PDIP
CD74HC30M
-55 to 125
14 Ld SOIC
CD54HC30NSR
-55 to 125
14 Ld SOP
CD54HCT30F3A
-55 to 125
14 Ld CERDIP
CD54HCT30H
-55 to 125
Die
CD74HCT30E
-55 to 125
14 Ld PDIP
CD74HCT30M
-55 to 125
14 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local TI sales office or customer service for ordering information.
Pinout
CD54HC30, CD54HCT30 (CERDIP)
CD74HC30 (PDIP, SOIC, SOP)
CD74HCT30 (PDIP, SOIC)
TOP VIEW
A
1
14 VCC
B
2
13 NC
C
3
12 H
D
4
11 G
E
5
10 NC
F
6
9
NC
GND
7
8
Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2002, Texas Instruments Incorporated.
1
CD54/74HC30, CD54/74HCT30
Functional Diagram
1
A
2
B
3
C
4
D
5
E
6
F
11
G
12
H
8
Y
Y = ABCDEFGH
TRUTH TABLE
INPUTS
A
B
C
D
E
F
G
H
OUTPUT
L
X
X
X
X
X
X
X
H
X
L
X
X
X
X
X
X
H
X
X
L
X
X
X
X
X
H
X
X
X
L
X
X
X
X
H
X
X
X
X
L
X
X
X
H
X
X
X
X
X
L
X
X
H
X
X
X
X
X
X
L
X
H
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
L
NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Irrelevant
Logic Symbol
1
A
B
C
D
E
2
3
4
8
Y
5
6
F
G
H
11
12
2
CD54/74HC30, CD54/74HCT30
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Package Thermal Impedance, θJA (see Note 3)
PDIP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W
SOIC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86oC/W
SOP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76oC/W
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
25oC
IO (mA) VCC (V)
-40oC TO +85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
HC TYPES
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC or
GND
-
-
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
-
6
-
-
±0.1
-
±1
-
±1
µA
3
CD54/74HC30, CD54/74HCT30
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
ICC
VCC or
GND
0
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
PARAMETER
Quiescent Device
Current
25oC
IO (mA) VCC (V)
-40oC TO +85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
6
-
-
2
-
20
-
40
µA
-
4.5 to
5.5
2
-
-
2
-
2
-
V
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
VIH or
VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1
-
±1
-
±1
µA
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC
and
GND
-
5.5
-
ICC
VCC or
GND
0
5.5
-
-
2
-
20
-
40
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
All
0.6
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
130
-
165
-
195
ns
4.5
-
-
26
-
33
-
39
ns
6
-
-
22
-
28
-
33
ns
5
-
10
-
-
-
-
-
ns
HC TYPES
Propagation Delay, Input to
Output (Figure 1)
Propagation Delay, Data Input to
Output Y
tPLH, tPHL
CL = 15pF
4
CD54/74HC30, CD54/74HCT30
Switching Specifications Input tr, tf = 6ns
PARAMETER
Transition Times (Figure 1)
Input Capacitance
Power Dissipation Capacitance
(Notes 5, 6)
(Continued)
SYMBOL
TEST
CONDITIONS
tTLH, tTHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
25
-
-
-
-
-
pF
HCT TYPES
Propagation Delay, Input to
Output (Figure 2)
tRHL, tPHL
CL = 50pF
4.5
-
-
28
-
35
-
42
ns
Propagation Delay, Data Input to
Output Y
tPLH, tPHL
CL = 15pF
5
-
11
-
-
-
-
-
ns
Transition Times (Figure 2)
tTLH, tTHL
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 5, 6)
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
26
-
-
-
-
-
pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per gate.
6. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
tr = 6ns
tf = 6ns
90%
50%
10%
INPUT
GND
tTLH
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
tPHL
tf = 6ns
tr = 6ns
VCC
tTLH
90%
1.3V
10%
INVERTING
OUTPUT
tPHL
tPLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
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