TPS727xx www.ti.com SBVS128B – JUNE 2009 – REVISED APRIL 2010 250mA, Ultralow IQ, Fast Transient Response, RF LOW-DROPOUT LINEAR REGULATOR FEATURES DESCRIPTION • Very Low Dropout: – 65mV Typical at 100mA – 130mV Typical at 200mA – 163mV Typical at 250mA • 2% Accuracy Over Load/Line/Temperature • Ultralow IQ: 7.9mA • Excellent Load Transient Performance:±50mV for 200mA Loading/Unloading Transient • Available in Fixed-Output Voltages From 0.9V to 5V Using Innovative Factory EEPROM Programming • High PSRR: 70dB at 1kHz • Stable with a 1.0mF Ceramic Capacitor • Thermal Shutdown and Overcurrent Protection • Available in 4-Ball, 0,4mm Pitch Wafer-Level Chip Scale and 1,5mm x 1,5mm SON Packages The TPS727xx family of low-dropout (LDO) linear regulators are ultralow quiescent current LDOs with excellent line and ultra-fast load transient performance and are designed for power-sensitive applications. The LDO output voltage level is preset by the use of innovative factory EEPROM programming. A precision bandgap and error amplifier provides overall 2% accuracy over load, line, and temperature extremes. The TPS727xx family is available in 1,5mm x 1,5mm SON and wafer chip-scale (WCSP) packages that make it ideal for handheld applications. This family of devices is fully specified over a temperature range of TJ = –40°C to +125°C. 1 234 YFF PACKAGE WCSP-4 (Top View) OUT GND B2 B1 A2 APPLICATIONS • • • • • DSE PACKAGE 1,5mm ´ 1,5mm SON-6 (Top View) OUT 1 6 IN NC 2 5 NC GND 3 4 EN A1 IN EN Wireless Handsets, Smart Phones, PDAs MP3 Players and Other Handheld Products Wireless LAN, Bluetooth®, Zigbee® Remote Controls Portable Consumer Products space TYPICAL APPLICATION CIRCUIT VIN IN OUT CIN COUT VOUT 1mF Ceramic TPS727xx On EN Off GND GROUND PIN CURRENT vs TEMPERATURE PSRR vs FREQUENCY 15 90 12 80 VIN = 2.1V IOUT = 0mA 70 IOUT = 10mA 60 IGND (mA) Power-Supply Rejection Ratio (dB) 100 50 40 9 6 30 20 3 10 IOUT = 200mA 0 0 10 100 1k 10k 100k Frequency (Hz) 1M 10M -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a registered trademark of Bluetooth SIG. Zigbee is a registered trademark of Zigbee Alliance. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated TPS727xx SBVS128B – JUNE 2009 – REVISED APRIL 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT VOUT TPS727xxx yyy z (1) (2) (2) XXX is the nominal output voltage. YYY is package designator. Z is package tape and reel quantity (R = 3000, T = 250). For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Output voltages from 0.9V to 5.0V in 50mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS (1) At TJ = –40°C to +125°C (unless otherwise noted). All voltages are with respect to GND. PARAMETER TPS727xx UNIT –0.3 to +6.0 V Enable voltage range, VEN –0.3 to +6.0 (2) V Output voltage range, VOUT –0.3 to +6.0 V Input voltage range, VIN Maximum output current, IOUT Internally limited Output short-circuit duration Indefinite Total continuous power dissipation, PDISS See Dissipation Ratings Table Human body model (HBM) ESD rating 2 kV 500 V Operating junction temperature range, TJ –55 to +150 °C Storage temperature range, TSTG –55 to +150 °C (1) (2) Charged device model (CDM) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. VEN absolute maximum rating is VIN or 6.0V, whichever is less. DISSIPATION RATINGS BOARD PACKAGE RqJC RqJA DERATING FACTOR ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°C High-K (1) DSE — 206°C/W 4.85mW/°C 485mW 269mW 194mW High-K (1) YFF 85°C/W 268°C/W 3.7mW/°C 370mW 205mW 150mW (1) 2 The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated TPS727xx www.ti.com SBVS128B – JUNE 2009 – REVISED APRIL 2010 ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.0V, whichever is greater; IOUT = 10mA, VEN = 0.9V, and COUT = 1.0mF, unless otherwise noted. Typical values are at TJ = +25°C. TPS727xx PARAMETER TEST CONDITIONS MIN MAX UNIT Input voltage range 2.0 5.5 VO Output voltage range 0.9 5.0 V TJ = +25°C –2.5 +2.5 mV VOUT + 0.3V ≤ VIN ≤ 5.5V, 0mA ≤ IOUT ≤ 200mA –2.0 +2.0 % VOUT (1) DC output accuracy VOUT + 0.3V ≤ VIN ≤ 5.5V, 0mA ≤ IOUT ≤ 250mA ΔVOUT ΔVO/ΔVIN Load transient Line regulation ΔVO/ΔIOUT Load regulation VDO Dropout voltage (2) ICL Output current limit IGND Ground pin current ISHDN PSRR Shutdown current (IGND) Power-supply rejection ratio ±1.0 V ±1.0 % 1mA to 200mA or 200mA to 1mA in 1ms, COUT = 1mF ±50.0 mV 1mA to 250mA or 250mA to 1mA in 1ms, COUT = 1mF ±65 mV VOUT(NOM) + 0.3V ≤ VIN ≤ 5.5V, IOUT = 10mA 8 mV/V 0mA ≤ IOUT ≤ 250mA 20 mV/mA VIN = 0.98 × VOUT(NOM), IOUT = 10mA 6.5 mV VIN = 0.98 × VOUT(NOM), IOUT = 50mA 32.5 mV 65 mV VIN = 0.98 × VOUT(NOM), IOUT = 100mA VIN = 0.98 × VOUT(NOM), IOUT = 200mA 130 VIN = 0.98 × VOUT(NOM), IOUT = 250mA 162.5 VOUT = 0.9 × VOUT(NOM) mV mV 400 550 mA IOUT = 0mA, TJ = –40°C to +125°C 7.9 12 mA IOUT = 200mA 110 mA IOUT = 250mA 130 mA VEN ≤ 0.4V, VIN = 2V, TJ = +25°C 0.12 mA VEN ≤ 0.4V, 2.0V < VIN ≤ 4.5V, TJ = –40°C to +85°C 0.55 VIN = 2.3V, VOUT = 1.8V, IOUT = 10mA 300 200 2 mA f = 10Hz 85 dB f = 100Hz 75 dB f = 1kHz 70 dB f = 10kHz 55 dB f = 100kHz 40 dB f = 1MHz 45 dB VN Output noise voltage BW = 100Hz to 100kHz, VIN = 2.1V, VOUT = 1.8V, IOUT = 10mA tSTR Startup time (3) COUT = 1.0mF, 0 ≤ IOUT ≤ 250mA VHI Enable pin high (enabled) 0.9 VIN V VLO Enable pin low (disabled) 0 0.4 V IEN Enable pin current EN = 5.5V 40 500 nA Undervoltage lock-out VIN rising 1.90 1.95 UVLO (1) (2) (3) TYP VIN TSD Thermal shutdown temperature TJ Operating junction temperature 33.5 mVRMS 100 1.85 Shutdown, temperature increasing ms +160 Reset, temperature decreasing +140 –40 V °C °C +125 °C The output voltage is programmed at the factory. VDO is measured for devices with VOUT(NOM) ≥ 2.35V so that VIN ≥ 2.3V. Startup time: Time from EN assertion to 0.98 × VOUT(NOM). Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS727xx SBVS128B – JUNE 2009 – REVISED APRIL 2010 www.ti.com DEVICE INFORMATION IN OUT Current Limit Thermal Shutdown UVLO EEPROM Bandgap EN LOGIC Figure 1. Functional Block Diagram PIN CONFIGURATIONS space YFF PACKAGE WCSP-4 (TOP VIEW) Note: OUT GND B2 B1 A2 A1 IN EN DSE PACKAGE 1,5mm × 1,5mm SON-6 (TOP VIEW) OUT 1 6 IN NC 2 5 NC GND 3 4 EN EN pin marked with dot on YFF package. PIN DESCRIPTIONS TPS727xx 4 NAME YFF DSE DESCRIPTION OUT B2 1 Regulated output voltage pin. A small 1mF ceramic capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. NC — 2 No connection. This pin can be tied to to ground to improve thermal dissipation. GND B1 3 Ground pin. EN A1 4 Enable pin. Driving EN over 0.9V turns on the regulator. Driving EN below 0.4V puts the regulator into shutdown mode, thus reducing the operating current to 120nA, nominal. NC — 5 No connection. This pin can be tied to to ground to improve thermal dissipation. IN A2 6 Input pin. A small capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated TPS727xx www.ti.com SBVS128B – JUNE 2009 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.0V, whichever is greater; IOUT = 10mA, VEN = VIN, and COUT = 1.0mF, unless otherwise noted. Typical values are at TJ = +25°C. LINE REGULATION (TPS72718) 1.90 1.90 IOUT = 10mA IOUT = 200mA 1.88 1.86 1.86 1.84 1.84 1.82 1.82 VOUT (V) VOUT (V) 1.88 LINE REGULATION (TPS72718) 1.80 1.78 1.76 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 2.1 2.6 3.1 3.6 4.1 4.6 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 5.1 5.6 2.1 2.6 3.1 3.6 VIN (V) Figure 2. Figure 3. LOAD REGULATION UNDER LIGHT LOADS (TPS72718) LOAD REGULATION (TPS72718) 1.90 1.90 0mA £ IOUT £ 10mA 1.88 4.6 5.1 5.6 0mA £ IOUT £ 250mA 1.88 1.86 1.86 1.84 1.84 1.82 1.82 VOUT (V) VOUT (V) 4.1 VIN (V) 1.80 1.78 1.76 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 0 1 2 3 4 5 6 7 IOUT (mA) Figure 4. Copyright © 2009–2010, Texas Instruments Incorporated 8 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 9 10 0 25 50 75 100 125 150 175 200 225 250 IOUT (mA) Figure 5. Submit Documentation Feedback 5 TPS727xx SBVS128B – JUNE 2009 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.0V, whichever is greater; IOUT = 10mA, VEN = VIN, and COUT = 1.0mF, unless otherwise noted. Typical values are at TJ = +25°C. DROPOUT VOLTAGE vs INPUT VOLTAGE (TPS72750) 160 160 140 140 120 120 100 100 VDO (mV) VDO (mV) DROPOUT VOLTAGE vs OUTPUT CURRENT (TPS72750) 80 60 40 50 100 150 60 +125°C +85°C +25°C -40°C 20 0 0 80 40 +125°C +85°C +25°C -40°C 20 IOUT = 200mA 200 0 2.25 250 2.75 3.25 IOUT (mA) Figure 7. OUTPUT VOLTAGE vs TEMPERATURE (TPS72718) GROUND PIN CURRENT vs INPUT VOLTAGE (TPS72718) 1.90 12.0 1.88 11.5 1.86 11.0 1.80 1.78 IOUT = 200mA 1.76 IOUT = 0mA +125°C +85°C +25°C -40°C 10.5 IOUT = 10mA 1.82 IGND (mA) VOUT (V) 4.75 4.25 Figure 6. 1.84 10.0 9.5 9.0 8.5 1.74 8.0 1.72 7.5 1.70 7.0 -40 -25 -10 5 20 35 50 65 Temperature (°C) Figure 8. 6 3.75 VIN (V) Submit Documentation Feedback 80 95 110 125 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6 VIN (V) Figure 9. Copyright © 2009–2010, Texas Instruments Incorporated TPS727xx www.ti.com SBVS128B – JUNE 2009 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.0V, whichever is greater; IOUT = 10mA, VEN = VIN, and COUT = 1.0mF, unless otherwise noted. Typical values are at TJ = +25°C. GROUND PIN CURRENT vs LOAD (TPS72718) GROUND PIN CURRENT vs TEMPERATURE (TPS72718) 15 140 VIN = 2.1V IOUT = 0mA 0mA £ IOUT £ 250mA 120 12 IGND (mA) IGND (mA) 100 80 60 +125°C +85°C +25°C -40°C 40 20 9 6 3 0 0 0 25 50 75 100 125 150 175 200 225 250 -40 -25 -10 5 20 50 65 80 95 110 125 Figure 10. Figure 11. SHUTDOWN CURRENT vs INPUT VOLTAGE (TPS72718) CURRENT LIMIT vs INPUT VOLTAGE (TPS72718) 550 2.0 +125°C +85°C +25°C -40°C 1.6 500 1.2 ILIM (mA) IGND (mA) 35 Temperature (°C) IOUT (mA) 0.8 450 400 0.4 350 0 2.0 2.5 3.0 3.5 4.0 4.5 VIN (V) Figure 12. Copyright © 2009–2010, Texas Instruments Incorporated 5.0 5.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) Figure 13. Submit Documentation Feedback 7 TPS727xx SBVS128B – JUNE 2009 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.0V, whichever is greater; IOUT = 10mA, VEN = VIN, and COUT = 1.0mF, unless otherwise noted. Typical values are at TJ = +25°C. PSRR vs FREQUENCY (VIN – VOUT = 0.5V, TPS72718) PSRR vs FREQUENCY (VIN – VOUT = 0.3V, TPS72718) 100 90 80 70 IOUT = 10mA 60 50 40 30 20 10 IOUT = 200mA Power-Supply Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 100 90 80 70 60 IOUT = 10mA 50 40 30 20 10 0 IOUT = 200mA 0 10 100 1k 10k 100k 1M 10 10M 100 1k Frequency (Hz) PSRR vs INPUT VOLTAGE (TPS72718) OUTPUT SPECTRAL NOISE DENSITY vs OUTPUT VOLTAGE (TPS72718) 10M 10.00 Noise Spectral Density (mV/ÖHz) Power-Supply Rejection Ratio (dB) 1M Figure 15. 70 60 50 40 30 20 1kHz 10kHz 100kHz 10 1.00 0.10 0.01 0 0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 IOUT = 10mA CIN = COUT = 1mF 10 2.8 100 1k VIN (V) 10k 100k 1M Figure 16. Figure 17. LOAD TRANSIENT RESPONSE: 0.1mA TO 200mA (TPS72718) LOAD TRANSIENT RESPONSE: 1mA TO 200mA (TPS72718) VIN = 2.3V tR = tF = 1ms VIN = 2.3V tR = tF = 1ms 100mA/div 200mA IOUT 0.1mA IOUT 1mA 50mV/div 50mV/div VOUT VOUT 100ms/div 50ms/div Figure 18. Figure 19. Submit Documentation Feedback 10M Frequency (Hz) 200mA 100mA/div 100k Figure 14. 80 8 10k Frequency (Hz) Copyright © 2009–2010, Texas Instruments Incorporated TPS727xx www.ti.com SBVS128B – JUNE 2009 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.0V, whichever is greater; IOUT = 10mA, VEN = VIN, and COUT = 1.0mF, unless otherwise noted. Typical values are at TJ = +25°C. LOAD TRANSIENT RESPONSE: 10mA TO 200mA (TPS72718) VIN = 2.3V tR = tF = 1ms 2mV/div 10mA 50mV/div VOUT VOUT 2.7V VIN 0.5V/div 100mA/div 200mA IOUT LINE TRANSIENT RESPONSE (TPS72718) Slew Rate = 1V/ms IOUT =100mA 2.1V 1ms/div 50ms/div Figure 20. Figure 21. LINE TRANSIENT RESPONSE (TPS72718) VIN INRUSH CURRENT (TPS72718) 1V/div 1V/div EN 5mV/div VOUT VOUT VIN = 2.1V VOUT = 1.8V IOUT = 100mA 0.5V/div Slew Rate = 1V/ms IOUT = 200mA 2.1V 50mA/div 2.7V VIN IIN 20ms/div 100ms/div Figure 22. Figure 23. VIN INRUSH CURRENT (TPS72718) VIN RAMP UP, RAMP DOWN RESPONSE (TPS72718) IOUT = 200mA 100mA/div VIN VOUT 1V/div 1V/div 1V/div EN VOUT VIN = 2.1V VOUT = 1.8V IOUT = 200mA IIN 20ms/div Figure 24. Copyright © 2009–2010, Texas Instruments Incorporated 200ms/div Figure 25. Submit Documentation Feedback 9 TPS727xx SBVS128B – JUNE 2009 – REVISED APRIL 2010 www.ti.com APPLICATION INFORMATION The TPS727xx family belongs to a family of new generation LDO regulators that consume extremely low quiescent current while simulatenously delivering excellent PSRR with very little headroom (VIN – VOUT differential voltage), and very good transient response. These features, combined with low noise without a noise reduction pin in an ultrasmall package, make this device ideal for portable applications. This family of regulators offers sub-bandgap output voltages, current limit and thermal protection, and is fully specified from –40°C to +125°C. INPUT AND OUTPUT CAPACITOR REQUIREMENTS Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1mF to 1.0mF low equivalent series resistance (ESR) capacitor across the IN pin and GND input of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is not sufficiently low, a 0.1mF input capacitor may be necessary to ensure stability. The TPS727xx is designed to be stable with standard ceramic capacitors with values of 1.0mF or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR should be less than 200mΩ. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device. High ESR capacitors may degrade PSRR. INTERNAL CURRENT LIMIT ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device is turned off. As the device cools down, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal Information section for more details. The PMOS pass element in the TPS727xx has a built-in body diode that conducts current when the voltage at the OUT pin exceeds the voltage at the IN pin. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of rated output current is recommended. SOFT START The startup current is given by Equation 1: ISOFT START (mA) = COUT(mF) ´ 0.07(V/ms) + ILOAD(mA) (1) This equation shows that soft-start current is directly proportional to COUT. The output voltage ramp rate is independent of COUT and load current, and has a typical value of 0.07V/ms. The TPS727xx automatically adjusts the soft-start current to supply both the load current and the COUT charge current. For example, if ILOAD = 0mA upon enabling the LDO, ISOFT START = 1mF × 0.07 V/ms + 0mA = 70mA, the current that charges the output capacitor. If ILOAD = 200mA, ISOFT START = 1mF × 0.07V/ms + 200mA = 270mA, the current required for charging output capacitor and supplying the load current. If the output capacitor and load are increased such that the soft-start current exceeds the output current limit, it is clamped at the typical current limit of 400mA. For example, if COUT = 10mF and IOUT = 200mA, 10mF × 0.07V/ms + 200mA = 900mA is not supplied. Instead, it is clamped at 400mA. SHUTDOWN The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to the IN pin. The TPS727xx internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output voltage is not regulated, and is VOUT = 10 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated TPS727xx www.ti.com DROPOUT VOLTAGE The TPS727xx uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO approximately scales with output current because the PMOS device behaves like a resistor in dropout. SBVS128B – JUNE 2009 – REVISED APRIL 2010 (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 16 in the Typical Characteristics section. The internal protection circuitry of the TPS727xx has been designed to protect against overload conditions. It is not intended to replace proper heatsinking. Continuously running the TPS727xx into thermal shutdown degrades device reliability. TRANSIENT RESPONSE Power Dissipation As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC lowand high-K boards are given in the Dissipation Ratings table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. UNDERVOLTAGE LOCK-OUT (UVLO) The TPS727xx uses an undervoltage lock-out circuit that keeps the output shut off until the input voltage reaches the UVLO threshold voltage. THERMAL INFORMATION Thermal Protection Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design Copyright © 2009–2010, Texas Instruments Incorporated Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 2: PD = (VIN - VOUT) ´ IOUT (2) Package Mounting Solder pad footprint recommendations for the TPS727xx are available from the Texas Instruments web site at www.ti.com. The recommended land pattern for the DSE package is shown in Figure 26. Figure 27 shows the dimensions of the YFF package. Submit Documentation Feedback 11 TPS727xx SBVS128B – JUNE 2009 – REVISED APRIL 2010 www.ti.com (1) Publication IPC-7351 is recommended for alternate designs. (2) For more information, refer to TI application notes SCBA017 and SLUA271 (Quad Flatpack No-Lead Logic Packages and QFN/SON PCB Attachment, respectively) for specific thermal information, via requirements, and additional recommendations for board layout. These documents are available at the Texas Instruments web site (http://www.ti.com) by searching for the literature number. (3) Laser-cutting apertures with trapedzoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for stencil design considerations. (4) Customers should contact their board fabrication site for minimum solder mask tolerances between signal pads. Figure 26. Recommended Land Pattern for DSE Package 12 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated TPS727xx www.ti.com (1) SBVS128B – JUNE 2009 – REVISED APRIL 2010 Devices in a YFF package can have a dimension that ranges within a specified tolerance. To determine the exact measurements, contact a local Texas Instruments representative. Figure 27. YFF Package Dimensions Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 13 TPS727xx SBVS128B – JUNE 2009 – REVISED APRIL 2010 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (September, 2009) to Revision B Page • Changed title of data sheet ................................................................................................................................................... 1 • Updated Features list ............................................................................................................................................................ 1 • Changed footnote 2 to Absolute Maximum Ratings table .................................................................................................... 2 • Revised numerous specifications and parameters in Electrical Characteristics table .......................................................... 3 • Revised operating parameters for Figure 5 .......................................................................................................................... 5 • Added operating parameters to Figure 7 .............................................................................................................................. 6 • Replaced Figure 6 ................................................................................................................................................................ 6 • Updated Figure 10 ................................................................................................................................................................ 7 Changes from Original (June, 2009) to Revision A Page • Changed PSRR value in Features list from 80dB to 70dB ................................................................................................... 1 • Updated YFF WCSP device graphics ( front page, pin drawing, Figure 27) to accurately reflect package layout .............. 1 • Updated format of characteristic performance graphs (Figure 18 through Figure 22) ......................................................... 8 • Changed wording of first paragraph in Internal Current Limit section ................................................................................ 10 14 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 24-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS72711YFFR PREVIEW DSBGA YFF 4 3000 TBD Call TI Call TI Samples Not Available TPS72711YFFT PREVIEW DSBGA YFF 4 250 TBD Call TI Call TI Samples Not Available TPS72715DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples TPS72715DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples TPS72715YFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Purchase Samples TPS72715YFFT ACTIVE DSBGA YFF 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Request Free Samples TPS72718DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples TPS72718DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples TPS72718YFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Purchase Samples TPS72718YFFT ACTIVE DSBGA YFF 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Request Free Samples TPS727285DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples TPS727285DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples TPS72728DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples TPS72728DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples TPS72728YFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Purchase Samples TPS72728YFFT ACTIVE DSBGA YFF 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2010 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Mar-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS72715DSER WSON DSE 6 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS72715DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS72718DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS72718DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS72728DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS72728DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Mar-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS72715DSER WSON DSE 6 3000 195.0 200.0 45.0 TPS72715DSET WSON DSE 6 250 195.0 200.0 45.0 TPS72718DSER WSON DSE 6 3000 195.0 200.0 45.0 TPS72718DSET WSON DSE 6 250 195.0 200.0 45.0 TPS72728DSER WSON DSE 6 3000 195.0 200.0 45.0 TPS72728DSET WSON DSE 6 250 195.0 200.0 45.0 Pack Materials-Page 2 X: Max = 1210 µm, Min = 1110 µm Y: Max = 842 µm, Min = 742 µm X: Max = 1210 µm, Min = 1110 µm Y: Max = 842 µm, Min = 742 µm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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