TI TPS71926

TPS718xx
TPS719xx
www.ti.com
SBVS088A – FEBRUARY 2007 – REVISED MARCH 2007
Dual, 200mA Output, Low Noise, High PSRR
Low-Dropout Linear Regulators in 2mm x 2mm SON Package
FEATURES
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DESCRIPTION
Dual, 200mA High-Performance LDOs
Low Total Quiescent Current: 90µA with Both
LDOs Enabled
Low Noise: 70µVRMS/V
Active Output Pulldown (TPS719xx)
Independent Enables for Each LDO
PSRR: 65dB at 1kHz, 45dB at 1MHz
Available in Multiple Fixed-Output Voltage
Combinations from 0.9V to 3.6V Using
Innovative Factory EEPROM Programming
Fast Start-Up Time: 160µs
Over-Current, Over-Temperature and
Under-Voltage Protection
Low Dropout: 230mV at 200mA
Stable with 1µF Ceramic Output Capacitor
Available in 2mm × 2mm SON-6 Package
The TPS718xx and TPS719xx families of
low-dropout (LDO) regulators offer a high
power-supply rejection ratio (PSRR), low noise, fast
start-up, and excellent line and load transient
responses while consuming a very low 90µA (typical)
at no load ground current with both LDOs enabled.
The TPS719xx also provides an active pulldown
circuit to quickly discharge output loads. The
TPS718xx and TPS719xx are stable with ceramic
capacitors and use an advanced BiCMOS fabrication
process to yield a typical dropout voltage of 230mV
at 200mA output loads. The TPS718xx and
TPS719xx also use a precision voltage reference
and feedback loop to achieve 3% overall accuracy
over all load, line, process, and temperature
variations. Both families of devices are fully specified
from TJ = –40°C to +125°C and are offered in a 2mm
× 2mm SON-6 package that is ideal for applications
such as mobile handsets and WLAN that require
good thermal dissipation while maintaining a very
small footprint.
APPLICATIONS
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Digital Cameras
Cellular Camera Phones
Wireless LAN, Bluetooth®
Handheld Products
2.7V - 6.5V
VIN
0.9V - 3.6V
IN
1mF
VOUT
OUT1
1mF
TPS718xx
TPS718xx, TPS719xx
DRV Package
2mm x 2mm SON
(TOP VIEW)
TPS719xx
On
OUT1 1
EN1
0.9V - 3.6V
Off
VOUT
OUT2
On
Off
IN 2
OUT2 3
6 EN1
GND
5 GND
4 EN2
1m F
EN2
GND
Typical Application Circuit
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPS718xx
TPS719xx
www.ti.com
SBVS088A – FEBRUARY 2007 – REVISED MARCH 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
VOUT (2) (3)
PRODUCT
TPS718xx-yywwwz
TPS719xx-yywwwz
XX is nominal output voltage for LDO1 (for example, 28 = 2.8V).
YY nominal output voltage for LDO2.
WWW is package designator.
Z is Tape & Reel quantity (R = 3000, T = 250).
Examples: TPS71918–285DRVR
TPS719185-33DRVR
(1)
(2)
(3)
XX = 18 = 1.8V, YYY = 285 = 2.85V
XXX = 185 = 1.85V, YY = 33 = 3.3V
DRV = 2mm x 2mm SON package
Z = R = 3000 piece reel
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Both outputs are programmable from 0.9V to 3.6V in 50mV increments.
Output voltages from 0.9V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating temperature range (unless otherwise noted). All voltages are with respect to GND.
PARAMETER
TPS718xx, TPS719xx
UNIT
Input voltage range, VIN
Enable voltage range, VEN1 and VEN2
–0.3 to +7.0
V
–0.3 to VIN + 0.3V
V
–0.3 to +7.0
V
Output voltage range, VOUT
Peak output current
Internally limited
Output short-circuit duration
Indefinite
Junction temperature range, TJ
–55 to +150
°C
Storage temperature range , TSTG
–55 to +150
°C
Total continuous power dissipation, PDISS
See Dissipation Ratings Table
ESD rating, HBM
2
kV
ESD rating, CDM
500
V
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
DISSIPATION RATINGS
BOARD
PACKAGE
RθJC
RθJA
DERATING FACTOR
ABOVE TA = +25°C
TA < +25°C
TA = +70°C
TA = +85°C
High-K (1)
DRV
20°C/W
95°C/W
10.53mW/°C
1053mW
579mW
421mW
(1)
2
The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
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TPS719xx
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SBVS088A – FEBRUARY 2007 – REVISED MARCH 2007
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater;
IOUT = 0.5mA, VEN1 = VEN2 = VIN, COUT = 1.0µF, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIN
Input voltage range (1)
2.7
6.5
VOUT1, VOUT2
Output voltage range
0.9
3.6
Nominal
Over VIN, IOUT, VOUT + 0.5V ≤ VIN ≤ 6.5V
Temp
0mA ≤ IOUT ≤ 200mA
VOUT1, VOUT2
Output accuracy
∆VOUT/ ∆VIN
Line regulation
VOUT(NOM) + 0.5V ≤ VIN ≤ 6.5V,
IOUT = 5mA
∆VOUT/ ∆IOUT
Load regulation
0mA ≤ IOUT ≤ 200mA
VDO
Dropout voltage (2)
(VIN = VOUT(NOM) – 0.1V)
IOUT = 200mA
ICL
Output current limit (per output)
VOUT = 0.9 × VOUT(NOM)
IGND
ISHDN
PSRR
VN
Shutdown current (IGND)
Power-supply rejection ratio
VIN = 3.8V, VOUT = 2.8V,
IOUT = 200mA
Startup time (3)
TSHUT
Shutdown time (4),
(TPS719xx only)
VEN(HI)
Enable high (enabled)
(EN1 and EN2)
VEN(LO)
Enable low (shutdown)
(EN1 and EN2)
UVLO
–3.0
240
(5)
130
µV/V
75
µV/mA
230
400
mV
mA
160
µA
IOUT1 = IOUT2 = 200mA
250
VEN1,2 ≤ 0.4V, 2.7V ≤ VIN < 4.5V,
TJ = –40°C to +85°C
0.3
VEN1,2 ≤ 0.4V, 4.5V ≤ VIN ≤ 6.5V,
TJ = –40°C to +85°C
1.8
µA
f = 100Hz
63
dB
f = 1kHz
63
dB
f = 10kHz
72
dB
f = 100kHz
58
dB
f = 1MHz
44
dB
µA
3.0
70 × VOUT
µA
µVRMS
RL = 14Ω, VOUT = 2.8V,
COUT = 1.0µF
160
µs
RL = ∞, COUT = 1.0µF,
VOUT = 2.8V
180
µs
VIN ≤ 5.5V
5.5V < VIN ≤ 6.5V
VIN rising
Hysteresis
VIN falling
Operating junction temperature
%
575
Under-voltage lockout
TJ
+3.0
90
EN1 = EN2 = 6.5V
Thermal shutdown temperature
V
mV
340
Enable pin current, enabled
(EN1 and EN2)
TSD
V
IOUT1 = IOUT2 = 0.1mA
Output noise voltage
BW = 100Hz to 100kHz
TSTR
IEN
(1)
(2)
(3)
(4)
(5)
Ground pin current
±2.5
TJ = +25°C
UNIT
1.2
6.5
V
1.25
6.5
V
0
0.4
V
0.04
1.0
µA
2.45
2.52
2.38
V
150
mV
Shutdown, temperature increasing
+160
°C
Reset, temperature decreasing
+140
°C
–40
+125
°C
Minimum VIN = VOUT + VDO or 2.7V, whichever is greater.
VDO is not measured for devices with VOUT(NOM) < 2.8V because minimum VIN = 2.7V.
Time from VEN = 1.25V to VOUT = 95% (VOUT(NOM)).
Time from VEN = 0.4V to VOUT = 5% (VOUT(NOM)).
See Shutdown section in the Applications Information for more details.
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TPS718xx
TPS719xx
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SBVS088A – FEBRUARY 2007 – REVISED MARCH 2007
DEVICE INFORMATION
TPS719 only
60W
Bandgap
UVLO
Current
Limit
Thermal
Shutdown
2.5mA
OUT1
EN1
Enable and
Power
Control
Logic
EN2
OUT2
Thermal
Shutdown
2.5mA
Current
Limit
IN
UVLO
Bandgap
60W
TPS719 only
GND
Figure 1. Functional Block Diagram
DRV PACKAGE
2mm × 2mm SON
(TOP VIEW)
OUT1 1
IN 2
OUT2 3
6 EN1
GND
5 GND
4 EN2
Table 1. PIN DESCRIPTIONS
TPS718xx, TPS719xx
4
NAME
NO.
OUT1
1
DESCRIPTION
Output of Regulator 1. A small ceramic capacitor (typically ≥ 1µF) is needed from this pin to ground to assure stability.
IN
2
Input supply to both regulators.
OUT2
3
Output of Regulator 2. A small ceramic capacitor (typically ≥ 1µF) is needed from this pin to ground to assure stability.
EN2
4
Enable pin for Regulator 2. Driving the Enable pin (EN2) high turns on Regulator 2. Driving this pin low puts Regulator 2
into shutdown mode, reducing operating current.
GND
5
Ground. Thermal pad should also be connected to ground.
EN1
6
Enable pin for Regulator 1. Driving the Enable pin (EN1) high turns on Regulator 1. Driving this pin low puts Regulator 1
into shutdown mode, reducing operating current.
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TPS719xx
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SBVS088A – FEBRUARY 2007 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 0.5mA,
VEN1 = VEN2 = VIN, COUT = 1.0µF, unless otherwise noted. Typical values are at TJ = +25°C.
LINE REGULATION
LINE REGULATION
4
0
TJ = +85°C
IOUT = 5mA
IOUT = 200mA
3
TJ = +25°C
DVOUT (mV)
DVOUT (mV)
-1
TJ = +125°C
2
1
TJ = +25°C
0
-1
TJ = -40°C
-2
-3
TJ = +85°C
-2
TJ = -40°C
-4
TJ = +125°C
-3
-5
-4
2.5
3.5
4.5
VIN (V)
5.5
6.5
2.5
3.5
Figure 2.
4.5
VIN (V)
5.5
6.5
150
200
Figure 3.
LOAD REGULATION UNDER LIGHT LOADS
LOAD REGULATION
5
4
TJ = +85°C
TJ = +25°C
2
0
-5
-2
DVOUT (mV)
DVOUT (mV)
0
TJ = -40°C
-4
-10
-15
-20
-25
-6
TJ = +125°C
TJ = +85°C
TJ = +25°C
TJ = -40°C
-30
TJ = +125°C
-8
-35
-40
-10
0
1
3
2
4
5
0
50
IOUT (mA)
100
IOUT (mA)
Figure 4.
Figure 5.
OUTPUT VOLTAGE vs
TEMPERATURE
DROPOUT VOLTAGE vs
OUTPUT CURRENT
350
2.805
IOUT = 5mA
TJ = +125°C
2.800
300
TJ = +85°C
2.795
2.785
IOUT = 200mA
2.780
VDO (mV)
VOUT (V)
250
IOUT = 0.1mA
2.790
200
150
TJ = +25°C
2.775
100
TJ = -40°C
2.770
50
2.765
0
2.760
-40 -25 -10
5
20
35 50
TJ (°C)
65
80
95 110 125
0
Figure 6.
50
100
IOUT (mA)
150
200
Figure 7.
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TPS718xx
TPS719xx
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SBVS088A – FEBRUARY 2007 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 0.5mA,
VEN1 = VEN2 = VIN, COUT = 1.0µF, unless otherwise noted. Typical values are at TJ = +25°C.
GROUND PIN CURRENT vs
OUTPUT CURRENT
GROUND PIN CURRENT vs
INPUT VOLTAGE
60
200
TJ = +125°C
IOUT = 1mA
TJ = +25°C
50
160
40
IGND (mA)
IGND (mA)
TJ = +85°C
120
TJ = -40°C
80
30
20
40
10
0
0
50
0
150
100
IOUT (mA)
200
2.5
4.5
VIN (V)
5.5
Figure 8.
Figure 9.
GROUND PIN CURRENT vs
TEMPERATURE (BOTH LDOs ENABLED)
SHUTDOWN CURRENT vs
INPUT VOLTAGE
140
6.5
5.0
IOUT = 0mA
4.5
Shutdown Current (mA)
120
100
IGND (mA)
3.5
80
60
40
4.0
TJ = +125°C
3.5
3.0
TJ = -40°C
2.5
TJ = +85°C
2.0
1.5
1.0
TJ = +25°C
20
0.5
0
0
-40 -25 -10
5
20
35 50
TJ (°C)
65
80
95 110 125
2.5
3.5
4.5
VIN (V)
5.5
6.5
Figure 10.
Figure 11.
CURRENT LIMIT vs
INPUT VOLTAGE
POWER-SUPPLY RIPPLE REJECTION vs
FREQUENCY (VIN– VOUT = 0.5V)
450
90
425
80
100mA
60
375
PSRR (dB)
Current Limit (mA)
5mA
70
400
350
325
275
200mA
40
30
TJ = +125°C
TJ = +85°C
TJ = +25°C
TJ = -40°C
300
50
20
10
0
250
2.5
3.5
4.5
VIN (V)
5.5
6.5
10
Figure 12.
6
100
1k
100k
10k
Frequency (Hz)
Figure 13.
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10M
TPS718xx
TPS719xx
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SBVS088A – FEBRUARY 2007 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 0.5mA,
VEN1 = VEN2 = VIN, COUT = 1.0µF, unless otherwise noted. Typical values are at TJ = +25°C.
POWER-SUPPLY RIPPLE REJECTION vs
FREQUENCY (VIN– VOUT = 1V)
POWER-SUPPLY RIPPLE REJECTION vs
INPUT VOLTAGE
90
80
100mA
80
70
1kHz
5mA
70
10kHz
60
PSRR (dB)
PSRR (dB)
60
50
40
30
50
100kHz
40
1MHz
30
20
20
200mA
0
0
10
100
1k
100k
10k
Frequency (Hz)
10M
1M
3.0
3.2
3.4
3.6
3.8
Figure 14.
Figure 15.
POWER-SUPPLY RIPPLE REJECTION vs
INPUT VOLTAGE
OUTPUT SPECTRAL NOISE DENSITY vs
FREQUENCY
Output Spectral Noise Density (mVÖHz)
10kHz
70
1kHz
60
100kHz
50
40
1MHz
30
20
VOUT = 2.80V
IOUT = 200mA
10
4.0
VIN (V)
80
PSRR (dB)
VOUT = 2.80V
IOUT = 5mA
10
10
0
10
VOUT = 2.80V
1
0.1
0.01
3.0
3.2
3.4
3.6
3.8
100
4.0
10k
1k
VIN (V)
Frequency (Hz)
Figure 16.
Figure 17.
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
6.5V
1V/div 3.3V
IOUTmin = 3mA
dVIN
= 1V/ms
dt
100k
dIOUT
= 200mA/ms
dt
250mA/div
IOUT1
10mV/div
VOUT1
10mV/div
VOUT2
VIN
10mV/div
VOUT1
10mV/div
VOUT2
10ms/div
20ms/div
Figure 18.
Figure 19.
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TPS719xx
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SBVS088A – FEBRUARY 2007 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 0.5mA,
VEN1 = VEN2 = VIN, COUT = 1.0µF, unless otherwise noted. Typical values are at TJ = +25°C.
TPS719 ENABLE RESPONSE
POWER-UP/POWER-DOWN
IOUT = 200mA
VIN
6.5V
0V
EN1, EN2
4V/div
1V/div
1V/div
VOUT1
1V/div
VOUT2
40ms/div
400ms/div
Figure 20.
8
VOUT
Figure 21.
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TPS718xx
TPS719xx
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SBVS088A – FEBRUARY 2007 – REVISED MARCH 2007
APPLICATION INFORMATION
The TPS718xx/TPS719xx belong to a family of new
generation LDO regulators that use innovative
circuitry to achieve ultra-wide bandwidth and high
loop gain, resulting in extremely high PSRR (up to
1MHz) at very low headroom (VIN – VOUT). These
features, combined with low noise, two independent
enables, low ground pin current and ultra-small
packaging, make this part ideal for portable
applications. This family of regulators offer
sub-bandgap output voltages, current limit and
thermal protection, and is fully specified from –40°C
to +125°C.
Figure 22 shows the basic circuit connections.
2.7V - 6.5V
VIN
1mF
VOUT
OUT1
TPS718xx
1mF
TPS719xx
On
EN1
0.9V - 3.6V
Off
VOUT
OUT2
On
Off
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended
that the board be designed with separate ground
planes for VIN and VOUT, with each ground plane
connected only at the GND pin of the device. In
addition, the ground connection for the output
capacitor should connect directly to the GND pin of
the device. High ESR capacitors may degrade
PSRR.
Internal Current Limit
0.9V - 3.6V
IN
Board Layout Recommendations to Improve
PSRR and Noise Performance
1m F
EN2
GND
Figure 22. Typical Application Circuit
Input and Output Capacitor Requirements
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1µF to 1.0µF low equivalent series resistance
(ESR) capacitor across the input supply near the
regulator. This capacitor counteracts reactive input
sources and improves transient response, noise
rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or if the device is
located close to the power source. If source
impedance is not sufficiently low, a 0.1µF input
capacitor may be necessary to ensure stability.
The TPS718xx/TPS719xx are designed to be stable
with standard ceramic capacitors of values 1.0µF or
larger at the output. X5R- and X7R-type capacitors
are best because they have minimal variation in
value and ESR over temperature. Maximum ESR
should be <1.0Ω.
The TPS718xx/TPS719xx internal current limits help
protect the regulator during fault conditions. During
current limit, the output sources a fixed amount of
current that is largely independent of output voltage.
For reliable operation, the device should not be
operated in a current limit state for extended periods
of time.
The
PMOS
pass
element
in
the
TPS718xx/TPS719xx has a built-in body diode that
conducts current when the voltage at OUT exceeds
the voltage at IN. This current is not limited, so if
extended reverse voltage operation is anticipated,
external limiting to 5% of rated output current may be
appropriate.
Shutdown
The enable pin (EN) is active high and is compatible
with standard and low voltage, TTL-CMOS levels.
When shutdown capability is not required, EN can be
connected to IN. The TPS719 with internal active
output pulldown circuitry discharges the output with a
time constant (t) of:
t=3
60 ´ RL
´ COUT
60 + RL
with:
•
•
RL = output load resistance
COUT = Output capacitance
Dropout Voltage
The TPS718xx/TPS719xx use a PMOS pass
transistor to achieve low dropout. When (VIN – VOUT)
is less than the dropout voltage (VDO), the PMOS
pass device is in its linear region of operation and
the input-to-output resistance is the RDS(ON) of the
PMOS pass element. VDO approximately scales with
output current because the PMOS device behaves
like a resistor in dropout.
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TPS719xx
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As with any linear regulator, PSRR and transient
response are degraded as (VIN – VOUT) approaches
dropout. This effect is shown in Figure 13 and
Figure 14 in the Typical Characteristics section.
Transient Response
As with any regulator, increasing the size of the
output capacitor will reduce over/undershoot
magnitude but increase duration of the transient
response.
Under-Voltage Lock-Out (UVLO)
The TPS718xx/TPS719xx utilize an under-voltage
lock-out circuit to keep the output shut off until
internal circuitry is operating properly. The UVLO
circuit has a de-glitch feature so that it typically
ignores undershoot transients on the input if they are
less than 50µs duration. On the TPS719xx, the
active pulldown discharges VOUT when the device is
in UVLO off condition. However, the input voltage
needs to be greater than 0.8V for active pulldown to
work.
Minimum Load
The TPS718xx/TPS719xx are stable with no output
load. Traditional PMOS LDO regulators suffer from
lower loop gain at very light output loads. The
TPS718xx/TPS719xx
employ
an
innovative,
low-current mode circuit under very light or no-load
conditions, resulting in improved output voltage
regulation performance down to zero output current.
THERMAL INFORMATION
Thermal Protection
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C the
output circuitry is again enabled. Depending on
power dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage due to
overheating.
10
Any tendency to activate the thermal protection
circuit indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete
design (including heatsink), increase the ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your particular application. This
configuration produces a worst-case junction
temperature of +125°C at the highest expected
ambient temperature and worst-case load.
The
internal
protection
circuitry
of
the
TPS718xx/TPS719xx has been designed to protect
against overload conditions. It was not intended to
replace proper heatsinking. Continuously running the
TPS718xx/TPS719xx
into
thermal
shutdown
degrades device reliability.
Power Dissipation
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the printed circuit board (PCB)
layout. The PCB area around the device that is free
of other components moves the heat from the device
to the ambient air. Performance data for JEDEC lowand high-K boards are given in the Dissipation
Ratings table. Using heavier copper increases the
effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating
layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT), as
shown in Equation 1:
PD = (VIN - VOUT) x IOUT
(1)
Package Mounting
Solder pad footprint recommendations for the
TPS718xx/TPS719xxx are available from the Texas
Instruments web site at www.ti.com.
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS71926-15DRVR
PREVIEW
SON
DRV
6
3000
TBD
Call TI
Call TI
TPS71926-15DRVT
PREVIEW
SON
DRV
6
250
TBD
Call TI
Call TI
TPS71928-28DRVR
PREVIEW
SON
DRV
6
3000
TBD
Call TI
Call TI
TPS71928-28DRVT
PREVIEW
SON
DRV
6
250
TBD
Call TI
Call TI
TPS71933-33DRVR
PREVIEW
SON
DRV
6
3000
TBD
Call TI
Call TI
TPS71933-33DRVT
PREVIEW
SON
DRV
6
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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