SN54AS194, SN74AS194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994 • • • • • • Parallel-to-Serial, Serial-to-Parallel Conversions Left or Right Shifts Parallel Synchronous Loading Direct Overriding Clear Temporary Data-Latching Capability Package Options Include Plastic Small-Outline Packages (D), Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs SN54AS194 . . . J PACKAGE SN74AS194 . . . D OR N PACKAGE (TOP VIEW) CLR SR SER A B C D SL SER GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA QB QC QD CLK S1 S0 description Inhibit clock (temporary data latch/do nothing) Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) A B NC C D Parallel (broadside) load Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QB QC NC QD CLK SL SER GND NC S0 S1 • • • • SN54AS194 . . . FK PACKAGE (TOP VIEW) SR SER CLR NC VCC QA These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operatingmode-control (S0, S1) inputs, and a direct overriding clear (CLR) line. The registers have four distinct modes of operation: NC – No internal connection Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low. The SN54AS194 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74AS194 is characterized for operation from 0°C to 70°C. Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AS194, SN74AS194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994 FUNCTION TABLE INPUTS MODE CLR S1 S0 CLK OUTPUTS SERIAL LEFT RIGHT PARALLEL A B C D QA QB QC QD L X X X X X X X X X L L L L H X X L X X X X X X QA0 QB0 QC0 QD0 H H H ↑ X X a b c d a b c d H L H ↑ X H X X X X H QAn QBn QCn H L H ↑ X L X X X X L QAn QBn QCn H H L ↑ H X X X X X QBn QCn QDn H H H L ↑ L X X X X X QBn QCn QDn L H L L X X X X X X X QA0 QB0 QC0 QD0 H = high level (steady state); L = low level (steady state); X = irrelevant (any input, including transitions); ↑ = transition from low to high level; a, b, c, d = the level of steady-state input at inputs A, B, C, or D, respectively; QA0, QB0, QC0, QD0 = the level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were established; QAn, QBn, QCn, QDn = the level of QA, QB, QC, respectively, before the most recent ↑ transition of the clock. logic symbol† CLR S0 S1 CLK 1 9 10 11 SRG4 R 0 M 1 C4 1 SR SER A B C D SL SER 2 3 4 5 6 7 0 3 /2 15 1, 4D QA 3, 4D 14 3, 4D 13 3, 4D QC 3, 4D 12 QD 2, 4D † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 POST OFFICE BOX 655303 QB • DALLAS, TEXAS 75265 SN54AS194, SN74AS194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994 logic diagram (positive logic) Parallel Inputs A S1 S0 SR SER 10 D 6 3 9 2 7 Two Identical Channels Not Shown† 1S CLK CLR SL SER 1S C1 1R C1 1R R R 11 1 15 12 QA QD Parallel Outputs † I/O ports not shown: QB (14) and QC (13) Pin numbers shown are for the D, J, and N packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AS194, SN74AS194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994 CLK ModeControl Inputs S0 S1 CLR Serial Data Inputs Parallel Data Inputs R L A H B L C H D L QA QB Outputs QC QD Shift Right Shift Left Clear Load Inhibit Clear Figure 1. Typical Clear, Load, Right-Shift, and Clear Sequences absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54AS194 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74AS194 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AS194, SN74AS194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994 recommended operating conditions SN54AS194 SN74AS194 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –2 –2 mA IOL fclock* Low-level output current 20 20 mA 80 MHz tw* tsu* High-level input voltage 2 Clock frequency 0 Pulse duration 4.5 CLK high 4 4 CLK low 6 7 Select 9 9.5 3.5 4 6 6 0.5 0.5 Hold time, data after CLK↑ Operating free-air temperature – 55 125 V 0 4 Clear inactive state th* TA 75 CLR Data Setup time before CLK↑ V 2 ns ns ns 0 °C 70 * On products compliant to MIL-STD-883, Class B, these parameters are based on characterization data, but are not production tested. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IIH IIL IO‡ ICC Data, CLK, CLR Mode, SL, SR Data, CLK, CLR Mode, SL, SR Data, CLK, CLR Mode, SL, SR SN54AS194 TYP† MAX TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 2 mA VCC = 4.5 V, IOL = 20 mA 5V VCC = 5 5.5 V, VI = 7 V VCC = 5 5.5 5V V, VI = 2 2.7 7V VCC = 5 5.5 5V V, VI = 0 0.4 4V VCC = 5.5 V, VO = 2.25 V Outputs high VCC = 5 5.5 5V SN74AS194 TYP† MAX MIN – 1.2 VCC – 2 0.35 – 30 Outputs low – 1.2 VCC – 2 0.5 V V 0.35 0.5 0.1 0.1 0.2 0.2 20 20 40 40 – 0.5 – 0.5 –1 –1 – 112 UNIT – 30 – 112 30 49 30 43 38 60 38 53 V mA µA mA mA mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54AS194, SN74AS194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994 switching characteristics (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† SN54AS194 SN74AS194 MIN fmax* tPLH tPHL tPHL MAX 75 CLK Any Q CLR Any Q MIN UNIT MAX 80 MHz 2.5 8 3 7 2.5 8 3 7 3.5 13 4 12 * On products compliant to MIL-STD-883, Class B, these parameters are based on characterization data, but are not production tested. † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns SN54AS194, SN74AS194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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