PRELIMINARY DATA SHEET 256MB DDR SDRAM SO DIMM EBD26UC6AKSA (32M words × 64 bits, 2 Banks) Description Features The EBD26UC6AKSA is 32M words × 64 bits, 2 banks Double Data Rate (DDR) SDRAM Small Outline Dual In-line Memory Module, mounted 8 pieces of 256M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board. • 200-pin socket type small outline dual in line memory module (SO DIMM) PCB height: 31.75mm Lead pitch: 0.6mm • 2.5V power supply • Data rate: 333Mbps/266Mbps (max.) • 2.5 V (SSTL_2 compatible) I/O • Double Data Rate architecture; two data transfers per clock cycle • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver • Data inputs, outputs and DM are synchronized with DQS • 4 internal banks for concurrent operation (Component) • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data referenced to both edges of DQS • Data mask (DM) for write data • Auto precharge option for each burst access • Programmable burst length: 2, 4, 8 • Programmable /CAS latency (CL): 2, 2.5 • Refresh cycles: (8192 refresh cycles /64ms) 7.8µs maximum average periodic refresh interval • 2 variations of refresh Auto refresh Self refresh Document No. E0307E20 (Ver. 2.0) Date Published November 2002 (K) Japan URL: http://www.elpida.com Elpida Memory , Inc. 2002 EBD26UC6AKSA Ordering Information Part number Data rate Mbps (max.) Component JEDEC speed bin (CL-tRCD-tRP) Package EBD26UC6AKSA-6B 333 DDR333B (2.5-3-3) 200-pin SO DIMM Gold EBD26UC6AKSA-7A 266 DDR266A (2-3-3) EDD2516AKTA-6B, -7A EBD26UC6AKSA-7B 266 DDR266B (2.5-3-3) EDD2516AKTA-6B, -7A, -7B Contact pad Mounted devices EDD2516AKTA-6B Pin Configurations Front side 1 pin 39 pin 41 pin 199 pin 2 pin 40 pin 42 pin 200 pin Back side Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VREF 51 VSS 2 VREF 52 VSS 3 VSS 53 DQ19 4 VSS 54 DQ23 5 DQ0 55 DQ24 6 DQ4 56 DQ28 7 DQ1 57 VDD 8 DQ5 58 VDD 9 VDD 59 DQ25 10 VDD 60 DQ29 11 DQS0 61 DQS3 12 DM0 62 DM3 13 DQ2 63 VSS 14 DQ6 64 VSS 15 VSS 65 DQ26 16 VSS 66 DQ30 17 DQ3 67 DQ27 18 DQ7 68 DQ31 19 DQ8 69 VDD 20 DQ12 70 VDD 21 VDD 71 NC 22 VDD 72 NC 23 DQ9 73 NC 24 DQ13 74 NC 25 DQS1 75 VSS 26 DM1 76 VSS 27 VSS 77 NC 28 VSS 78 NC 29 DQ10 79 NC 30 DQ14 80 NC 31 DQ11 81 VDD 32 DQ15 82 VDD 33 VDD 83 NC 34 VDD 84 NC 35 CK0 85 NC 36 VDD 86 NC 37 /CK0 87 VSS 38 VSS 88 VSS 39 VSS 89 CK2 40 VSS 90 VSS 41 DQ16 91 /CK2 42 DQ20 92 VDD 43 DQ17 93 VDD 44 DQ21 94 VDD 45 VDD 95 CKE1 46 VDD 96 CKE0 47 DQS2 97 NC 48 DM2 98 NC 49 DQ18 99 A12 50 DQ22 100 A11 101 A9 151 DQ42 102 A8 152 DQ46 103 VSS 153 DQ43 104 VSS 154 DQ47 105 A7 155 VDD 106 A6 156 VDD Preliminary Data Sheet E0307E20 (Ver. 2.0) 2 EBD26UC6AKSA Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 107 A5 157 VDD 108 A4 158 /CK1 109 A3 159 VSS 110 A2 160 CK1 111 A1 161 VSS 112 A0 162 VSS 113 VDD 163 DQ48 114 VDD 164 DQ52 115 A10/AP 165 DQ49 116 BA1 166 DQ53 117 BA0 167 VDD 118 /RAS 168 VDD 119 /WE 169 DQS6 120 /CAS 170 DM6 121 /CS0 171 DQ50 122 /CS1 172 DQ54 123 NC 173 VSS 124 NC 174 VSS 125 VSS 175 DQ51 126 VSS 176 DQ55 127 DQ32 177 DQ56 128 DQ36 178 DQ60 129 DQ33 179 VDD 130 DQ37 180 VDD 131 VDD 181 DQ57 132 VDD 182 DQ61 133 DQS4 183 DQS7 134 DM4 184 DM7 135 DQ34 185 VSS 136 DQ38 186 VSS 137 VSS 187 DQ58 138 VSS 188 DQ62 139 DQ35 189 DQ59 140 DQ39 190 DQ63 141 DQ40 191 VDD 142 DQ44 192 VDD 143 VDD 193 SDA 144 VDD 194 SA0 145 DQ41 195 SCL 146 DQ45 196 SA1 147 DQS5 197 VDDSPD 148 DM5 198 SA2 149 VSS 199 VDDID 150 VSS 200 NC Preliminary Data Sheet E0307E20 (Ver. 2.0) 3 EBD26UC6AKSA Pin Description Pin name Function A0 to A12 Address input Row address Column address BA0, BA1 Bank select address DQ0 to DQ63 Data input/output /RAS Row address strobe command /CAS Column address strobe command A0 to A12 A0 to A8 /WE Write enable /CS0, /CS1 Chip select CKE0, CKE1 Clock enable CK0 to CK2 Clock input /CK0 to /CK2 Differential clock input DQS0 to DQS7 Input and output data strobe DM0 to DM7 Input mask SCL Clock input for serial PD SDA Data input/output for serial PD SA0 to SA2 Serial address input VDD Power for internal circuit VDDQ Power for DQ circuit VDDSPD Power for serial EEPROM VREF Input reference voltage VSS Ground VDDID VDD identification flag NC No connection Preliminary Data Sheet E0307E20 (Ver. 2.0) 4 EBD26UC6AKSA Serial PD Matrix Byte No. Function described 0 1 Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 80H 128 bytes 0 0 0 0 1 0 0 0 08H 256 bytes 2 Memory type 0 0 0 0 0 1 1 1 07H DDR SDRAM 3 Number of row address 0 0 0 0 1 1 0 1 0DH 13 4 Number of column address 0 0 0 0 1 0 0 1 09H 9 5 Number of DIMM banks 0 0 0 0 0 0 1 0 02H 2 6 Module data width 0 1 0 0 0 0 0 0 40H 64 bits 7 Module data width continuation 0 0 0 0 0 0 0 0 00H 0 8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H SSTL2 9 DDR SDRAM cycle time, CL = X -6B 0 1 1 0 0 0 0 0 60H CL = 2.5*1 0 1 1 1 0 1 0 1 75H 0 1 1 1 0 0 0 0 70H 0.7ns*1 0 1 1 1 0 1 0 1 75H 0.75ns*1 -7A, -7B 10 SDRAM access from clock (tAC) -6B -7A, -7B 11 DIMM configuration type 0 0 0 0 0 0 0 0 00H None 12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.8µs Self refresh 13 Primary SDRAM width 0 0 0 1 0 0 0 0 10H × 16 14 Error checking SDRAM width 0 0 0 0 0 0 0 0 00H Not used 0 0 0 0 0 0 0 1 01H 1 CLK 0 0 0 0 1 1 1 0 0EH 2,4,8 0 0 0 0 0 1 0 0 04H 4 18 SDRAM device attributes: /CAS latency 0 0 0 0 1 1 0 0 0CH 2, 2.5 19 SDRAM device attributes: /CS latency 0 0 0 0 0 0 0 1 01H 0 20 SDRAM device attributes: /WE latency 0 0 0 0 0 0 1 0 02H 1 21 SDRAM module attributes 0 0 1 0 0 0 0 0 20H Unbuffered 22 SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0H VDD ± 0.2V 23 Minimum clock cycle time at CL = X –0.5 -6B, -7A 0 1 1 1 0 1 0 1 75H CL = 2*1 1 0 1 0 0 0 0 0 A0H 24 Maximum data access time (tAC) from clock at CL = X –0.5 -6B 0 1 1 1 0 0 0 0 70H 0.7ns*1 0 1 1 1 0 1 0 1 75H 0.75ns*1 0 0 0 0 0 0 0 0 00H 0 1 0 0 1 0 0 0 48H 18ns 15 16 17 SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device -7B -7A, -7B 25 to 26 27 Minimum row precharge time (tRP) -6B 0 1 0 1 0 0 0 0 50H 20ns 28 Minimum row active to row active delay 0 (tRRD) -6B 0 1 1 0 0 0 0 30H 12ns 0 1 1 1 1 0 0 3CH 15ns -7A, -7B -7A, -7B 0 Preliminary Data Sheet E0307E20 (Ver. 2.0) 5 EBD26UC6AKSA Byte No. Function described 29 Minimum /RAS to /CAS delay (tRCD) -6B -7A, -7B 30 Minimum active to precharge time (tRAS) -6B -7A, -7B Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 1 0 0 1 0 0 0 48H 18ns 0 1 0 1 0 0 0 0 50H 20ns 0 0 1 0 1 0 1 0 2AH 42ns 0 0 1 0 1 1 0 1 2DH 45ns 31 Module bank density 0 0 0 0 0 0 1 0 20H 128M bytes 32 Address and command setup time before clock (tIS) -6B 0 1 1 1 0 1 0 1 75H 0.75ns*1 1 0 0 1 0 0 0 0 90H 0.9ns*1 0 1 1 1 0 1 0 1 75H 0.75ns*1 1 0 0 1 0 0 0 0 90H 0.9ns*1 Data input setup time before clock (tDS) 0 -6B 1 0 0 0 1 0 1 45H 0.45ns*1 0 1 0 1 0 0 0 0 50H 0.5ns*1 0 1 0 0 0 1 0 1 45H 0.45ns*1 0 1 0 1 0 0 0 0 50H 0.5ns*1 -7A, -7B 33 Address and command hold time after clock (tIH) -6B -7A, -7B 34 -7A, -7B 35 Data input hold time after clock (tDH) -6B -7A, -7B 36 to 40 Superset information 0 0 0 0 0 0 0 0 00H Future use 41 Active command period (tRC) -6B 0 0 1 1 1 1 0 0 3CH 60ns*1 0 1 0 0 0 1 0 0 44H 68ns*1 0 1 0 0 1 0 0 0 48H 72ns*1 0 1 0 0 1 0 1 1 4BH 75ns*1 -7A, -7B 42 Auto refresh to active/ Auto refresh command cycle (tRFC) -6B -7A, -7B 43 SDRAM tCK cycle max. (tCK max.) 0 0 1 1 0 0 0 0 30H 12ns*1 44 Dout to DQS skew -6B 0 0 1 0 1 1 0 1 2DH 0.45ns*1 0 0 1 1 0 0 1 0 32H 0.5ns*1 0 1 0 1 0 1 0 1 55H 0.55ns*1 0 1 1 1 0 1 0 1 75H 0.75ns*1 Future use -7A, -7B 45 Data hold skew (tQHS) -6B -7A, -7B 46 to 61 Superset information 0 0 0 0 0 0 0 0 00H 62 SPD Revision 0 0 0 0 0 0 0 0 00H 63 Checksum for bytes 0 to 62 -6B 1 1 1 0 1 0 0 0 E8H -7A 1 0 1 0 0 0 1 0 A2H -7B 1 1 0 0 1 1 0 1 CDH 64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH Continuation code 66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory 67 to 71 Manufacturing location 0 0 0 0 0 0 0 0 00H 72 Module part number × × × × × × × × ×× (ASCII-8bit code) 73 Module part number 0 1 0 0 0 1 0 1 45H E 74 Module part number 0 1 0 0 0 0 1 0 42H B 75 Module part number 0 1 0 0 0 1 0 0 44H D Preliminary Data Sheet E0307E20 (Ver. 2.0) 6 EBD26UC6AKSA Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 76 0 0 1 0 0 1 32H 2 Module part number 1 0 77 Module part number 0 0 1 1 0 1 1 0 36H 6 78 Module part number 0 1 0 1 0 1 0 1 55H U 79 Module part number 0 1 0 0 0 0 1 1 43H C 80 Module part number 0 0 1 1 0 1 1 0 36H 6 81 Module part number 0 1 0 0 0 0 0 1 41H A 82 Module part number 0 1 0 0 1 0 1 1 4BH K 83 Module part number 0 1 0 1 0 0 1 1 53H S 84 Module part number 0 1 0 0 0 0 0 1 41H A 85 Module part number 0 0 1 0 1 1 0 1 2DH — 86 Module part number -6B 0 0 1 1 0 1 1 0 36H 6 0 0 1 1 0 1 1 1 37H 7 87 Module part number -6B, -7B 0 1 0 0 0 0 1 0 42H B 0 1 0 0 0 0 0 1 41H A -7A, -7B -7A 88 to 90 Module part number 0 0 1 0 0 0 0 0 20H (Space) 91 Revision code 0 0 1 1 0 0 0 0 30H Initial 92 Revision code 0 0 1 0 0 0 0 0 20H (Space) 93 Manufacturing date × × × × × × × × ×× 94 Manufacturing date × × × × × × × × ×× 95 to 98 Module serial number 99 to 127 Manufacture specific data Note: These specifications are defined based on component specification, not module. Preliminary Data Sheet E0307E20 (Ver. 2.0) 7 Year code (HEX) Week code (HEX) EBD26UC6AKSA Block Diagram /CS1 /CS0 RS DQS0 LDQS /CS LDQS RS /CS DQS4 8 RS DQS1 RS DM1 8 LDM LDM I/O0 to I/O7 I/O0 to I/O7 UDQS UDQS DM4 D0 I/O0 to I/O7 RS D4 DQS5 UDM UDQS UDM DM5 8 RS LDQS /CS LDQS DQS6 LDM DQS3 RS DM3 8 DM6 UDQS I/O0 to I/O7 I/O8 to I/O15 I/O8 to I/O15 /CS LDQS /CS D1 UDQS LDM LDM I/O0 to I/O7 I/O0 to I/O7 RS DQ48 to DQ55 RS D5 DQS7 D3 UDQS UDQS D7 RS UDM UDM DM7 RS DQ24 to DQ31 UDM LDQS 8 I/O0 to I/O7 RS UDM RS /CS RS DQ16 to DQ23 D6 UDQS RS LDM 8 I/O0 to I/O7 RS DQ40 to DQ47 I/O8 to I/O15 RS DM2 D2 RS I/O8 to I/O15 DQS2 RS DQ32 to DQ39 RS DQ8 to DQ15 /CS LDM LDM 8 RS DQ0 to DQ7 LDQS RS RS DM0 /CS LDQS 8 I/O8 to I/O15 I/O8 to I/O15 UDM UDM I/O8 to I/O15 I/O8 to I/O15 RS DQ56 to DQ63 * D0 to D7 : 256M bits DDR SDRAM U0 : 2k bits EEPROM Rs : 22Ω Serial PD BA0 to BA1 SDRAMs (D0 to D7) A0 to AN SDRAMs (D0 to D7) SCL /RAS SDRAMs (D0 to D7) SA0 A0 /CAS SDRAMs (D0 to D7) SA1 A1 SA2 A2 /WE SDRAMs (D0 to D7) CKE0 SDRAMs (D0 to D3) CKE1 SDRAMs (D4 to D7) VDDSPD SPD VREF SDRAMs (D0 to D7) VDD SDRAMs (D0 to D7), VDD and VDDQ SDA SCL SDA U0 WP CK0 /CK0 4 loads CK1 /CK1 4 loads CK2 10 pF VSS /CK2 SDRAMs (D0 to D7), SPD Notes : VDDID Open 1. DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. VDDID strap connections: (for memory device VDD, VDDQ) Strap out (open): VDD = VDDQ Strap in (closed): VDD ≠ VDDQ 2. The SDA pull-up registor is reguired due to the open-drain/open-collector output. 3. The SCL pull-up registor is recommended, because of the normal SCL lime inactive "high" state. Preliminary Data Sheet E0307E20 (Ver. 2.0) 8 EBD26UC6AKSA Logical Clock Net Structure 4DRAM loads DRAM1 DRAM2 120Ω DIMM connector DRAM3 DRAM4 Preliminary Data Sheet E0307E20 (Ver. 2.0) 9 EBD26UC6AKSA Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 200 µs and then, execute power on sequence and auto refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to VSS VT –1.0 to +3.6 V Supply voltage relative to VSS VDD, VDDQ –1.0 to +3.6 V Short circuit output current IO 50 mA Power dissipation PD 8 W Operating temperature TA 0 to +70 °C Storage temperature Tstg –55 to +125 °C Note 1 Note: DDR SDRAM device specification. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC Operating Conditions (TA = 0 to +70°C) (DDR SDRAM Device Specification) Parameter Symbol Supply voltage Min Typ Max Unit Notes 1 VDD, VDDQ 2.3 2.5 2.7 V VSS 0 0 0 V Input reference voltage VREF 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V Termination voltage VTT VREF – 0.04 VREF VREF + 0.04 V Input high voltage VIH (DC) VREF + 0.15 — VDDQ + 0.3 V 2 Input low voltage VIL (DC) –0.3 — VREF – 0.15 V 3 VIN (DC) –0.3 — VDDQ + 0.3 V 4 VIX (DC) 0.5 × VDDQ − 0.2V 0.5 × VDDQ 0.5 × VDDQ + 0.2V V VID (DC) 0.36 — VDDQ + 0.6 Input voltage level, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input differential voltage, CK and /CK inputs Notes: 1. 2. 3. 4. 5. 6. V 5, 6 VDDQ must be lower than or equal to VDD. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns. VIN (DC) specifies the allowable dc execution of each differential input. VID (dc) specifies the input differential voltage required for switching. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement. Preliminary Data Sheet E0307E20 (Ver. 2.0) 10 EBD26UC6AKSA DC Characteristics 1 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol Grade max. Operating current (ACTV-PRE) IDD0 -6B -7A, -7B 1320 1200 mA Operating current (ACTV-READ-PRE) IDD1 -6B -7A, -7B 1560 1440 mA Idle power down standby current IDD2P 48 mA -6B -7A, -7B -6B -7A, -7B 560 480 480 400 Floating idle standby current IDD2F Quiet idle standby current IDD2Q Active power down standby current IDD3P Active standby current IDD3N Operating current (Burst read operation) Operating current (Burst write operation) IDD4R IDD4W Auto refresh current IDD5 Self refresh current IDD6 Operating current (4 banks interleaving) IDD7A Unit mA mA 320 -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B mA 880 800 2080 1840 2080 1840 3200 2800 mA mA mA mA 48 mA 3240 2800 mA Test condition CKE ≥ VIH, tRC = tRC (min.) CKE ≥ VIH, BL = 4, CL = 2.5, tRC = tRC (min.) CKE ≤ VIL Notes 1, 2, 9 1, 2, 5 4 CKE ≥ VIH, /CS ≥ VIH, 4, 5 DQ, DQS, DM = VREF CKE ≥ VIH, /CS ≥ VIH, 4, 10 DQ, DQS, DM = VREF CKE ≤ VIL CKE ≥ VIH, /CS ≥ VIH tRAS = tRAS (max.) CKE ≥ VIH, BL = 2, CL = 2.5 CKE ≥ VIH, BL = 2, CL = 2.5 tRFC = tRFC (min.), Input ≤ VIL or ≥ VIH Input ≥ VDD – 0.2 V Input ≤ 0.2 V BL = 4 3 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6 5, 6, 7 Notes. 1. These IDD data are measured under condition that DQ pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one cycle. 6. Data/Data mask transition twice per one cycle. 7. 4 banks active. Only one bank is running at tRC = tRC (min.) 8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general. 9. Command/Address transition once every two clock cycles. 10. Command/Address stable at ≥ VIH or ≤ VIL. DC Characteristics 2 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol Input leakage current ILI Output leakage current ILO Output high current IOH Output low current IOL min. max. Unit Test condition –16 16 µA VDD ≥ VIN ≥ VSS –10 10 µA VDD ≥ VOUT ≥ VSS –15.2 — mA VOUT = 1.95V 1 15.2 — mA VOUT = 0.35V 1 Note: 1. DDR SDRAM device specification. Preliminary Data Sheet E0307E20 (Ver. 2.0) 11 Notes EBD26UC6AKSA Pin Capacitance (TA = 25°C, VDD, VDDQ = 2.5V ± 0.2V) Parameter Symbol Pins max. Unit Input capacitance CI1 Address, /RAS, /CAS, /WE TBD pF Input capacitance CI2 CK, /CK, CKE, /CS TBD pF Data and DQS input/output capacitance CO DQ, DQS, DM TBD pF Notes AC Characteristics (TA = 0 to +70°°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) (DDR SDRAM Device Specification) -6B -7A -7B Parameter Symbol min. max. min. max. min. max Unit Notes Clock cycle time (CL = 2) tCK 7.5 12 7.5 12 10 12 ns 10 (CL = 2.5) tCK 6 12 7.5 12 7.5 12 ns CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK half period tHP min (tCH, tCL) — min (tCH, tCL) — min (tCH, tCL) — tCK tAC –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 2, 11 tDQSCK –0.6 0.6 –0.75 0.75 –0.75 0.75 ns 2, 11 DQS to DQ skew tDQSQ — 0.45 — 0.5 — 0.5 ns 3 DQ/DQS output hold time from DQS tQH tHP – tQHS — tHP – tQHS — tHP – tQHS — ns Data hold skew factor tQHS — 0.55 — 0.75 — 0.75 ns –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 5, 11 –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 6, 11 DQ output access time from CK, /CK DQS output access time from CK, /CK Data-out high-impedance time from tHZ CK, /CK Data-out low-impedance time from tLZ CK, /CK Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQ and DM input setup time tDS 0.45 — 0.5 — 0.5 — ns 8 DQ and DM input hold time tDH 0.45 — 0.5 — 0.5 — ns 8 DQ and DM input pulse width tDIPW 1.75 — 1.75 — 1.75 — ns 7 Write preamble setup time tWPRES 0 — 0 — 0 — ns Write preamble tWPRE 0.25 — 0.25 — 0.25 — tCK Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS falling edge to CK setup time tDSS 0.2 — 0.2 — 0.2 — tCK DQS falling edge hold time from CK tDSH 0.2 — 0.2 — 0.2 — tCK DQS input high pulse width tDQSH 0.35 — 0.35 — 0.35 — tCK DQS input low pulse width tDQSL 0.35 — 0.35 — 0.35 — tCK Address and control input setup time tIS 0.75 — 0.9 — 0.9 — ns 8 Address and control input hold time tIH 0.75 — 0.9 — 0.9 — ns 8 Address and control input pulse width 2.2 — 2.2 — 2.2 — ns 7 tIPW Preliminary Data Sheet E0307E20 (Ver. 2.0) 12 9 EBD26UC6AKSA -6B Parameter -7A -7B Symbol min. max. min. max. min. max Unit tMRD 2 — 2 — 2 — tCK tRAS 42 120000 45 120000 45 120000 ns tRC 60 — 67.5 — 67.5 — ns tRFC 72 — 75 — 75 — ns Active to Read/Write delay tRCD 18 — 20 — 20 — ns Precharge to active command period tRP 18 — 20 — 20 — ns Active to Autoprecharge delay tRAP tRCD min. — tRCD min. — tRCD min. — ns Active to active command period tRRD 12 — 15 — 15 — ns Write recovery time tWR 15 — 15 — 15 — ns Mode register set command cycle time Active to Precharge command period Active to Active/Auto refresh command period Auto refresh to Active/Auto refresh command period Auto precharge write recovery and tDAL precharge time Internal write to Read command tWTR delay (tWR/tCK)+ — (tRP/tCK) (tWR/tCK)+ — (tRP/tCK) (tWR/tCK)+ — (tRP/tCK) tCK 1 — 1 — 1 — tCK Average periodic refresh interval — 7.8 — 7.8 — 7.8 µs tREF Notes 13 Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter definitions, see ‘Timing Waveforms’ section. 2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing VTT. 5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving. 6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK. 12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than 0.4V/400 cycle. 13. tDAL = (tWR/tCK)+(tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns, tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3) tDAL = 5 clocks Preliminary Data Sheet E0307E20 (Ver. 2.0) 13 EBD26UC6AKSA Timing Parameter Measured in Clock Cycle for unbuffered DIMM Number of clock cycle tCK Parameter 6ns Symbol min. 7.5ns max. min. max. Write to pre-charge command delay (same bank) tWPD 4 + BL/2 3 + BL/2 Read to pre-charge command delay (same bank) tRPD BL/2 BL/2 Write to read command delay (to input all data) tWRD 2 + BL/2 2 + BL/2 Burst stop command to write command delay (CL = 2) tBSTW 2 2 (CL = 2.5) tBSTW 3 3 Burst stop command to DQ High-Z (CL = 2) tBSTZ 2 2 2 2 (CL = 2.5) tBSTZ 2.5 2.5 2.5 2.5 Read command to write command delay (to output all data) (CL = 2) tRWD 2 + BL/2 2 + BL/2 (CL = 2.5) tRWD 3 + BL/2 3 + BL/2 Pre-charge command to High-Z (CL = 2) tHZP 2 2 2 2 (CL = 2.5) tHZP 2.5 2.5 2.5 2.5 Write command to data in latency tWCD 1 1 1 1 Write recovery tWR 3 2 DM to data in latency tDMD 0 Mode register set command cycle time tMRD 2 2 Self refresh exit to non-read command tSNR 12 10 Self refresh exit to read command tSRD 200 200 Power down entry tPDEN 1 Power down exit to command input tPDEX 1 Preliminary Data Sheet E0307E20 (Ver. 2.0) 14 0 1 0 1 1 0 1 EBD26UC6AKSA Pin Functions CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins) Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY8) is loaded via the A0 to the A8 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. BA0, BA1 (input pin) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table] BA0 BA1 Bank 0 L L Bank 1 H L Bank 2 L H Bank 3 H H Remark: H: VIH. L: VIL. CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH. DQ (input and output pins) Data are input to and output from these pins. DQS (input and output pin) DQS provide the read data strobes (as output) and the write data strobes (as input). Preliminary Data Sheet E0307E20 (Ver. 2.0) 15 EBD26UC6AKSA DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and VREF VDD and VDDQ (power supply pins) 2.5V is applied. (VDD is for the internal circuit and VDDQ is for the output buffer.) VDDSPD (power supply pin) 2.5V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. Detailed Operation Part, AC Characteristics and Timing Waveforms Refer to the EDD2516AKTA datasheet (E0303E). Preliminary Data Sheet E0307E20 (Ver. 2.0) 16 EBD26UC6AKSA Physical Outline Unit: mm 67.60 63.60 11.55 18.45 3.80 (DATUM -A-) 4x Full R 4.00 199 1 6.00 20.0 31.75 Component area (Front) A 11.40 2.15 47.40 B 2.45 4.20 1.00 ± 0.10 4.20 1.50 2.15 47.40 11.40 2.45 2 200 R0.50 ± 0.20 R0.50 ± 0.20 2x φ 1.80 4.00 ± 0.10 Component area (Back) (DATUM -A-) 2.00 Min. Detail A Detail B (DATUM -A-) 0.25 Max 2.55 4.00 ± 0.10 FULL R 0.60 0.45 ± 0.03 1.80 1.00 ± 0.10 ECA-TS2-0019-01 Preliminary Data Sheet E0307E20 (Ver. 2.0) 17 EBD26UC6AKSA CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0202 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Preliminary Data Sheet E0307E20 (Ver. 2.0) 18 EBD26UC6AKSA The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107 Preliminary Data Sheet E0307E20 (Ver. 2.0) 19