PRELIMINARY DATA SHEET 128MB Registered DDR SDRAM DIMM EBD12RB8ALFA (16M words × 72 bits, 1 Bank) Description Features The EBD12RB8ALFA is a 16M × 72 × 1 bank Double Data Rate (DDR) SDRAM Module, mounted 9 pieces of 128M bits DDR SDRAM (EDD1208ALTA) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). Read and write operations are performed at the cross points of the CLK and the /CLK. This high-speed data transfer is realized by the 2bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 184-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board. • 184-pin socket type dual in line memory module (DIMM) Outline: 133.35mm (Length) × 43.18mm (Height) × 4.00mm (Thickness) Lead pitch: 1.27mm • 2.5V power supply (VDD/VDDQ) • SSTL-2 interface for all inputs and outputs • Clock frequency: 133MHz/100MHz (max.) • Data inputs and outputs are synchronized with DQS • 4 banks can operate simultaneously and independently (Component) • Burst read/write operation • Programmable burst length: 2, 4, 8 Burst read stop capability • Programmable burst sequence Sequential Interleave • Start addressing capability Even and Odd • Programmable /CAS latency (CL): 2, 2.5 • 8192 refresh cycles: 15.6µs (4096/64ms) • 2 variations of refresh Auto refresh Self refresh Document No. E0212E10 (Ver. 1.0) Date Published August 2001 Printed in Japan URL: http://www.elpida.com C Elpida Memory, Inc. 2001 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. EBD12RB8ALFA Ordering Information Part number Clock frequency MHz (max.) /CAS latency Package EBD12RB8ALFA-7A EBD12RB8ALFA-75 EBD12RB8ALFA-1A 133 133 100 2.0 2.5 2.0 184-pin dual lead Gold out socket type Contact pad Mounted devices EDD1208ALTA Pin Configurations Front side 1 pin 52 pin 53 pin 93 pin 92 pin 144 pin 145 pin 184 pin Back side Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VREF 47 DQS8 93 VSS 139 VSS 2 DQ0 48 A0 94 DQ4 140 DM8/DQS17 3 VSS 49 CB2 95 DQ5 141 A10 4 DQ1 50 VSS 96 VDDQ 142 CB6 5 DQS0 51 CB3 97 DM0/DQS9 143 VDDQ 6 DQ2 52 BA1 98 DQ6 144 CB7 7 VDD 53 DQ32 99 DQ7 145 VSS 8 DQ3 54 VDDQ 100 VSS 146 DQ36 9 NC 55 DQ33 101 NC 147 DQ37 10 /RESET 56 DQS4 102 NC 148 VDD 11 VSS 57 DQ34 103 NC 149 DM4/DQS13 12 DQ8 58 VSS 104 VDDQ 150 DQ38 13 DQ9 59 BA0 105 DQ12 151 DQ39 14 DQS1 60 DQ35 106 DQ13 152 VSS 15 VDDQ 61 DQ40 107 DM1/DQS10 153 DQ44 16 NC 62 VDDQ 108 VDD 154 /RAS 17 NC 63 /WE 109 DQ14 155 DQ45 18 VSS 64 DQ41 110 DQ15 156 VDDQ 19 DQ10 65 /CAS 111 NC 157 /CS0 20 DQ11 66 VSS 112 VDDQ 158 NC 21 CKE0 67 DQS5 113 NC 159 DM5/DQS14 22 VDDQ 68 DQ42 114 DQ20 160 VSS 23 DQ16 69 DQ43 115 NC 161 DQ46 24 DQ17 70 VDD 116 VSS 162 DQ47 25 DQS2 71 NC 117 DQ21 163 NC 26 VSS 72 DQ48 118 A11 164 VDDQ 27 A9 73 DQ49 119 DM2/DQS11 165 DQ52 28 DQ18 74 VSS 120 VDD 166 DQ53 29 A7 75 NC 121 DQ22 167 NC Preliminary Data Sheet E0212E10 (Ver. 1.0) 2 EBD12RB8ALFA Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 30 VDDQ 76 NC 122 A8 168 VDD 31 DQ19 77 VDDQ 123 DQ23 169 DM6/DQS15 32 A5 78 DQS6 124 VSS 170 DQ54 33 DQ24 79 DQ50 125 A6 171 DQ55 34 VSS 80 DQ51 126 DQ28 172 VDDQ 35 DQ25 81 VSS 127 DQ29 173 NC 36 DQS3 82 VDDID 128 VDDQ 174 DQ60 37 A4 83 DQ56 129 DM3/DQS12 175 DQ61 38 VDD 84 DQ57 130 A3 176 VSS 39 DQ26 85 VDD 131 DQ30 177 DM7/DQS16 40 DQ27 86 DQS7 132 VSS 178 DQ62 41 A2 87 DQ58 133 DQ31 179 DQ63 42 VSS 88 DQ59 134 CB4 180 VDDQ 43 A1 89 VSS 135 CB5 181 SA0 44 CB0 90 NC 136 VDDQ 182 SA1 45 CB1 91 SDA 137 CLK0 183 SA2 46 VDD 92 SCL 138 /CLK0 184 VDDSPD Preliminary Data Sheet E0212E10 (Ver. 1.0) 3 EBD12RB8ALFA Pin Description Pin name Function A0 to A11 Address input Row address Column address BA0, BA1 Bank select address DQ0 to DQ63 Data input/output CB0 to CB7 Check bit (Data input/output) /RAS Row address strobe command /CAS Column address strobe command /WE Write enable /CS0 Chip select CKE0 Clock enable CLK0 Clock input /CLK0 Differential clock input DQS0 to DQS8 Input and output data strobe DM0 to DM8/DQS9 to DQS17 Input and output data strobe SCL Clock input for serial PD A0 to A11 A0 to A9, A11 SDA Data input/output for serial PD SA0 to SA2 Serial address input VDD Power for internal circuit VDDQ Power for DQ circuit VDDSPD Power for serial EEPROM VREF Input reference voltage VSS Ground VDDID VDD indentication flag /RESET Reset pin (forces register inputs low) NC No connection Preliminary Data Sheet E0212E10 (Ver. 1.0) 4 EBD12RB8ALFA Serial PD Matrix Byte No. 0 1 Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 80H 128 bytes 0 0 0 0 1 0 0 0 08H 256 bytes 2 Memory type 0 0 0 0 0 1 1 1 07H DDR SDRAM 3 Number of row address 0 0 0 0 1 1 0 0 0CH 12 4 Number of column address 0 0 0 0 1 0 1 0 0AH 10 5 Number of DIMM banks 0 0 0 0 0 0 0 1 01H 1 6 Module data width 0 1 0 0 1 0 0 0 48H 72 bits 7 Module data width continuation 0 0 0 0 0 0 0 0 00H 0 8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H SSTL 2 9 DDR SDRAM cycle time, CL = 2.5 (-7A) 0 1 1 1 0 1 0 1 75H 7.5ns (-75) 0 1 1 1 0 1 0 1 75H 7.5ns (-1A) 1 0 1 0 0 0 0 0 A0H 10ns 0 1 1 1 0 1 0 1 75H 0.75ns (-75) 0 1 1 1 0 1 0 1 75H 0.75ns (-1A) 1 0 0 0 0 0 0 0 80H 0.8ns 10 SDRAM access from clock (tAC) (-7A) 11 DIMM configuration type 0 0 0 0 0 0 1 0 02H ECC 12 Refresh rate/type 1 0 0 0 0 0 0 0 80H Norm 13 Primary SDRAM width 0 0 0 0 1 0 0 0 08H ×8 14 Error checking SDRAM width 0 0 0 0 1 0 0 0 08H ×8 0 0 0 0 0 0 0 1 01H 1 CLK 0 0 0 0 1 1 1 0 0EH 2, 4, 8 0 0 0 0 0 1 0 0 04H 4 0 0 0 0 1 1 0 0 0CH 2, 2.5 0 0 0 0 0 0 0 1 01H 0 0 0 0 0 0 0 1 0 02H 1 SDRAM module attributes 0 0 1 0 0 1 1 0 26H Reg+PLLdifclk 22 SDRAM Device Attributes: General 0 0 0 0 0 0 0 0 00H VDD± 0.2V 23 Minimum clock cycle time at CL = 2 (-7A) 0 1 1 1 0 1 0 1 75H 7.5ns 15 16 17 18 19 20 21 24 SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency (-75) 1 0 1 0 0 0 0 0 A0H 10ns (-1A) 1 0 1 0 0 0 0 0 A0H 10ns Maximum data access time (tAC) from clock at CL = 2 0 (-7A) 1 1 1 0 1 0 1 75H 0.75ns (-75) 0 1 1 1 0 1 0 1 75H 0.75ns (-1A) 1 0 0 0 0 0 0 0 80H 0.8ns 0 0 0 0 0 0 0 0 00H 25 to 26 Preliminary Data Sheet E0212E10 (Ver. 1.0) 5 EBD12RB8ALFA Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 27 Minimum row precharge time (tRP) (-7A) 0 1 0 1 0 0 0 0 50H 20ns (-75) 0 1 0 1 0 0 0 0 50H 20ns (-1A) 0 1 0 1 0 0 0 0 50H 20ns Minimum row active to row active delay (tRRD) 0 (-7A) 0 1 1 1 1 0 0 3CH 15ns 28 29 30 (-75) 0 0 1 1 1 1 0 0 3CH 15ns (-1A) 0 0 1 1 1 1 0 0 3CH 15ns 0 1 0 1 0 0 0 0 50H 20ns (-75) 0 1 0 1 0 0 0 0 50H 20ns (-1A) 0 1 0 1 0 0 0 0 50H 20ns 0 0 1 0 1 1 0 1 2DH 45ns (-75) 0 0 1 0 1 1 0 1 2DH 45ns (-1A) 0 0 1 1 0 0 1 0 32H 50ns Minimum /RAS to /CAS delay (tRCD) (-7A) Minimum active to precharge time (tRAS) (-7A) 31 Module bank density 0 0 1 0 0 0 0 0 20H 128Mbytes 32 Address and command setup time before clock (tIS) (-7A) 1 0 0 1 0 0 0 0 90H 0.9ns (-75) 1 0 0 1 0 0 0 0 90H 0.9ns (-1A) 1 0 1 1 0 0 0 0 B0H 1.1ns 1 0 0 1 0 0 0 0 90H 0.9ns 33 34 35 Address and command hold time after clock (tIH) (-7A) (-75) 1 0 0 1 0 0 0 0 90H 0.9ns (-1A) 1 0 1 1 0 0 0 0 B0H 1.1ns Data input setup time before clock (tDS) 0 (-7A) 1 0 1 0 0 0 0 50H 0.5ns (-75) 0 1 0 1 0 0 0 0 50H 0.5ns (-1A) 0 1 1 0 0 0 0 0 60H 0.6ns 0 1 0 1 0 0 0 0 50H 0.5ns 0 1 0 1 0 0 0 0 50H 0.5ns 0.6ns Data input hold time after clock (tDH) (-7A) (-75) 0 1 1 0 0 0 0 0 60H 36 to 61 Superset information (-1A) 0 0 0 0 0 0 0 0 00H 62 SPD Revision 0 0 0 0 0 0 0 0 00H 63 Checksum for bytes 0 to 62 (-7A) 1 0 0 0 1 0 0 1 89H (-75) 1 0 1 1 0 1 0 0 B4H (-1A) 0 1 0 1 1 0 1 0 5AH 64 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH 65 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H 72 Manufacturing location 73 to 90 Manufacturer’s Part number 91 to 92 Revision code 93 to 94 Manufacturing date 95 to 98 Assembly serial number Preliminary Data Sheet E0212E10 (Ver. 1.0) 6 Elpida Memory EBD12RB8ALFA Byte No. Function described Bit7 Bit6 99 to 127 Manufacture specific data Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Block Diagram /RCS0 DQS0 DM0/DQS9 DQS4 DM4/DQS13 DQ 0 DM /CS DQS DQ 1 D0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 DQS1 DM1/DQS10 DQS5 DM5/DQS14 DQ 0 DM /CS DQS DQ 1 D1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 DQS2 DM2/DQS11 DQ 0 DM /CS DQS DQ 1 D5 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQS6 DM6/DQS15 DQ 0 DM /CS DQS DQ 1 D2 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 DQS3 DM3/DQS12 DQ 0 DM /CS DQS DQ 1 D6 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQS7 DM7/DQS16 DQ 0 DM /CS DQS DQ 1 D3 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63 DQS8 DM8/DQS17 DQ 0 DM /CS DQS DQ 1 D7 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 SERIAL PD DQ 0 DM /CS DQS DQ 1 D8 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 CB 0 CB 1 CB 2 CB 3 CB 4 CB 5 CB 6 CB 7 /CS0 BA0, BA1 A0 to A11 A0 /RCS0 /CS0 : D0 to D8 RBA0, RBA1 BA0, BA1 : D0 to D8 RA0 to RA11 /RCAS CKE0 RCKE0 CKE : D0 to D8 /RWE /WE : D0 to D8 Register /WE PCK /PCK /RRAS A1 A2 SA0 SA1 SA2 /CAS /RAS SDA SCL A0 to A11 : D0 to D8 /RAS : D0 to D8 /CAS : D0 to D8 Note : DQ 0 DM /CS DQS DQ 1 D4 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 /RESET VDD D0 to D8 VREF D0 to D8 VSS D0 to D8 VDDID CLK0, /CLK0 Wire per Clock loading table/Wiring diaglams. Remarks : 1. The value of all resistors of DQs, DQSs, DM/DQSs is 22 . : 2. D0 to D8: EDD1208ALTA (4M words 8 bits 4 banks) Preliminary Data Sheet E0212E10 (Ver. 1.0) 7 D0 to D8 VDDQ PLL * Comments EBD12RB8ALFA Differential Clock Net Wiring (CLK0, /CLK0) 0ns (nominal) SDRAM stack PLL 120Ω OUT1 SDRAM stack 120Ω CLK0 IN 240Ω /CLK0 120Ω Register1 (Typically two registers per DIMM) OUT'N' C Feedback 240Ω Register2 Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl be set to 0 ns (nominal). 2. Input, output and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. 4. Termination resistors for feedback path clocks are located after the pins of the PLL. Preliminary Data Sheet E0212E10 (Ver. 1.0) 8 EBD12RB8ALFA Pin Functions (1) CLK, /CLK (input pin): The CLK and the /CLK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CLK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CLK and the /CLK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CLK and the /CLK. /CS (input pin): When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A11 (input pins): Row address (AX0 to AX11) is determined by the A0 to the A11 level at the cross point of the CLK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11) is loaded via the A0 to the A9, the A11 at the cross point of the CLK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected. CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. The CKE level must be kept for 1 CLK cycle (= LCKEPW) at least, that is, if CKE changes at the cross point of the CLK rising edge and the VREF level with proper setup time tIS, at the next CLK rising edge CKE level must be kept with proper hold time tIH. Pin Functions (2) DQ, CB (input and output pins): Data are input to and output from these pins. DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input). VDD and VDDQ (power supply pins): 2.5V is applied. (VDD is for the internal circuit and VDDQ is for the output buffer.) VDDSPD (power supply pin): 2.5V is applied (For serial EEPROM). VSS (power supply pin): Ground is connected. /RESET (input pin): LVCMOS reset input. When /RESET is low, all registers are reset and all outputs are low. Detailed Operation Part, AC Characteristics and Timing Waveforms Refer to the EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Series datasheet (E0136E). DM pins of component device fixed to VSS level on the module board. DIMM /CAS latency = Device CL + 1 for registered type. Preliminary Data Sheet E0212E10 (Ver. 1.0) 9 EBD12RB8ALFA Electrical Specifications Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT –0.5 to +3.6 V 1 Supply voltage relative to VSS VDD, VDDQ –0.5 to +3.6 V 1 Short circuit output current IO 50 mA Power dissipation PD 21 W Operating temperature TA 0 to +70 °C Storage temperature Tstg –55 to +125 °C Notes: 1. Respect to VSS. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC Operating Conditions (TA = 0 to +55°C) Parameter Symbol min. Typ max. Unit Notes Supply voltage VDD, VDDQ 2.3 2.5 2.7 V 1, 2 VSS 0 0 0 V Input reference voltage VREF 0.49 × VDDQ — 0.51 × VDDQ V 1 Termination voltage VTT VREF – 0.04 VREF VREF + 0.04 V 1 DC Input high voltage VIH VREF + 0.18 — VDDQ + 0.3 V 1, 3 DC Input low voltage VIL –0.3 — VREF – 0.18 V 1, 4 DC Input signal voltage VIN (dc) –0.3 — VDDQ + 0.3 V 5 DC differential input voltage VSWING (dc) 0.36 — VDDQ + 0.6 V 6 Notes: 1. 2. 3. 4. 5. 6. All parameters are referred to VSS, when measured. VDDQ must be lower than or equal to VDD. VIH is allowed to exceed VDD up to 4.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns. VIN (dc) specifies the allowable dc execution of each differential input. VSWING (dc) specifies the input differential voltage required for switching. Preliminary Data Sheet E0212E10 (Ver. 1.0) 10 EBD12RB8ALFA DC Characteristics (TA = 0 to 55°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol Operating current (ACTV-PRE) ICC0 Operating current (ACTV-READICC1 PRE) Idle power down standby current ICC2P Idle standby current ICC2N Active power down standby current ICC3P Active standby current ICC3N Operating current (Burst read operation) ICC4R Operating current (Burst write operation) ICC4W Auto refresh current ICC5 Self refresh current ICC6 Notes. 1. 2. 3. 4. 5. 6. 7. Grade -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A max. Unit Test condition Notes TBD mA CKE ≥ VIH, tRC = tRC (min.) 1, 2, 5 TBD mA CKE ≥ VIH, BL = 2, CL = 3.5, tRC = tRC (min.) 1, 2, 5 TBD mA CKE ≤ VIL 4 TBD mA CKE ≥ VIH, /CS ≥ VIH 4 TBD mA CKE ≤ VIL 3 TBD mA CKE ≥ VIH, /CS ≥ VIH tRAS = tRAS (max.) 3 TBD mA CKE ≥ VIH, BL = 2, CL = 3.5 1, 2, 5, 6 TBD mA CKE ≥ VIH, BL = 2, CL = 3.5 1, 2, 5, 6 TBD mA tRFC = tRFC (min.) Input ≤ VIL or ≥ VIH TBD mA Input ≥ VDD – 0.2V Input ≤ 0.2V. These ICC data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one cycle. Data/Data mask transition twice per one cycle. The ICC data on this table are measured with regard to tCK = tCK (min.) in general. DC Characteristics2 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol min. max. Unit Test condition Input leakage current ILI –10 10 µA VDD ≥ VIN ≥ VSS Output leakage current ILO –5 5 µA VDD ≥ VOUT ≥ VSS Output high current IOH –15.2 — mA VOUT = 1.95V Output low current IOL 15.2 — mA VOUT = 0.35V Preliminary Data Sheet E0212E10 (Ver. 1.0) 11 Notes EBD12RB8ALFA Pin Capacitance (TA = 25°C, VDD, VDDQ = 2.5V ± 0.2V) Parameter Symbol Pins Unit Notes Input capacitance CI1 Address, /RAS, /CAS, /WE, TBD /CS, CKE max. pF 1, 3 Input capacitance CI2 CLK, /CLK TBD pF 1, 3 Data and DQS input/output capacitance CO DQ, DQS, CB TBD pF 1, 2, 3 AC Characteristics Synchronous Characteristics -7A Parameter Clock cycle time CL = 2.5 -75 -1A Symbol min. max. min. max. min. max. Unit tCK 7.5 12 7.5 12 10 12 ns CL = 2 7.5 12 10 12 10 12 ns CLK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CLK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK DQ output access time from CLK, /CLK tAC –0.75 0.75 –0.75 0.75 –0.8 0.8 ns DQS output access time from CLK, /CLK tDQSCK –0.75 0.75 –0.75 0.75 –0.8 0.8 ns — 0.5 — 0.5 — 0.6 ns DQS-DQ skew (for DQS and all DQ signals) tDQSQA — 0.5 — 0.5 — 0.6 ns Data out low-impedance time from CLK, /CLKtLZ –0.75 0.75 –0.75 0.75 –0.8 0.8 ns Data out high-impedance time from CLK, /CLK tHZ –0.75 0.75 –0.75 0.75 –0.8 0.8 ns Half clock period tHP tCH, tCL — tCH, tCL — tCH, tCL — DQS-DQ skew (for DQS and associated DQ tDQSQ signals) ns Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQ/DQS output hold time from DQS tQH tHP – 0.75 — tHP – 0.75 — tHP – 1 — ns DQ and DM input setup time tDS 0.5 — 0.5 — 0.6 — ns DQ and DM input hold time tDH 0.5 — 0.5 — 0.6 — ns 1.75 — 1.75 — 2 — ns DQ and DM input pulse width (for each input) tDIPW Write preamble setup time tWPRES 0 — 0 — 0 — ns Write preamble tWPRE 0.25 — 0.25 — 0.25 — tCK Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS input high pulse width tDQSH 0.35 — 0.35 — 0.35 — tCK DQS input low pulse width tDQSL 0.35 — 0.35 — 0.35 — tCK DQS falling edge to CLK setup time tDSS 0.2 — 0.2 — 0.2 — tCK DQS falling edge hold time from CLK tDSH 0.2 — 0.2 — 0.2 — tCK Address and control input setup time tIS 0.9 — 0.9 — 1.1 — ns Address and control input hold time tIH 0.9 — 0.9 — 1.1 — ns Address and control input pulse width tIPW 2.2 — 2.2 — 2.5 — ns Internal write to read command delay tWTR 1 — 1 — 1 — tCK Preliminary Data Sheet E0212E10 (Ver. 1.0) 12 Note EBD12RB8ALFA Synchronous Characteristics Example tCK 7.5 ns Symbol min. max. 10 ns min. max. Unit tCH 3.4 4.1 4.5 5.5 ns tCL 3.4 4.1 4.5 5.5 ns tRPRE 6.75 8.25 9 11 ns tRPST 3 4.5 4 6 ns tWPRE 0.25 — 2.5 — ns tWPST 3 4.5 4 6 ns tDQSS 5.6 9.4 7.5 12.5 ns tDQSH 2.63 — 3.5 — ns tDQSL 2.63 — 3.5 — ns tDSS 1.5 — 2 — ns tDSH 1.5 — 2 — ns tWTR 7.5 — 10 — ns Asynchronous Characteristics -7A Parameter ACT to REF/ACT command period (operation) REF to REF/ACT command period (refresh) ACT to PRE command period -75 -1A Symbol min. max. min. max. min. max. Unit tRC 65 — 65 — 70 — ns tRFC 75 — 75 — 80 — ns tRAS 45 120,000 45 120,000 50 120,000 ns PRE to ACT command period tRP 20 — 20 — 20 — ns ACT to READ/WRITE delay tRCD 20 — 20 — 20 — ns ACT(one) to ACT(another) command period tRRD 15 — 15 — 15 — ns Write recovery time tWR 2 — 2 — 2 — CLK Auto precharge write recovery time + precharge time tDAL TBD — TBD — TBD — ns Mode register set command cycle time tMRD 15 — 15 — 15 — ns Exit self refresh to command tXSNR 75 — 75 — 80 — ns Average periodic Refresh interval tREF1 — 15.6 — 15.6 — 15.6 µs Preliminary Data Sheet E0212E10 (Ver. 1.0) 13 EBD12RB8ALFA Physical Outline Unit: mm 133.35 ± 0.15 128.95 4.00 max (DATUM -A-) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Front) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 1 92 B 64.77 ;; ; ; ;; ; 4.00 min 2.30 (64.48) A 1.27 ± 0.10 49.53 4.00 ± 0.10 184 R 2.00 Detail B (DATUM -A-) 1.27 typ 6.62 0.20 ± 0.15 2.50 ± 0.20 Detail A 2.175 R 0.90 1.00 ± 0.05 3.80 6.35 1.80 ± 0.10 Note: Tolerance on all dimensions ± 0.13 unless otherwise specified. Preliminary Data Sheet E0212E10 (Ver. 1.0) 14 43.18 ± 0.15 93 17.80 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Back) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 3.00 min 10.00 2 – φ 2.50 ± 0.10 EBD12RB8ALFA CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0107 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Preliminary Data Sheet E0212E10 (Ver. 1.0) 15 EBD12RB8ALFA The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107 Preliminary Data Sheet E0212E10 (Ver. 1.0) 16