EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim GENERAL DESCRIPTION EM73469A is an advanced single chip CMOS 4-bit micro-controller. It contains 4K-byte ROM, 244-nibble RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function. EM73469A also contains 6 interrupt sources, 1 input port, 2 bidirection ports, LCD display (32x4), and one high speed timer/counter with melody output. EM73469A has plentiful operating modes (SLOW, IDLE, STOP) intended to reduce the power consumption. FEATURES • Operation voltage • Clock source • • • • • • • • • • • • • • : 1.2V to 1.8V. : Dual clock system. Low-frequency oscillator is Crystal or RC oscillator (32K Hz, connect an external resistor) by mask option and high-frequency oscillator is RC oscillator (connect an external resistor). Instruction set : 109 powerful instructions. Instruction cycle time : Up to 2us for 4 MHz (high speed clock). 122 µs or 244µs by frequency double mask option for 32768 Hz (low speed clock). ROM capacity : 4096 X 8 bits. RAM capacity : 244 X 4 bits. Input port : 1 port (P0). P0(0..3) and IDLE releasing function are available by mask option. Bidirection port : 2 ports (P4, P8). P4.0 and SOUND is available by mask option. P4.1 is shared with HTC external input. P8(0..3) and IDLE releasing function are available by mask option. 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width measurement. High speed timer/counter : One 8-bit high speed timer/counters is programmable for auto load timer, melody output and pulse width measurement. Built-in time base counter : 22 stages. Subroutine nesting : Up to 13 levels. Interrupt : External . . . . . 2 input interrupt sources. Internal . . . . . . 2 Timer overflow interrupts, 1 time base interrupt. 1 high speed timer overflow interrupt. LCD driver : 32 X 4 dots, 1/4, 1/3, 1/2 static six kinds of duty selectable, 1/2 bias, 1/3 bias. Power saving function : SLOW, IDLE, STOP operation mode. Package type : Chip form 61 pins. APPLICATIONS EM73469A is suitable for application in family applicance, consumer products, hand held games and the toy controller. * This specification are subject to be changed without notice. 1.9.2001 1 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr FUNCTION BLOCK DIAGRAM RESET Reset Control CLK LXOUT LXIN Clock Generator Clock Generator (slow) Timing Generator Sleep Mode Control System Control Data pointer Time Base ROM Timer/Counter (TA,TB) Stack pointer ACC Data Bus Interrupt Control Instruction Decoder Instruction Register Stack ALU ROM Flag Z C S PC G HR LR DP SP I/O Control P0.0/WAKEUP0 P0.1/WAKEUP1 P0.2/WAKEUP2 P0.3/WAKEUP3 LCD P4.0/SOUND P4.1TRGH P4.2 P4.3 P8.0(INT1)/WAKEUPA P8.1(TRGB)/WAKEUPB P8.2(INT0)/WAKEUPC P8.3(TRGA)/WAKEUPD SOUND SEG0~SEG31 HTC COM0~COM3 VA VB V1 V2 V3 PIN DESCRIPTIONS Symbol V DD V SS RESET CLK LXIN LXOUT P0(0..3)/WAKEUP0..3 P4.0/SOUND Pin-type Function Power supply (+) Power supply (-) RESET-A System reset input signal, low active mask option : none pull-up OSC-I RC clock source connecting pin OSC-B/OSC-H1 Crystal/RC connecting pin for low speed clock source OSC-B Crystal connecting pin for low speed clock source INPUT-K 4-bit input port with IDLE releasing function mask option : wakeup enable, negative edge release, pull-up wakeup enable, negative edge release, none wakeup enable, positive edge release, pull-down wakeup enable, positive edge release, none wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none I/O-R 1-bit bidirection I/O port or inverse sound effect output mask option : SOUND enable, high current push-pull SOUND disable, open-drain * This specification are subject to be changed without notice. 1.9.2001 2 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim PIN DESCRIPTIONS Symbol Pin-type P4.1/TRGH I/O-Q P4(2,3) I/O-Q P8.0(INT1)/WAKEUPA, I/O-S P8.2(INT0)/WAKEUPC P8.1(TRGB)/WAKEUPB I/O-S P8.3(TRGA)/WAKEUPD SOUND VA,VB, V1, V2, V3 COM0~COM3 SEG0~SEG31 TEST Function SOUND disable, low current push-pull SOUND disable, normal current push-pull SOUND disable, high current push-pull 1-bit bidirection I/O port with HTC external input mask option : NMOS open-drain PMOS open-drain low current push-pull normal current push-pull high current push-pull 2-bit bidirection I/O port with high current source mask option : NMOS open-drain PMOS open-drain low current push-pull normal current push-pull high current push-pull 2-bit bidirection I/O port with external interrupt source input and IDLE releasing function mask option : wakeup enable, low current push-pull wakeup enable, normal current push-pull wakeup disable, open-drain wakeup disable, low current push-pull wakeup disable, normal current push-pull 2-bit bidirection I/O port with time/counter A,B external input and IDLE releasing function mask option : wakeup enable, low current push-pull wakeup enable, normal current push-pull wakeup disable, open-drain wakeup disable, low current push-pull wakeup disable, normal current push-pull Melody output Connect the capacitors for LCD bias voltage LCD common output pins LCD segment output pins Tie Vss as package type, no connecting as COB type. FUNCTION DESCRIPTIONS PROGRAM ROM (4K X 8 bits) 4 K x 8 bits program ROM contains user's program and some fixed data. The basic structure of program ROM can be divided into 5 parts. 1. Address 000h: Reset start address. 2. Address 002h - 00Ch : 6 kinds of interrupt service routine entry addresses. 3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh, 036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h, 07Eh, 086h. 4. Address 000h - 7FFh : LCALL subroutine entry address. 5. Address 000h - FFFh : Except used as above function, the other region can be used as user's program region. * This specification are subject to be changed without notice. 1.9.2001 3 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr address 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh 086h .. . 4096 x 8 bits Reset start address INT0; External interrupt service routine entry address HTCI; High speed timer interrupt service entry address TRGA; Timer/counterA interrupt service routine entry address TRGB; Timer/counter B interrupt service routine entry address TBI; Time base interrupt service routine entry address INT1; External interrupt service routine entry address SCALL, subroutine call entry address .. . FFFh User's program and fixed data are stored in the program ROM. User's program is according the PC value to send next executed instruction code. Fixed data can be read out by two ways. (1) Table-look-up instruction : Table -look-up instruction is depended on the Data Pointer (DP) to indicate to ROM address, then to get the ROM code data. LDAX LDAXI Acc ← ROM[DP]L Acc ← ROM[DP] H,DP+1 DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code data. First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can get the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI". PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction. LDIA #07h; STADPL STADPM STADPH : LDL #00h; LDH #03h; LDAX STAMI LDAXI STAM ; ORG 777h DATA 56h; : ; DP3-0 ← 07h ; DP5-4 ← 07h ; DP8-6 ← 07h, Load DP=777h ; ACC ← 6h ; RAM[30] ← 6h ; ACC ← 5h ; RAM[31] ← 5h DATA RAM ( 244-nibble ) There is total 244 - nibble data RAM from address 00 to F3h Data RAM includes 3 parts: zero page region, stacks and data area. * This specification are subject to be changed without notice. 1.9.2001 4 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim Increment Address 00h~0Fh 10h~1Fh 20h~2Fh 30h~3Fh 40h~4Fh : B0h ~ BFh C0h ~ CFh D0h ~ DFh E0h ~ EFh F0h ~ F3h zero page LCD display RAM level 0 level 4 level 8 level C level 1 level 5 level 9 level 2 level 6 level A level 3 level17 level B LCD display RAM: RAM address from 20h ~ 3Fh are the LCD display RAM area, the RAM data of this region can't be operated by instruction LDHL xx and EXHL. ZERO-PAGE: From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero-page addressing mode for the instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y". PROGRAM EXAMPLE: To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM. STD #07h, 03h ; RAM[03] ← 07h CLR 0Eh,2 ; RAM[0Eh]2 ← 0 STACK: There are 13-level (maximum) stack for user using for subroutine (including interrupt and CALL). User can assign any level be the starting stack by giving the level number to stack pointer (SP). When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address will be saved into stack until return from those subroutines, the PC value will be restored by the data saved in stack. DATA AREA: Except the special area used by user, the whole RAM can be used as data area for storing and loading general data. ADDRESSING MODE (1) Indirect addressing mode: Indirect addressing mode indicates the RAM address by specified HL register. For example: LDAM ; Acc ← RAM[HL] STAM ; RAM[HL] ← Acc (2) Direct addressing mode: Direct addressing mode indicates the RAM address by immediate data. * This specification are subject to be changed without notice. 1.9.2001 5 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT For example: LDA x ; Acc← RAM[x] ary n i m i l e Pr STA x ; RAM[x] ← Acc (3) Zero-page addressing mode For zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit manupulated operation directly. For example: STD #k,y ; RAM[y] ← #k ADD #k,y; RAM[y] ← RAM[y] + #k PROGRAM COUNTER (4K ROM) Program counter ( PC ) is composed by a 12-bit counter, which indicates the next executed address for the instruction of program ROM. For a 4K - byte size ROM, PC can indicate address form 000h - FFFh, for BRANCH and CALL instrcutions, PC is changed by instruction indicating. (1) Branch instruction: SBR a Object code: 00aa aaaa Condition: SF=1; PC ← PC 11-6.a ( branch condition satisified ) PC Hold original PC value+1 a a a a a a SF=0; PC← PC +1( branch condition not satisified ) PC Original PC value + 1 LBR a Object code: 1100 aaaa aaaa aaaa Condition: SF=1; PC ← a ( branch condition satisified ) PC a a a a a a a a a a a a SF=0 ; PC ← PC + 2 ( branch condition not satisified ) PC Original PC value + 2 (2) Subroutine instruction: SCALL a Object code: 1110 nnnn Condition : PC ← a ; a=8n+6 ; n=1..15 ; a=86h, n=0 PC 0 0 0 0 a a a a a a a a a a a a a a a LCALL a Object code: 0100 0 aaa aaaa aaaa Condition: PC ← a PC 0 a a a a * This specification are subject to be changed without notice. 1.9.2001 6 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim RET Object code: 0100 1111 Condition: PC ← STACK[SP]; SP + 1 PC The return address stored in stack RT I Object code: 0100 1101 Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1 PC The return address stored in stack (3) Interrupt acceptance operation: When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into PC,The interrupt vectors are as following: INT0 (External interrupt from P8.2) PC 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 TRGA (Timer A overflow interrupt) PC 0 0 0 0 0 TRGB (Time B overflow interrupt) PC 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 TBI (Time base interrupt) PC 0 0 0 INT1 (External interrupt from P8.0) PC 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (4) Reset operation: PC 0 (5) Other operations: For 1-byte instruction execution: PC + 1 For 2-byte instruction execution: PC + 2 ACCUMULATOR * This specification are subject to be changed without notice. 1.9.2001 7 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr Accumulator is a 4-bit data register for temporary data. For the arithematic, logic and comparative opertion .., ACC plays a role which holds the source data and result. FLAGS There are four kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), SF ( Status flag ) and GF ( General flag ), these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation. All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after RTI instruction executed. (1) Carry Flag ( CF ) The carry flag is affected by following operation: a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1", in another word, if the operation has no carry-out, CF will be "0". b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF will be "0", in another word, if no borrow-in, CF will be "1". c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction operation. d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0". For TTSFC instruction, the content of CF sends into SF then set itself "1". (2) Zero Flag ( ZF ) ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1", otherwise, the ZF will be "0". (3) Status Flag ( SF ) The SF is affected by instruction operation and system status. a. SF is initiated to "1" for reset condition. b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise, branch condition will not be satisified by SF = 0. (4) General Flag ( GF ) GF is a one bit general purpose register which can be set, clear, test by instruction SGF, CGF and TGS. PROGRAM EXAMPLE: Check following arithematic operation for CF, ZF, SF * This specification are subject to be changed without notice. 1.9.2001 8 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim CF - LDIA #00h; LDIA #03h; ADDA #05h; ADDA #0Dh; ADDA #0Eh; ZF 1 0 0 0 0 SF 1 1 1 0 0 ALU The arithematic operation of 4 - bit data is performed in ALU unit. There are 2 flags can be affected by the result of ALU operation, ZF and SF. The operation of ALU can be affected by CF only. ALU STRUCTURE ALU supported user arithematic operation function, including : addition, subtraction and rotaion. DATA BUS ALU ZF CF SF GF ALU FUNCTION (1) Addition: For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function. The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1", otherwise, not equal "0", ZF will be "0". When the addition operation has a carry-out, CF will be "1", otherwise, CF will be "0". EXAMPLE: Operation 3+4=7 7+F=6 0+0=0 8+8=0 Carry Zero 0 1 0 1 0 0 1 1 (2) Subtraction: For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function. The subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "1". * This specification are subject to be changed without notice. 1.9.2001 9 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr EXAMPLE: Operation 8-4=4 7-F= -8(1000) 9-9=0 Carry 1 0 1 Zero 0 0 1 (3) Rotation: There are two kinds of rotation operation, one is rotation left, the other is rotation right. RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data will be hold in CF. MSB LSB ACC CF RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and the shift out data will be hold in CF. MSB LSB ACC CF PROGRAM EXAMPLE: To rotate Acc right and shift a "1" into the MSB bit of Acc. TTCFS; CF ← 1 RRCA; rotate Acc right and shift CF=1 into MSB. HL REGISTER HL register are two 4-bit registers, they are used as a pair of pointer for the address of RAM memory and also 2 independent temporary 4-bit data registers. For some instruction, L register can be a pointer to indicate the pin number ( Port4 ). HL REGISTER STRUCTURE 3 2 1 0 3 2 1 0 H REGISTER L REGISTER HL REGISTER FUNCTION * This specification are subject to be changed without notice. 1.9.2001 10 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim (1) For instruction : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH, HL register used as a temporary register. PROGRAM EXAMPLE: Load immediate data "5h" into L register, "Dh" into H register. LDL #05h; LDH #0Dh; (2) For instruction LDAM, STAM, STAMI .., HL register used as a pointer for the address of RAM memory. PROGRAM EXAMPLE: Store immediate data #Ah into RAM of address 35h. LDL #5h; LDH #3h; STDMI #0Ah; RAM[35] ← Ah (3) For instruction : SELP, CLPL, TFPL, L regieter be a pointer to indicate the bit of I/O port. When LR = 0 indicate P4.0 PROGRAM EXAMPLE: To set bit 0 of Port4 to "1" LDL #00h; SEPL ; P4.0 ← 1 STACK POINTER (SP) Stack pointer is a 4-bit register which stores the present stack level number. Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition . When a new subroutine is accepted, the SP will be decreased one automatically, in another word, if returning from a subroutine, the SP will be increased one. The data transfer between ACC and SP is by instruction of "LDASP" and "STASP". DATA POINTER (DP) Data pointer is a 12-bit register which stores the address of ROM can indicate the ROM code data specified by user (refer to data ROM). CLOCK AND TIMING GENERATOR The clock generator is supported by a single clock system, the clock source comes from crystal (resonator) or RC oscillation is decided by mask option, the working frequency range is 480 K Hz to 4 MHz depending on the working voltage. CLOCK GENERATOR STRUCTURE There are two clock generator for system clock control. P14 is the status register for the CPU status. P16, P19 and P22 are the system clock mode control ports. * This specification are subject to be changed without notice. 1.9.2001 11 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr fc High-frequency generator P14 CLK Low-frequency generator LXOUT System clock mode control fs LXIN P16 P19 P22 Mask option for choose Crystal or RC oscillator System control LXIN LXIN LXOUT Crystal connection RC connection SYSTEM CLOCK MODE CONTROL The system clock mode controller can start or stop the high-frequency and low-frequency clock oscillator and switch between the basic clocks. EM73469A has four operation modes (NORMAL, SLOW,IDLE and STOP operation modes). STOP operation mode I/O wakeup High osc : stopped Low osc : stopped Command (P16) Reset Reset Command (P16) Command (P22) Command (P22) Reset release RESET operation High osc : oscillating Low osc : oscillating NORMAL operation mode Reset SLOW operation mode High osc : stopped Low osc : oscillating Command (P19) Reset I/O or internal timer wakeup IDLE (CPU stops) High osc : stopped Low osc : oscillating Operation Mode NORMAL SLOW IDLE STOP Oscillator High, Low frequency Low frequency Low frequency None System Clock High frequency clock Low frequency clock CPU stops CPU stops * This specification are subject to be changed without notice. Available function One instruction cycle LCD, High speed timer 8/fc LCD, High speed timer 4/fs or 8/fs by mask option LCD All disable 1.9.2001 12 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT NORMAL OPERATION MODE inary Prelim The 4-bit µc is in the NORMAL operation mode when the CPU is reseted. This mode is a dual clock system (high-frequency(fc) and low-frequency(fs) clocks oscillating). It can be changed to SLOW or STOP operation mode by the command register (P22 or P16). The instruction cycle is 8/fc in NORMAL operation mode. LCD display and high speed timer/counter with melody output are available for the NORMAL operation mode. SLOW OPERATION MODE The SLOW operation mode is a single clock system (low-frequency(fs) clock oscillating). It can be changed to the DUAL operation mode with the commoand register (P22), STOP operation mode with P16 and IDLE operation mode with P19. The instruction cycle is 4/fs or 8/fs by frequency double mask option in SLOW operation mode. LCD display and high speed timer/counter with melody output are available for the SLOW operation mode. P22 3 * 2 SOM 1 * SOM 0 1 P14 3 * 0 * Initial value : 0000 Select operation mode NORMAL operation mode SLOW operation mode 2 WKS 1 0 LFS CPUS Initial value : *000 LFS 0 1 Low-frequency status LXIN source is not stable LXIN source is stable WKS 0 1 Wakeup status Wakeup not by internal timer Wakeup by internal timer CPUS 0 1 CPU status NORMAL operation mode SLOW operation mode Port14 is the status register for CPU. P14.0 (CPU status) and P14.1 (Low-frequency status) are read-only bits. p14.2 (wakeup status) will be set to "1" when CPU is wake-up by internal timer. P14.2 will be cleared to "0" when user out data to P14. IDLE OPERATION MODE The IDLE operation mode suspends all SLOW operations except for the low-frequency clock and LCD driver. It retains the internal status with low power consumption without stopping the clock function and LCD display. LCD display is available for the IDLE operation mode. Sound generator is disabled in this mode. The IDLE operation mode will be wakeup and return to the SLOW operation mode by the internal timing generator or I/O pins (P0(0..3)/WAKEUP 0..3 or P8(0..3)/WAKEUPA..D). * This specification are subject to be changed without notice. 1.9.2001 13 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr P19 3 2 1 IDME IDME 0 1 * * 0 Initial value : 0000 SIDR Enable IDLE mode Enable IDLE mode Reserved SIDR 0 0 0 1 1 0 1 1 Select IDLE releasing condition P0(0..3), P8(0..3) pin input P0(0..3), P8(0..3) pin input and 1 sec signal P0(0..3), P8(0..3) pin input and 0.5 sec signal P0(0..3), P8(0..3) pin input and 15.625 ms signal STOP OPERATION MODE The STOP operation mode suspends system operation and holds the internal status immediately before the suspension with low power consumption. This mode will be released by reset or I/O pins (P0(0..3)/ WAKEUP 0..3 or P8(0..3)/WAKEUP A..D). LCD display and high speed timer/counter with melody output are disabled in the mode. P16 3 2 SPME 1 0 SWWT SPME 0 1 * * Initial value : 0000 Enable STOP mode Enable STOP mode Reserved SWWT 0 0 0 1 1 0 1 1 Set wake-up warm-up time wait normal frequency ready (26/fc) wait slow frequency ready (214/fs) Reserved Reserved TIME BASE INTERRUPT ( TBI ) The time base can be used to generate a fixed frequency interrupt. There are 8 kinds of frequencies can be selected by setting P25. P25 3 2 1 0 initial value : 0000 0 0 0 0 0 1 1 1 1 1 P25 0 x 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 x x 0 1 0 1 0 1 0 1 x NORMAL operation mode Interrupt disable Interrupt frequency LXIN / 23 Hz Interrupt frequency LXIN / 24 Hz Interrupt frequency LXIN / 25 Hz Interrupt frequency LXIN / 214 Hz Interrupt frequency LXIN / 21 Hz Interrupt frequency LXIN / 26 Hz Interrupt frequency LXIN / 28 Hz Interrupt frequency LXIN / 210 Hz Reserved SLOW operation mode Interrupt disable Reserved Reserved Reserved Interrupt frequency LXIN / 214 Hz Reserved Interrupt frequency LXIN / 26 Hz Interrupt frequency LXIN / 28 Hz Interrupt frequency LXIN / 210 Hz Reserved TIMER / COUNTER ( TIMERA, TIMERB ) Timer/counters can support user three special functions: 1. Even counter 2. Timer. 3. Pulse-width measurement. * This specification are subject to be changed without notice. 1.9.2001 14 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim These three functions can be executed by 2 timer/counter independently. For timerA, the counter data is saved in timer register TAH, TAM, TAL, which user can set counter initial value and read the counter value by instruction "LDATAH(M,L), STATAH(M,L)" and timer register is TBH, TBM, TBL and W/R instruction "LDATBH (M,L), STATBH (M,L)". The basic structure of timer/counter is composed by two same structure counter, these two counters can be set initial value and send counter value to timer register, P28 and P29 are the command ports for timerA and timer B, user can choose different operation mode and different internal clock rate by setting these two ports. When timer/counter overflow, it will generate a TRGA(B) interrupt request to interrupt control unit. INTERRUPT CONTROL TRGB request TRGA request DATA BUS 12 BIT COUNTER 12 BIT COUNTER EVENT COUNTER CONTROL P8.3/ TRGA internal clock EVENT COUNTER CONTROL TIMER CONTROL TIMER CONTROL PULSE-WIDTH MEASUREMENT CONTROL PULSE-WIDTH MEASUREMENT CONTROL P28 IPSA TMSA P29 TMSB P8.1/ TRGB MUX internal clock high speed timer/counter IPSB TIMER/COUNTER CONTROL P8.1/TRGB, P8.3/TRGA are the external timer inputs for timerB and timerA, they are used in event counter and pulse-width measurement mode. Timer/counter command port: P28 is the command port for timer/counterA and P29 is for the timer/ counterB. Port 28 3 2 TMSA 1 0 IPSA Initial state: 0000 Port 29 3 2 TMSB 1 0 TIMER/COUNTER MODE SELECTION TMSA (B) Function description 0 0 Stop 0 1 Event counter mode 1 0 Timer mode 1 1 Pulse width measurement mode IPSB Initial state: 0000 INTERNAL PULSE-RATE SELECTION IPSA NORMAL mode SLOW mode Reserved 0 0 LXIN/23 Hz 0 1 LXIN/27 Hz LXIN/27 Hz 11 1 0 LXIN/2 Hz LXIN/211 Hz 1 1 LXIN/215 Hz LXIN/215 Hz INTERNAL PULSE-RATE SELECTION IPSB NORMAL mode SLOW mode 0 0 Depend on high speed timer/counter 0 1 LXIN/25 Hz LXIN/25 Hz 9 1 0 LXIN/2 Hz LXIN/29 Hz 1 1 LXIN/213 Hz LXIN/213 Hz * This specification are subject to be changed without notice. 1.9.2001 15 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr TIMER/COUNTER FUNCTION Timer/counterA can be programmable for timer, event counter and pulse width measurement. Each timer/ counter can execute any one of these functions independly. EVENT COUNTER MODE For event counter mode, timer/counter increases one at any rising edge of P8.1/TRGB for timerB (P8.3/ TRGA for timer A). When timerB (timerA) counts overflow, it will give interrupt control an interrupt request TRGB (TRGA). P8.1/TRGB (P8.3/TRGA) TimerB (TimerA) value n n+1 n+2 n+3 n+4 n+5 n+6 PROGRAM EXAMPLE: Enable timerA with P28 LDIA #0100B; OUTA P28; Enable timerA with event counter mode TIMER MODE For timer mode, timer/counter increase one at any rising edge of internal pulse. User can choose 4 kinds of internal pulse rate by setting IPSB for timerB (IPSA for timerA). When timer/counter counts overflow, TRGB (TRGA) will be generated to interrupt control unit. Internal pulse TimerB (TimerA )value n n+1 n+2 n+3 n+4 n+5 n+6 n+7 PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock LXlN=32KHz LDIA #0100B; EXAE; enable mask 2 EICIL 110111B; interrupt latch ←0, enable EI LDIA #0AH; STATAL; LDIA #00H; STATAM; LDIA #0FH; STATAH; LDIA #1000B; OUTA P28; enable timerA with internal pulse rate: LXIN/23 Hz NOTE: The preset value of timer/counter register is calculated as following procedure. Internal pulse rate: LXIN/23 ; LXIN = 32KHz The time of timer counter count one = 23 /LXIN = 8/32768=0.244ms The number of internal pulse to get timer overflow = 60 ms/ 0.244ms = 245.901= 0F6H The preset value of timer/counter register = 1000H - 0F6H = 0F0AH PULSE WIDTH MEASUREMENT MODE * This specification are subject to be changed without notice. 1.9.2001 16 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim For the pulse width measurement mode, the counter only incresed by the rising edge of internal pulse rate as external timer/counter input (P8.1/TRGB, P8.3/TRGA ), interrupt request will be generated as soon as timer/counter count overflow. P8.1/TRGB(P8.3/TRGA) Internal pulse n TimerB(TimerA) value n+1 n+2 n+3 n+4 n+5 PROGRAM EXAMPLE: Enable timerA by pulse width measurement mode. LDIA #1100b; OUTA P28; Enable timerA with pulse width measurement mode. HIGH SPEED TIMER/COUNTER EM73469A has one 8-bit high speed timer/counter (HTC). It supports three special functions : auto load timer, melody output and pulse width measurement modes. The HTC is available for the NORMAL and SLOW operation mode. The HTC can be set initial value and send counter value to counter registers (P11 and P10), P31 is the command port for HTC, user can choose different operation mode and different internal clockrate by setting the port. The timer/counter increase one at the rising edge of internal pulse. The HTC can generate an overflow interrupt (HTCI) when it overflows. The HTCI cannot be generated when the HTC is in the melody mode or disabled. Output data ÷2 FHTC P4.0/SOUND P31(3,2) 8-bit binary counter mask option SOUND P31(1,0) Overflow HTCI interrupt Timer/counter B Reload XIN P11 P10 Input data P4.1/TRGH Data bus P31 is the command register of the 8-bit high speed timer/counter. P31 3 2 HTMS 1 0 Initial value : 0000 HIPS HTMS Mode selection HIPS 0 0 1 1 Stop Auto load timer mode Melody mode Pulse width measurement mode 0 0 1 1 0 1 0 1 0 1 0 1 Clock rate selection NORMAL mode SLOW mode 0 LXIN/2 Hz LXIN/20 Hz 2 LXIN/2 Hz LXIN/22 Hz 4 CLK/2 Hz Reserved CLK/26 Hz Reserved P11 and P10 are the counter registers of the 8-bit high speed timer/counter. P10 is the lower nibble register and P11 is the higher nibble register. (HT is the value of counter registers.) P11 3 2 1 0 Higher nibble register P10 3 2 1 0 Lower nibble register * This specification are subject to be changed without notice. Initial value : 0000 0000 (HT) 1.9.2001 17 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr ** FHTC=[(XIN/2X)/(100H-HT)]/2, HT=0~255 ** Example : LXIN=32K Hz, HIPS=01, HT=11110000B=0F0H. ⇒FHTC=[(32K Hz/22)/(100H-0f0H)]/2=256 Hz. LDIA OUTA LDIA OUTA LDIA OUTA #1111B P11 #0000B P10 #1001B P31 The value of 8-bit binary up counter can be presetted by P10 and P11. The value of registers can loaded into the HTC when the counter starts counting or occurs overflow. If user write value to the registers before the next overflow occurs, the preset value can be changed. The preset value will be changed when users output the different data to P10 and P11. The count value of HTC can be read from P10 and P11. The value is unstable when user read the value during counting. Thus, user must disable the counter before reading the value. The P4.0/SOUND and SOUND pins will output the squre wave in the melody mode. When the CPU is not in the melody mode, the P4.0/SOUND is high and SOUND is low. The P4.1/RGH pin will be the input pin in the pulse width measurement mode. User must output high to P4.1/ TRGH and then it can be the HTC external input pin. When the HTC is disabled, the P4.1 pin is a normal I/ O pin. INTERRUPT FUNCTION There are 6 interrupt sources, 2 external interrupt sources, 4 internal interrupt sources. Multiple interrupts are admitted according the priority. Type External Internal Internal Internal Internal External Interrupt source Priority Externalinterrupt(INT0) High speed timer overflow interrupt (HTCI) TimerA overflow interrupt (TRGA) TimerB overflow interrupt (TRGB) Time base interrupt(TBI) Externalinterrupt(INT1) Interrupt Interrupt Program ROM Latch Enable condition entry address 1 2 3 4 5 6 IL5 IL4 IL3 IL2 IL1 IL0 EI=1 EI=1,MASK3=1 EI=1,MASK2=1 EI=1,MASK1=1 EI=1,MASK0=1 002H 004H 006H 008H 00AH 00CH INTERRUPT STRUCTURE MASK0 MASK1 MASK1 MASK2 MASK3 Reset by system reset and program instruction INT1 r0 TBI r1 TRGB r2 TRGA r3 HTCI r4 INT0 r5 IL0 IL1 IL2 IL3 IL4 IL5 Priority checker Reset by system reset and program instruction Set by program instruction EI Interrupt request * This specification are subject to be changed without notice. Entry address generator Interrupt entry address 1.9.2001 18 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim Interrupt controller: IL0-IL5 : Interrupt latch. Hold all interrupt requests from all interrupt sources. ILr can not be set by program, but can be reset by program or system reset, so IL only can decide which interrupt source can be accepted. MASK0-MASK3 EI : Except INT0, MASK register can promit or inhibit all interrupt sources. : Enable interrupt Flip-Flop can promit or inhibit all interrupt sources, when interrupt happened, EI is cleared to "0" automatically, after RTI instruction happened, EI will be set to "1" again. Priority checker : Check interrupt priority when multiple interrupts happened. INTERRUPT FUNCTION The procedure of interrupt operation: 1. Push PC and all flags to stack. 2. Set interrupt entry address into PC. 3. Set SF= 1. 4. Clear EI to inhibit other interrupts happened. 5. Clear the IL for which interrupt source has already be accepted. 6. To excute interrupt subroutine from the interrupt entry address. 7. CPU accept RTI, restore PC and flags from stack. Set EI to accept other interrupt requests. PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA" LDIA #1100B; EXAE; set mask register "1100B" EICIL 111111B ; enable interrupt F.F. LCD DRIVER EM73469A can directly drive the liquid crystal display (LCD) and has 32 segment, 4 common output pins (1/ 2 bias, 1/3 bias). There are total 32x4 dots can be display. The V1, V2, V3, VA, VB, VDD and VSS pins are the LCD bias generator. CONTROL OF LCD DRIVER The LCD driver control command register is P27. When LDC is 0, the LCD is disabled, the COM and SEG pins are VSS. When LDC is 1, the LCD driver enables. When the CPU is reseted or during the STOP operation mode, the LCD driver is disabled. Port27 2 1 0 Initial value : 0000 LDC LDC 0 1 DUTY LCD display control LCD display disable LCD display enable DUTY Driving method select 0 0 0 1/4 duty (1/3 bias) 0 0 1 1/4 duty (1/2 bias) 0 1 0 1/3 duty (1/3 bias) 0 1 1 1/3 duty (1/2 bias) 1 0 0 1/2 duty (1/2 bias) 1 0 1 Static 1 1 * Reserved The LCD display data is stored in the display data area of the data memory (RAM). The display data area begins with address 20H during reset. The LCD display data area ia as below : * This specification are subject to be changed without notice. 1.9.2001 19 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr RAM COM3 COM2 COM1 address bit3 bit2 bit1 SEG0 20H SEG1 21H SEG2 22H : : : : SEG30 3EH SEG31 3FH The relation between LCD display data and driving method Driving method bit3 bit2 bit1 bit0 1/4 duty COM3 COM2 COM1 COM0 1/3 duty COM2 COM1 COM0 1/2 duty COM1 COM0 Static COM0 LCD frame frequency : According to the drive method to set the frame frequency. Duty Frame frequency (Hz) 1/4 duty 64 x (4/4) = 64 1/3 duty 64 x (4/3) = 85 1/2 duty 64 x (4/2) = 128 Static 64 COM0 bit0 PROGRAM EXAMPLE : LDIA #0001B ; 1/4 duty, 1/2 bias OUTA P27 LDIA #1001B ; enable LCD OUTA P27 LCD DRIVING METHODS There are six kinds of driving methods can be selected by DUTY (P27.0~P27.2). The drivinf waveforms of LCD driver are as below : • VDD=1.5V (1) 1/4 duty (1/3 bias) (2 ) 1/3 duty (1/3 bias) VDD VDD 4.5V V3 VB V1 3V V2 V2 VA 4.5V V3 3V 1.5V VA VB VSS V1 1.5V VSS V3 V2 V1 Vss V3 V2 V1 Vss COM1 V3 V2 V1 Vss V3 V2 V1 Vss COM2 V3 V2 V1 Vss V3 V2 V1 Vss COM3 V3 V2 V1 Vss SEG0 V3 V2 V1 Vss V3 V2 V1 Vss SEG0-COM0 ON V3 V2 V1 Vss -V1 -V2 -V3 V3 V2 V1 Vss -V1 -V2 -V3 SEG0-COM1 OFF V3 V2 V1 Vss -V1 -V2 -V3 V3 V2 V1 Vss -V1 -V2 -V3 COM0 Frame Frame * This specification are subject to be changed without notice. 1.9.2001 20 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim (3) 1/4 duty (1/2 bias) V3 3V V3 VB V1 3V VA VB VSS V1 VDD 3V V3 V3 1.5V VA VB VSS V1 1.5V VSS COM0 V3 V1 Vss V3 V1 Vss V3 V1 Vss COM1 V3 V1 Vss V3 V1 Vss V3 V1 Vss COM2 V3 V1 Vss V3 V1 Vss COM3 V3 V1 Vss SEG0 V3 V1 Vss V3 V1 Vss V3 V1 Vss V3 V1 Vss -V1 -V3 V3 V1 Vss -V1 -V3 V3 V1 Vss -V1 -V3 V3 V1 Vss -V1 -V3 V3 V1 Vss -V1 -V3 V3 V1 Vss -V1 -V3 VA VB SEG0-COM1 OFF Frame Frame Frame V1 1.5V VSS V3 Vss ON SEG0-COM0 ON 3V V2 V2 V2 1.5V (6) static VDD VDD V2 VA (5) 1/2 duty (1/2 bias) (4) 1/3 duty (1/2 bias) VDD OFF V3 V1 Vss V3 Vss -V3 V3 Vss -V3 Frame RESETTING FUNCTION When CPU in normal working condition and RESET pin holds in low level for three instruction cycles at least, then CPU begins to initialize the whole internal states, and when RESET pin changes to high level, CPU begins to work in normal condition. The CPU internal state during reset condition is as following table : Hardware condition in RESET state Program counter Status flag Interrupt enable flip-flop ( EI ) MASK0 ,1, 2, 3 Interrupt latch ( IL ) P10, 11,14, 16, 19, 25, 27, 28, 29, 31 P4, 8, 23, 24 Both oscillator Initial value 0000h 01h 00h 00h 00h 00h 0Fh Start oscillation The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option. The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD. RESET * This specification are subject to be changed without notice. 1.9.2001 21 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr EM73469A I/O PORT DESCRIPTION : Port 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 E E E I Input function Input port , wakeup function ---Input port ---Input port, wakeup function, -----CPU status -- Output function E E I I I I I I I I I I I ---Output port, P4.0/SOUND ---Output port -High speed timer/counter High speed timer/counter --Clear P14.0 to 0 -STOP mode control register --IDLE mode control register --Slow mode control register --Timebase control register -LCD control register Timer/counter A control register Timer/counter B control register -HTC control register * This specification are subject to be changed without notice. Note low nibble high nibble 1.9.2001 22 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim ABSOLUTE MAXIMUM RATINGS Items Sym. Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Ratings V DD V IN VO PD T OPR T STG Conditions -0.5V to 6V -0.5V to VDD+0.5V -0.5V to VDD+0.5V 300mW 0oC to 50oC -55oC to 125oC TOPR=50 oC RECOMMANDED OPERATING CONDITIONS Items Sym. Supply Voltage V DD Input Voltage V IH V IL FC Fs Operating Frequency Ratings Condition 1.2V to 1.8V 1.2V to 1.8V 0.90xVDD to VDD 0V to 0.10xVDD 4MHz 32KHz 500KHz<Fc<4MHz by RC osc Fs=32KHz by crystal osc CLK, VSS (RC osc), R=330KΩ LXIN, LXOUT (crystal osc) DC ELECTRICAL CHARACTERISTICS (VDD=1.5±0.2V, VSS=0V, TOPR=25oC) Parameters Supply current Hysteresis voltage Input current Sym. Min. Typ. I DD - 200 300 µA - 8 7 1 -6 1.1 4 3 0.1 4 -4 -30 -3 - 6 1 ±1 -90 -10 - µA µA µA V V µA µA µA µA µA µA V 1.0 - - V 300K 400K 0.2 1 560K V µA Ω V HYS+ V HYSI IH I IL Output voltage Leakage current Input resistor V OH V OL I LO R IN 0.50VDD 0.20VDD Max. Unit 0.75VDD 0.40VDD * This specification are subject to be changed without notice. Conditions VDD=1.7V,no load,NORMAL mode, Fc=4MHz (RC osc : R=330KΩ), Fs=32KHz VDD=1.7V,no load,SLOW mode, Fs=32KHz VDD=1.7V,IDLE mode VDD=1.7V, STOP mode RESET, P0, P8 P0, Pull-down, VIH=VDD P0, Pull-up, VIH=VSS P0, None RESET, VDD=1.7V, VO=1.7/0V Normal current Push-pull, VDD=1.7V,VIL=0.2V Low current Push-pull, VDD=1.7V,VIL=0.2V High current push-pull, SOUND VDD=1.7V, IOH=-100µA Normal current push-pull, VDD=1.3V, IOH=-10µA VDD=1.3V,IOL=100µA Open-drain, VDD=1.7V, VO=1.7V RESET 1.9.2001 23 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr RESET PIN TYPE TYPE RESET-A RESET mask option OSCILLATION PIN TYPE TYPE OSC-B TYPE OSC-H1 LXIN LXIN Crystal Osc. RC Osc. 1.2MΩ LXOUT TYPE OSC-I CLK RC Osc. 330KΩ INPUT PIN TYPE TYPE INPUT-K positive edge input data detector WAKEUP mask option : mask option negative edge detector I/O PIN TYPE TYPE I/O-N TYPE I/O-Q : mask option * This specification are subject to be changed without notice. : mask option 1.9.2001 24 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim TYPE I/O-R TYPE I/O-S path B Input data path A path B SEL path A TYPE I/O-Q : mask option Path A : Path B : Output data latch Output data Special function output TYPE I/O-N Special function control input Input data Output data latch Output data WAKEUP function mask option For set and clear bit of port instructions, data goes through path A from output data latch to CPU. For input and test instructions, data from output pin go through path B to CPU and the output data latch will be set to high. * This specification are subject to be changed without notice. 1.9.2001 25 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr VSS 1 CLK 2 LXOUT 3 LXIN 4 VDD 61 60 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VB VA V3 V2 V1 PAD DIAGRAM 59 58 57 56 55 54 53 52 51 50 49 48 47 5 46 SEG6 45 SEG7 44 SEG8 43 SEG9 42 SEG10 41 SEG11 P4.3 6 40 SEG12 P4.2 7 39 SEG13 P4.1/TRGH 8 38 SEG14 37 SEG15 P4.0/SOUND 9 36 SEG16 35 SEG17 (0,0) EM73469A P8.3 11 34 SEG18 P8.2 12 33 SEG19 P8.1 13 32 SEG20 P8.0 14 31 SEG21 RESET 15 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 P0.0 P0.2 19 20 21 22 23 24 25 26 27 28 29 30 P0.3 16 17 18 P0.1 10 TEST SOUND Unit : µm Chip Size : 2160 x 2390 µm Note : For PCB layout, IC substrate must be floated or connected to VSS. * This specification are subject to be changed without notice. 1.9.2001 26 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol VSS CLK LXOUT LXIN VDD P4.3 P4.2 P4.1/TRGH P4.0/SOUND SOUND P8.3 P8.2 P8.1 P8.0 RESET TEST P0.3 P0.2 P0.1 P0.0 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 X -906.4 -921.4 -921.4 -921.4 -904.7 -921.4 -921.4 -921.4 -921.4 -920.5 -921.4 -921.4 -921.4 -921.4 -921.4 -762.7 -638.1 -518.2 -389.9 -270.0 -145.9 -26.0 93.9 213.8 333.7 453.6 573.5 693.4 813.3 933.2 921.4 921.4 921.4 921.4 921.4 921.4 921.4 921.4 921.4 921.4 * This specification are subject to be changed without notice. Y 1009.1 877.3 637.5 517.6 397.1 205.3 65.7 -71.6 -211.2 -347.4 -474.9 -594.8 -717.8 -837.7 -979.7 -1036.4 -1036.4 -1036.4 -1036.4 -1036.4 -1036.4 -1036.4 -1036.4 -1036.4 -1036.4 -1036.4 -1036.4 -1036.4 -1036.4 -1036.4 -888.8 -768.9 -649.0 -529.1 -409.2 -289.3 -169.4 -49.5 70.4 190.3 1.9.2001 27 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Symbol SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VB VA V3 V2 V1 X 921.4 921.4 921.4 921.4 921.4 921.4 933.2 813.3 693.4 573.5 453.6 333.7 213.8 93.9 -26.0 -145.9 -265.8 -385.7 -505.6 -625.5 -745.4 * This specification are subject to be changed without notice. Y 310.2 430.1 550.0 669.9 789.8 909.7 1037.3 1037.3 1037.3 1037.3 1037.3 1037.3 1037.3 1037.3 1037.3 1037.3 1037.3 1037.3 1037.3 1037.3 1037.3 1.9.2001 28 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT INSTRUCTION TABLE inary Prelim (1) Data Transfer Mnemonic LDA x LDAM LDAX LDAXI LDH #k LDHL x LDIA #k LDL #k STA x STAM STAMD STAMI STD #k,y STDMI #k THA TLA Object code (binary) 0110 1010 xxxx xxxx 0101 1010 0110 0101 0110 0111 1001 kkkk 0100 1110 xxxx xx00 1101 kkkk 1000 kkkk 0110 1001 xxxx xxxx 0101 1001 0111 1101 0111 1111 0100 1000 kkkk yyyy 1010 kkkk 0111 0110 0111 0100 Operation description Acc←RAM[x] Acc ←RAM[HL] Acc←ROM[DP] L Acc←ROM[DP] H,DP+1 HR←k LR←RAM[x],HR←RAM[x+1] Acc←k LR←k RAM[x]←Acc RAM[HL]←Acc RAM[HL]←Acc, LR-1 RAM[HL]←Acc, LR+1 RAM[y]←k RAM[HL]←k, LR+1 Acc←HR Acc←LR Byte 2 1 1 1 1 2 1 1 2 1 1 1 2 1 1 1 Cycle 2 1 2 2 1 2 1 1 2 1 1 1 2 1 1 1 Flag C Z Z Z Z Z Z Z Z Z Z Z S 1 1 1 1 1 1 1 1 1 1 C C' 1 C' 1 1 (2) Rotate Mnemonic RLCA RRCA Object code (binary) 0101 0000 0101 0001 Operation description ←CF←Acc← →CF→Acc→ Byte 1 1 Cycle 1 1 Flag C Z C Z C Z S C' C' Flag Z Z Z Z Z Z Z Z Z Z Z Z S C' C' C' C' C' C' C' C C C C' 1.9.2001 29 (3) Arithmetic operation Mnemonic ADCAM ADD #k,y ADDA #k ADDAM ADDH #k ADDL #k ADDM #k DECA DECL DECM INCA Object code (binary) 0111 0100 0110 0111 0110 0110 0110 0101 0111 0101 0101 0000 1001 kkkk yyyy 1110 0101 kkkk 0001 1110 1001 kkkk 1110 0001 kkkk 1110 1101 kkkk 1100 1100 1101 1110 Operation description Acc←Acc + RAM[HL] + CF RAM[y]←RAM[y] +k Acc←Acc+k Acc←Acc + RAM[HL] HR←HR+k LR←LR+k RAM[HL]←RAM[HL] +k Acc←Acc-1 LR←LR-1 RAM[HL]←RAM[HL] -1 Acc←Acc + 1 * This specification are subject to be changed without notice. Byte 1 2 2 1 2 2 2 1 1 1 1 Cycle 1 2 2 1 2 2 2 1 1 1 1 C C - EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr INCL INCM SUBA #k SBCAM SUBM #k 0111 1110 0101 1111 0110 1110 0111 kkkk 0111 0010 0110 1110 1111 kkkk LR←LR + 1 RAM[HL]←RAM[HL]+1 Acc←k-Acc Acc←RAM[HLl - Acc - CF' RAM[HL]←k - RAM[HL] 1 1 2 1 2 Operation description Byte 1 1 2 1 2 C - Z Z Z Z Z C' C' C C C (4) Logical operation Mnemonic 1110 0110 kkkk 1011 1110 1110 kkkk 1110 0100 kkkk 1000 1110 1100 kkkk 1001 Acc←Acc&k Acc←Acc & RAM[HL] RAM[HL]←RAM[HL]&k Acc←Acc k Acc ←Acc RAM[HL] RAM[HL]←RAM[HL] k Acc←Acc^RAM[HL] 2 1 2 2 1 2 1 Operation description Byte Acc↔RAM[x] Acc↔HR Acc↔LR Acc↔RAM[HL] LR↔RAM[x], HR↔RAM[x+1] 2 1 1 1 2 Operation description Byte If SF=1 then PC←PC11-6.a5-0 elsenull If SF= 1 then PC←a else null 1 2 Operation description Byte -- 0110 0111 0110 0110 0111 0110 0111 ---- ANDA #k ANDAM ANDM #k ORA #k ORAM ORM #k XORAM Object code (binary) Cycle 2 1 2 2 1 2 1 C - Flag Z Z Z Z Z Z Z Z S Z' Z' Z' Z' Z' Z' Z' (5) Exchange Mnemonic EXA x EXAH EXAL EXAM EXHL x Object code (binary) 0110 1000 xxxx xxxx 0110 0110 0110 0100 0101 1000 0100 1100 xxxx xx00 Cycle Flag C Z S 2 2 2 1 - Z Z Z Z 1 1 1 1 2 - - 1 Flag C Z S 1 - - 1 2 - - 1 C Flag Z S C C C C - Z Z Z Z Z Z Z' Z' Z' C Z' C (6) Branch Mnemonic SBR a LBR a Object code (binary) 00aa aaaa 1100 aaaa aaaa aaaa Cycle (7) Compare Mnemonic CMP #k,y CMPA x CMPAM CMPH #k CMPIA #k CMPL #k Object code (binary) 0100 1011 kkkk yyyy 0110 1011 xxxx xxxx 0111 0011 0110 1110 1011 kkkk 1011 kkkk 0110 1110 0011 kkkk k-RAM[y] RAM[x]-Acc RAM[HL] - Acc k - HR k - Acc k-LR * This specification are subject to be changed without notice. 2 2 1 2 1 2 Cycle 2 2 1 2 1 2 1.9.2001 30 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT (8) Bit manipulation Mnemonic CLM b CLP p,b CLPL CLR y,b SEM b SEP p,b SEPL SET y,b TF y,b TFA b TFM b TFP p,b TFPL TT y,b TTP p,b Object code (binary) 1111 00bb 0110 1101 11bb pppp 0110 0000 0110 1100 11bb yyyy 1111 01bb 0110 1101 01bb pppp 0110 0010 0110 1100 01bb yyyy 0110 1100 00bb yyyy 1111 10bb 1111 11bb 0110 1101 00bb pppp 0110 0001 0110 1100 10bb yyyy 0110 1101 10bb pppp inary Prelim Operation description Byte RAM[HL]b←0 PORT[p]b←0 PORT[LR3-2+4]LR1-0←0 RAM[y]b←0 RAM[HL]b←1 PORT[p]b←1 PORT[LR3-2+4]LRl-0←1 RAM[y]b←1 SF←RAM[y]b' SF←Acc b' SF←RAM[HL]b' SF←PORT[p]b' SF←PORT[LR3-2+4]LR1-0' SF←RAM[y]b SF←PORT[p]b 1 2 1 2 1 2 1 2 2 1 1 2 1 2 2 Operation description Byte Cycle 1 2 2 2 1 2 2 2 2 1 1 2 2 2 2 C - Flag Z - S 1 1 1 1 1 1 1 1 * * * * * * * Flag Z - S - (9) Subroutine Mnemonic Object code (binary) LCALL a 0100 0aaa aaaa aaaa SCALL a 1110 nnnn Cycle 2 2 C - 1 2 - - - SP←SP + 1, PC←STACK[SP] 1 2 - - - Operation description Byte STACK[SP]←PC, SP←SP -1, PC←a STACK[SP]←PC, SP←SP - 1, PC←a, a = 8n +6 (n=1~15),0086h (n =0) RET 0100 1111 (10) Input/output Mnemonic INA INM OUT OUTA OUTM p p #k,p p p Object code (binary) 0110 1111 0100 pppp 0110 1111 1100 pppp 0100 1010 kkkk pppp 0110 1111 000p pppp 0110 1111 100p pppp Acc←PORT[p] RAM[HL]←PORT[p] PORT[p]←k PORT[p]←Acc PORT[p]←RAM[HL] 2 2 2 2 2 Operation description Byte Cycle 2 2 2 2 2 C - Flag Z Z - S Z' Z' 1 1 1 C 0 Flag Z - S 1 1 * (11) Flag manipulation Mnemonic CGF SGF TFCFC Object code (binary) 0101 0111 0101 0101 0101 0011 GF←0 GF←1 SF←CF', CF←0 * This specification are subject to be changed without notice. 1 1 1 Cycle 1 1 1 1.9.2001 31 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT ary n i m i l e Pr TGS TTCFS TZS 0101 0100 0101 0010 0101 1011 SF←GF SF←CF, CF←1 SF←ZF 1 1 1 Operation description Byte 1 1 1 1 - - * * * (12) Interrupt control Mnemonic CIL r DICIL r EICIL r EXAE RTI Object code (binary) 0110 0011 11rr rrrr 0110 0011 10rr rrrr 0110 0011 01rr rrrr 0111 0101 0100 1101 IL←IL & r EIF←0,IL←IL&r EIF←1,IL←IL&r MASK↔Acc SP←SP+1,FLAG.PC ←STACK[SP],EIF ←1 2 2 2 1 1 Operation description Byte no operation 1 Cycle 2 2 2 1 2 Flag Z * S 1 1 1 1 * Flag C Z - S - Flag Z Z Z Z Z Z Z Z Z Z Z - S 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C * (13) CPU control Mnemonic NOP Object code (binary) 0101 0110 Cycle 1 (14) Timer/Counter & Data pointer & Stack pointer control Mnemonic LDADPL LDADPM LDADPH LDASP LDATAL LDATAM LDATAH LDATBL LDATBM LDATBH STADPL STADPM STADPH STASP STATAL STATAM STATAH STATBL STATBM STATBH Object code (binary) 0110 1010 1111 1100 0101 0110 1111 1101 0101 0110 1111 1110 0101 0110 1111 1111 0110 1010 1111 0100 0101 0110 1111 0101 0101 0110 1111 0110 0110 1010 1111 1000 0101 0110 1111 1001 0101 0110 1111 1010 0110 1001 1111 1100 0110 1001 1111 1101 0110 1001 1111 1110 0110 1001 1111 1111 0110 1001 1111 0100 0110 1001 1111 0101 0110 1001 1111 0110 0110 1001 1111 1000 0110 1001 1111 1001 0110 1001 1111 1010 Operation description Acc←[DP] L Acc←[DP] M Acc←[DP] H Acc←SP Acc←[TA] L Acc←[TA] M Acc←[TA] H Acc←[TB] L Acc←[TB]M Acc←[TB]H [DP] L←Acc [DP] M←Acc [DP] H←Acc SP←Acc [TA] L←Acc [TA]M←Acc [TA]H←Acc [ TB]L←Acc [TB]M←Acc [TB]H←Acc * This specification are subject to be changed without notice. Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C - 1.9.2001 32 EM73469A 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT inary Prelim **** SYMBOL DESCRIPTION Symbol Description Symbol HR PC SP A CC CF SF EI MASK ΤΑ RAM[HL] ROM[DP] L [DP] L [DP] H H register Program counter Stack pointer Accumulator Carry flag Status flag Enable interrupt register Interrupt mask Timer/counter A Data memory (address : HL ) Low 4-bit of program memory Low 4-bit of data pointer register High 4-bit of data pointer register LR DP STACK[SP] FLAG ZF GF IL PORT[p] ΤΒ RAM[x] ROM[DP] H [DP] M [TA]L([TB]L) [TA]M([TB]M) Middle 4-bit of timer/counter A (timer/counter B) register Transfer Addition Logic AND Logic XOR Concatenation 8-bit RAM address 4-bit or 5-bit port address 6-bit interrupt latch Contents of bit assigned by bit 1 to 0 of LR Bit 3 to 2 of LR [TA]H([TB]H) LR 1-0 LR3-2 ↔ -- ← + & ^ . x p r ' #k y b PC 11-6 a 5-0 * This specification are subject to be changed without notice. Description L register Data pointer Stack specified by SP All flags Zero flag General flag Interrupt latch Port ( address : p ) Timer/counter B Data memory (address : x ) High 4-bit of program memory Middle 4-bit of data pointer register Low 4-bit of timer/counter A (timer/counter B) register High 4-bit of timer/counter A (timer/counter B) register Exchange Substraction Logic OR Inverse operation 4-bit immediate data 4-bit zero-page address Bit address Bit 11 to 6 of program counter Bit 5 to 0 of destination address for branch instruction 1.9.2001 33