EMC EM73201CP

EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
m
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GENERAL DESCRIPTION
EM73201 is an advanced single chip CMOS 4-bit micro-controller. It contains 2K-byte ROM, 52-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, one 12-bit timer/counter for the kernel function.
EM73201 also contains 5 interrupt sources, 4 I/O ports (including 1 input port, 1 output port for LED driving,
2 bidirection I/O ports) built-in watch-dog-time counter and one high frequency clock output for modulating
infrared signal.
Except low-power consumption and high speed, EM73201 also have a sleep and hold mode operation for the
power saving function.
EM73201 is suitable for application in family appliance, consumer products and toy controller.
FEATURES
• Operation voltage
• Clock source
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
: 2.4V to 6.0V (clock frequency: 32 KHz to 5 MHz)
: Single clock system for RC , Crystal and external clock source, available by
mask option.
Instruction set
: 109 powerful instructions.
Instruction cycle time
: Up to 2µs for 4.19MHz .
ROM capacity
: 2048 x 8 bits.
RAM capacity
: 52 x 4 bits.
Input port
: 1 port (P0).
Output port
: 1 port (P1).
Bidirection I/O port
: 2 ports (P7,P8).
12-bit timer/counter
: One 12-bit timer/counter is programmable for timer, even counter and pulse
width measurement mode.
Built-in time base counter : 22 stages.
Subroutine nesting
: Up to 13 levels.
Interrupt
: External interrupt . . . . . . 2 input interrupt sources.
Internal interrupt . . . . . . 1 timer overflow interrupt,
1 time base interrupt.
The built-in watch-dog-timer counter is available by mask option.
Low voltage reset is available by mask option.
High frequency clockout: Programmable high frequency clock output for modulating infrared signal.
Power saving function
: Sleep mode and Hold mode.
Package type
: EM73201H
Chip form 22 pins.
EM73201AP
DIP
18 pins.
EM73201BK
SKINNY 22 pins.
EM73201CP
DIP
16 pins.
APPLICATIONS
EM73201 is suitable for application in family appliance, consumer products and the toy controller.
* This specification are subject to be changed without notice.
7.20.1999
1
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
m
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P
PIN CONFIGURATIONS
EM73201AP
P8.3
P7.0
P7.1
P7.2
P7.3
P1.0
P1.1
P1.2
VSS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
EM73201BK
P8.0
P8.3
P7.0
P7.1
P7.2
P7.3
P1.0
P1.1
P1.2
P1.3
VSS
VDD
P8.2
XOUT
XIN
TEST
P0.3
P0.2
P0.1
P0.0
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
EM73201CP
VDD
P7.0
P7.2
P7.3
P1.0
P1.1
P1.2
VSS
VDD
P8.2
RESET
P8.1
XOUT
XIN
TEST
P0.3
P0.2
P0.1
P0.0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RESET
XOUT
XIN
TEST
P0.3
P0.2
P0.1
P0.0
EM73201AP must enable low voltage reset
FUNCTIONAL BLOCK DIAGRAM
XIN/CLK XOUT/NC
RESET
Reset
Control
WDT
Clock
Generator
Sleep Mode
Control
Timing
Generator
System Control
Data pointer
Instruction Decoder
Instruction Register
Time
Base
ROM
12 bits
timer
counter
Stack pointer
ACC
Data Bus
Interrupt
Control
Stack
ALU
ROM
Flag
Z
C
S
G
HR
LR
PC
I/O Control
P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3
* This specification are subject to be changed without notice.
P7.0
P7.1
P7.2
P7.3
P8.0/INT1
P8.1
P8.2/INT0
P8.3/TRGA
P1.0/CLKOUT
P1.1
P1.2
P1.3
Infrared Control
7.20.1999
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
m
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PIN DESCRIPTIONS
Symbol
Pin- Type
VDD
Vss
RESET
RESET-A
XIN/CLK
XOUT/NC
P(0..3)/WAKEUP0..3
OSC-A/OSC-C
OSC-A
INPUT-C
P1.0/CLKOUT
OUTPUT-B
P1(1..3)
OUTPUT-A
P7(0..3)
I/O-U
P8.0/INT1,P8.2/INT0
I/O-W
P8.3/TRGA
I/O-V
P8.1
I/O-W
Function
Power supply (+)
Power supply (-)
System reset input signal, low active
mask option:
none
pull-up
Crystal/RC or external clock source connecting pin
Crystal connecting pin or NC for RC osc. type
4-bit input port with Sleep/Hold releaseing func tion
mask option : none
pull-up
pull-down
1-bit high current output pin for LED driving or clock output for
infrared signal
mask option : open-drain, normal sink
open-drain, high sink
normal source, normal sink
normal source, high sink
3-bit high current output pin for LED driving
mask option : open-drain, normal sink
open-drain, high sink
normal source, normal sink
normal source, high sink
4-bit bidirection I/O port
mask option : open-drain, normal sink
low source, normal sink
normal source, normal sink
normal source, high sink
high source, high sink
2-bit bidirection I/O pins with external interrupt sources input
mask option : open-drain, normal sink
low source, normal sink
normal source, normal sink
normal source, high sink
high source, high sink
1-bit bidirection I/O pin with timer/counter A external input
mask option : open-drain, normal sink
low source, normal sink
normal source, normal sink
normal source, high sink
high source, high sink
1-bit bidirection I/O pin
mask option : open-drain, normal sink
low source, normal sink
normal source, normal sink
normal source, high sink
high source, high sink
* This specification are subject to be changed without notice.
7.20.1999
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
FUNCTION DESCRIPTIONS
inary
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PROGRAM ROM ( 2K X 8 bits )
2 K x 8 bits program ROM contains user's program and some fixed data .
The basic structure of program ROM can be divided into 5 parts.
1. Address 000h: Reset start address.
2. Address 002h - 00Ch: 4 kinds of interrupt service rountine entry addresses .
3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh,
036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h ,07Eh, 086h .
4. Address 000h - 7FFh : LCALL subroutine entry address
5. Address 7E0h - 7FFh : The data region for 5-to-8 bits data conversion table .
6. Address 000h - 7FFh : Except used as above function, the other region can be used as user's program region.
address
000h
002h
004h
006h
008h
00Ah
00Ch
00Eh
086h
..
.
2048 x 8 bits
Reset start address
INT0; External interrupt service routine entry address
TRGA, Timer/counterA interrupt service routine entry address
TBI; Time base interrupt service routine entry address
INT1; External interrupt service routine entry address
SCALL, subroutine call entry address
..
.
7FFh
User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code. Fixed data can be read out by two ways.
(1) Table-look-up instruction:
Table-look-up instruction is depended on the Data Pointer ( DP ) to indicate to ROM address, then to get
the ROM code data.
LDAX
LDAXI
Acc ← ROM[DP]L
Acc ← ROM[DP]H,DP+1
DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM
code data. First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH",
then user can get the lower nibble of ROM code data by instruction "LDAX" and higher nibble by
instruction "LDAXI".
PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction.
LDIA #07h;
STADPL
STADPM
STADPH
:
LDL #00h;
LDH #03h;
LDAX
; [DP]L ← 07h
; [DP]M ← 07h
; [DP]H ← 07h, Load DP=777h
; ACC ← 6h
* This specification are subject to be changed without notice.
7.20.1999
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
STAMI
LDAXI
STAM
:
; RAM[30] ← 6h
; ACC ← 5h
; RAM[31] ← 5h
inary
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ORG 777h
DATA 56h;
:
DATA RAM ( 52-nibble )
There is total 52 - nibble data RAM from address 00 to 33h
Data RAM includes 3 parts: zero page region, stacks and data area.
Increment
Address
Level 0
Level 1
Level 2
Level 3
10h - 1Fh
Level 4
Level 5
Level 6
Level 7
20h - 2Fh
Level 8
Level 9
Level 10
Level 11
30h - 33h
Level 12
Stack
Increment
00h - 0Fh
Zero-page
ZERO- PAGE:
From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero-page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE:
To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.
STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]2 ← 0
STACK:
There are 13 - level (maximum) stack for user using for subroutine (including interrupt and CALL). User
can assign any level be the starting stack by giving the level number to stack pointer (SP).
When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address
will be saved into stack until return from those subroutines, the PC value will be restored by the data saved
in stack.
DATA AREA:
Except the special area used by user, the whole RAM can be used as data area for storing and loading general
data.
ADDRESSING MODE
(1) Indirect addressing mode:
Indirect addressing mode indicates the RAM address by specified HL register.
For example: LDAM ; Acc ← RAM[HL]
STAM ; RAM[HL] ← Acc
(2) Direct addressing mode:
Direct addressing mode indicates the RAM address by immediate data.
* This specification are subject to be changed without notice.
7.20.1999
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
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For example: LDA x ; Acc← RAM[x]
STA x ; RAM[x] ← Acc
(3) Zero-page addressing mode
For zero-page region, user can using direct addressing to write or do any arithematic, comparsion
or bit manupulated operation directly.
For example: STD #k,y ; RAM[y] ← #k
ADD #k,y; RAM[y] ← RAM[y] + #k
PROGRAM COUNTER (2K ROM)
Program counter ( PC ) is composed by a 12-bit counter, which indicates the next executed address for the
instruction of program ROM.
For a 2 K - byte size ROM, PC can indicate address form 000h - 7FFh, for BRANCH and CALL instrcutions,
PC is changed by instruction indicating.
(1) Branch instruction:
SBR a
Object code: 00aa aaaa
Condition: SF=1; PC ← PC 11-6.a ( branch condition satisified )
PC Hold original PC value+1 a a
a
a
a
a
SF=0; PC← PC +1( branch condition not satisified)
PC
Original PC value + 1
LBR a
Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC ← a ( branch condition satisified)
PC
0 a
a
a
a
a
a
a
a
a
a
a
SF=0 ; PC ← PC + 2 ( branch condition not satisified )
PC
Original PC value + 2
(2) Subroutine instruction:
SCALL a
Object code: 1110 nnnn
Condition : PC ← a ; a=8n+6 ; n=1..15 ; a=86h, n=0
PC
0
0
0
0
a
a
a
a
a
a
a
a
LCALL a
Object code: 0100 0 aaa aaaa aaaa
Condition: PC ← a
* This specification are subject to be changed without notice.
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
PC 0
a
a
a
a
inary
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a
a
a
a
a
a
a
RET
Object code: 01 00 1 1 1 1
Condition: PC ← STACK[SP]; SP + 1
PC
The return address stored in stack
RT I
Object code: 0100 1101
Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1
PC
The return address stored in stack
(3) Interrupt acceptance operation:
When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC,The interrupt vectors are as following:
INT0 (External interrupt from P8.2)
PC 0
0
0
0
0
0
0
0
0
0
1
0
TRGA (Timer A overflow interrupt)
PC 0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
0
TBI (Time base interrupt)
PC 0
0
0
INT1 (External interrupt from P8.0)
PC 0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
(4) Reset operation:
PC 0
(5) Other operations:
For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
ACCUMULATOR
Accumulator is a 4-bit data register for temporary data . For the arithematic, logic and comparative opertion
.., ACC plays a role which holds the source data and result .
FLAGS
* This specification are subject to be changed without notice.
7.20.1999
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
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There are four kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), SF ( Status flag ) and GF ( General flag ),
these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation .
All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction executed .
(1) Carry Flag ( CF )
The carry flag is affected by following operation:
a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1",
in another word, if the operation has no carry-out, CF will be "0".
b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF
will be "0", in another word, if no borrow-in, CF will be "1".
c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction
operation.
d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after
rotation.
e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0".
For TTSFC instruction, the content of CF sends into SF then set itself "1".
(2) Zero Flag ( ZF )
ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1",
otherwise, the ZF will be "0".
(3) Status Flag ( SF )
The SF is affected by instruction operation and system status .
a. SF is initiated to "1" for reset condition .
b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise,
branch condition will not be satisified by SF = 0 .
(4) General Flag ( GF )
GF is a one bit general purpose register which can be set, clear, test by instruction SGF, CGF and TGS.
PROGRAM EXAMPLE:
Check following arithematic operation for CF, ZF, SF
LDIA #00h;
LDIA #03h;
ADDA #05h;
ADDA #0Dh;
ADDA #0Eh;
CF
-
ZF
1
0
0
0
0
* This specification are subject to be changed without notice.
SF
1
1
1
0
0
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
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ALU
The arithematic operation of 4 - bit data is performed in ALU unit . There are 2 flags can be affected by
the result of ALU operation, ZF and SF . The operation of ALU can be affected by GF only .
ALU STRUCTURE
ALU supported user arithematic operation function, including : addition, subtraction and rotaion.
DATA BUS
ALU
ZF CF SF GF
ALU FUNCTION
(1) Addition:
For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function.
The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1",
otherwise, not equal "0", ZF will be "0", When the addition operation has a carry-out. CF will be "1",
otherwise, CF will be "0".
EXAMPLE:
Operation
3+4=7
7+F=6
0+0=0
8+8=0
Carry
0
1
0
1
Zero
0
0
1
1
(2) Subtraction:
For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function . The
subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will
be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result
of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "0".
EXAMPLE:
Operation
8-4=4
7-F= -8(1000)
9-9=0
Carry
1
0
1
Zero
0
0
1
* This specification are subject to be changed without notice.
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
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(3) Rotation:
There are two kinds of rotation operation, one is rotation left, the other is rotation right.
RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data
will be hold in CF.
MSB LSB
ACC
CF
RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and the
shift out data will be hold in CF.
MSB LSB
ACC
CF
PROGRAM EXAMPLE: To rotate Acc right and shift a "1" into the MSB bit of Acc .
TTCFS; CF ← 1
RRCA; rotate Acc right and shift CF=1 into MSB.
HL REGISTER
HL register are two 4-bit registers, they are used as a pair of pointer for the address of RAM memory and also
2 independent temporary 4-bit data registers. For some instruction, L register can be a pointer to indicate the
pin number ( Port7 ) .
HL REGISTER STRUCTURE
3 2
1 0
3 2 1 0
H REGISTER L REGISTER
HL REGISTER FUNCTION
(1) For instruction : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH, HL register used as a
temporary register .
PROGRAM EXAMPLE: Load immediate data "5h" into L register, "Dh" into H register.
LDL #05h;
LDH #0Dh;
(2) For instruction LDAM, STAM, STAMI .., HL register used as a pointer for the address of RAM memory.
PROGRAM EXAMPLE: Store immediate data #Ah into RAM of address 35h.
* This specification are subject to be changed without notice.
7.20.1999
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
LDL #5h;
LDH #3h;
STDMI #0Ah; RAM[35] ← Ah
inary
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(3) For instruction : SELP, CLPL, TFPL, L regieter be a pointer to indicate the bit of I/O port.
When LR = C - F, indicate P7.0 - P7.3
PROGRAM EXAMPLE: To set bit 2 of Port7 to "1"
LDL #0Eh;
SEPL ; P7.2 ← 1
STACK POINTER (SP)
Stack pointer is a 4-bit register which stores the present stack level number.
Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition
. When a new subroutine is accepted, the SP will be decreased one automatically, in another word, if
returning from a subroutine, the SP will be increased one .
The data transfer between ACC and SP is by instruction of "LDASP" and "STASP".
DATA POINTER (DP)
Data pointer is a 12-bit register which stores the address of ROM can indicate the ROM code data
specified by user (refer to data ROM).
CLOCK AND TIMING GENERATOR
The clock generator is supported by a single clock system, the clock source comes from crystal (resonator
or RC oscillation is decided by mask option . the working frequency range is 32 K Hz to 5 MHz depending
on the working voltage.
CLOCK AND TIMING GENERATOR STRUCTURE
The clock generator connects outside compoments ( crystal or resonator by XIN and XOUT pin for crystal
osc type, Resistor and capacitor by CLK pin for RC osc type, these two type is decided by mask option ).
the clock generator generates a basic system clock "fc".
When CPU sleeping, the clock generator will be stoped until the sleep condition released.
The system clock control generates 4 basic phase signals ( S1, S2, S3, S4 ) and system clock .
Mask option
sleep
Mask option for choose Crystal or RC oscillation
XIN/CLK
clock generator
fc
System clock
System clock control
XOUT
S1
* This specification are subject to be changed without notice.
S2
S3
S4
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4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
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XIN/CLK
XIN/CLK
XOUT
XOUT
Crystal connection
RC connection
CLOCK AND TIMING GENERATOR FUNCTION
The frequency of fc is the oscillation frequency for XIN, XOUT by crystal ( resonator) or for CLK by RC
osc.
When CPU sleeps, the XOUT pin will be in "high" state .
When user chooses RC osc, XOUT pin is no used .
The instruction cycle equal 8 basic clock fc.
1 instructure cycle = 8 / fc
TIMING GENERATOR AND TIME BASE
The timing generator produces the system clock from basic clock pulse which can be normal mode or slow
mode clock.
1 instruction cycle = 8 basic clock pulses
There are 22 stages time base .
Prescaler
fc
1 2 3
4
Binary counter
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
When working in the single clock mode, the timebase clock source is come from fc that is RC oscillation.
Time base provides basic frequency for following function:
1. TBI (time base interrupt) .
2. Timer/counter, internal clock source.
3. Warm-up time for sleep - mode releasing.
TIME BASE INTERRUPT (TBI )
The time base can be used to generate a fixed frequency interrupt . There are 8 kinds of frequencies can be
selected by setting "25"
Single clock mode
P25 3 2 1 0
( initial value 0000 )
0 0 x x: Interrupt disable
0 1 0 0: Interrupt frequency XIN / 210 Hz
0 1 0 1: Interrupt frequency XIN / 211 Hz
0 1 1 0: Interrupt frequency XIN / 212 Hz
0 1 1 1: Interrupt frequency XIN / 213 Hz
1 1 0 0: Interrupt frequency XIN / 29 Hz
1 1 0 1: Interrupt frequency XIN / 28 Hz
1 1 1 0: Interrupt frequency XIN / 215 Hz
1 1 1 1: Interrupt frequency XIN / 217 Hz
1 0 x x: Reserved
* This specification are subject to be changed without notice.
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
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TIMER / COUNTER ( TIMERA)
Timer/counters can support user three special functions:
1. Even counter
2. Timer.
3. Pulse-width measurement.
These three functions can be executed by timer/counter.
For timerA, the counter data is saved in timer register TAH, TAM, TAL, which user can set counter
initial value and read the counter value by W/B instruction "LDATAH (B,L), STATAH (B,L)".
The counter can be set initial value and send counter value to timer register. P28 is the command port
for timerA , user can choose different operation mode and different internal clock rate by setting the
port. When timer/counter overflow, it will generate a TRGA interrupt request to interrupt control unit.
INTERRUPT CONTROL
TRGA request
DATA BUS
12 BIT COUNTER
EVENT COUNTER CONTROL
P8.3/
TRGA
TIMER CONTROL
internal clock
PULSE-WIDTH MEASUREMENT
CONTROL
P28
TMSA
IPSA
TIMER/COUNTER CONTROL
P8.3/TRGA is the external timer inputs for timerA, it used in event counter and pulse-width
measurement mode.
Timer/counter command port: P28 is the command port for timer/counterA.
Port 28 3
2
1
0
TMSA IPSA
Initial state: 0000
TIMER/COUNTER MODE SELECTION
TMSA
Function description
00
Stop
0 1
Event counter mode
10
Timer mode
11
Pulse width measurement mode
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
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INTERNAL PULSE-RATE SELECTION
IPSA
Function description
00
XIN/210 Hz
0 1
XIN/2
1 0
XIN/2
11
XIN/2
14
Hz
18
Hz
22
Hz
TIMER/COUNTER FUNCTION
EVENT COUNTER MODE
For event counter mode, timer/counter increases one at any rising edge of P8.3/TRGA for timerA. When
timerA counts overflow, it will give interrupt control an interrupt request TOFIA.
P8.3/TRGA
TimerA value
n
n+1
n+2
n+3
n+4
n+5
n+6
PROGRAM EXAMPLE: Enable timerA with P28.
LDIA #0100B;
OUTA P28; Enable timerA with event counter mode
TIMER MODE
For timer mode ,timer/counter increase one at any rising edge of internal pulse . User can choose 4 kinds
of internal pulse rate by setting IPSA for timerA.
When timer/counter counts overflow, TRGA will be generated to interrupt control unit.
Internal pulse
TimerA value
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock XlN=4MHz
LDIA #0100B;
EXAE; enable mask 2
EICIL 110111B; interrupt latch ←0, enable EI
LDIA #06H;
STATAL;
* This specification are subject to be changed without notice.
7.20.1999
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
m
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LDIA #01H;
STATAM;
LDIA #0FH;
STATAH;
LDIA #1000B;
OUTA P28; enable timerA with internal pulse rate: XIN/210 Hz
NOTE:
The preset value of timer/counter register is calculated as following procedure.
Internal pulse rate: XIN/210 ; XIN = 4MHz
The time of timer counter count one = 210 /XIN = 1024/4000=0.256ms
The number of internal pulse to get timer overflow = 60 ms/ 0.256ms = 234.375 = 0EAH
The preset value of timer/counter register = 1000H - 0EAH = 0F16H
PULSE WIDTH MEASUREMENT MODE
For the pulse width measurement mode, the counter only incresed by the rising edge of internal pulse rate as
external timer/counter input (P8.3/TRGA ), interrupt request will be generated as soon as timer/counter
overflow.
P8.3/TRGA
Internal pulse
TimerA value
n
n+1
n+2
n+3
n+4
n+5
PROGRAM EXAMPLE: Enable timerA by pulse width measurement mode .
LDIA #1100B;
OUTA P28; Enable timerA with pulse width measurement mode.
INTERRUPT FUNCTION
There are 4 interrupt sources, 2 external interrupt sources, 2 internal interrupt sources . Multiple
interrupts are admitted according the priority .
Type
External
Internal
Internal
Internal
Internal
External
Interrupt source
External interrupt(INT0)
Reserved
TimerA overflow interrupt (TRGA)
Reserved
Time base interrupt(TBI)
External interrupt(INT1)
Priority
Interrupt
Latch
Interrupt
Enable condition
Program ROM
entry address
1
2
3
4
5
6
IL5
IL4
IL3
IL2
IL1
IL0
EI=1
EI=1, MASK3=1
EI=1, MASK2=1
EI=1, MASK1=1
002h
004h
006h
008h
00Ah
00Ch
* This specification are subject to be changed without notice.
EI=1,MASK0=1
7.20.1999 15
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
INTERRUPT STRUCTURE
inary
m
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P
MASK0 MASK1 MASK1 MASK2 MASK3
Reset by system reset and program
instruction
INT1
r0
TBI
r1
IL0
IL1
TRGA
r3
r2
IL2
r4
IL3
IL4
INT0
r5
IL5
Priority checker
Reset by system reset and program
instruction
Set by program instruction
EI
Interrupt request
Entry address generator
Interrupt entry address
Interrupt controller:
IL0-IL5
: Interrupt latch . Hold all interrupt requests from all interrupt sources. ILr can not be
set by program, but can be reset by program or system reset, so IL only can decide
which interrupt source can be accepted.
MASK0-MASK3
: Except INT0 ,MASK register can promit or inhibit all interrupt sources.
EI
: Enable interrupt Flip-Flop can promit or inhibit all interrupt sources, when interrupt happened, EI is cleared to "0" automatically, after RTI instruction happened,
EI will be set to "1" again .
Priority checker: Check interrupt priority when multiple interrupts happened.
INTERRUPT FUNCTION
The procedure of interrupt operation:
1. Push PC and all flags to stack.
2. Set interrupt entry address into PC.
3. Set SF= 1.
4. Clear EI to inhibit other interrupts happened.
5. Clear the IL for which interrupt source has already be accepted.
6. To excute interrupt subroutine from the interrupt entry address.
7. CPU accept RTI, restore PC and flags from stack . Set EI to accept other interrupt requests.
PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA"
LDIA #1100B;
EXAE; set mask register "1100B"
EICIL 111111B ; enable interrupt F.F.
POWER SAVING FUNCTION ( Sleep / Hold functlon )
* This specification are subject to be changed without notice.
7.20.1999
16
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
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m
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During sleep and hold condition, CPU holds the system's internal status with a low power consumption, for
the sleep mode, the system clock will be stoped in the sleep condition and system need a warm up time for
the stability of system clock running after wakeup . In the other way, for the hold mode, the system clock
does not stop at all and it does not need a warm-up time any way.
The sleep and hold mode is controlled by Port 16 and released by P0(0..3)/WAKEUP0-3.
P16
3
2
1
0
WM SE SWWT
initial value :0000
WM Set wake-up release mode
0
1
SWWT Set wake-up warm-up time
0 0 218 /XIN
0 1 214 /XIN
1 0 216 /XIN
1 1 Hold mode
Wake-up in edge release mode
Reserved
SE Enable sleep/hold
0 Reserved
1 Enable sleep / hold rnode
Sleep and hold condition:
1. Osc stop ( sleep only ) and CPU internal status held .
2. Internal time base clear to"0"
3. CPU internal memory ,flags, register, I/O held original states.
4. Program counter hold the executed address after sleep release.
Release condition:
1. Osc start to oscillating.(sleep only)
2. Warm-up time passing ( sleep only ).
3. According PC to execute the following program.
There is one kind of sleep/hold release mode .
1.Edge release mode:
Release sleep/hold condition by the falling edge of any one of P0(0..3)/WAKEUP0-3.
Note : There is only one mask option for weakeup function in EM73201. So,the weakeup function of
P0(0..3)/WAKEUP0..3 are enabled or disabled together.
INFRARED SIGNAL
The infrared signal generator supports user different frequencies and duties clock signal by P1.0/CLKOUT
pin.
The basic structure of infrared signal generator is composed by a frequency divider and a duty controller,
these two parts generate differen frequencies and dutyies according to the command port, Port4 and Port5,
assigned . When the CPU is reseted, the CPU is reseted, the P1.0/CLKOUT pin will keep high.
PORT5
PORT4
E
3
2
1
0
A
B
3
2
C
1
D
0
initial state : 0 x x x initial state : 0 0 0 0
* This specification are subject to be changed without notice.
7.20.1999 17
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
m
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Infrared signal command port
PORT4
PORT5
Frequecy divider
fc
Duty controller
P1.0/CLKOUT
E
X
1
0
0
0
0
0
0
0
0
A
0
1
1
1
1
1
1
1
1
1
B
X
X
0
0
0
0
1
1
1
1
C
X
X
0
0
1
1
0
0
1
1
D
X
X
0
1
0
1
0
1
0
1
CLK OUT
HIGH
fc/12
fc/8
fc/16
fc/32
fc/64
LOW
fc/16 ; 1/4 duty
fc/16 ; 1/2 duty
fc/16 ; 3/4 duty
fc
fc/8
fc/16
fc/64
fc/16 , 1/4 duty
fc/16 , 1/2 duty
fc/16 , 3/4 duty
Program example:
To disable CLKOUT before sleep.
LDIA #0000B;
OUTA P5;
OUTA P4; set clkout pin in high state
LDIA #0100B;
OUTA P16; Sleep
:
To enable a CLKOUT signal with frequency
fc/16, 3/4 duty .
LDIA #0000B;
OUTA P5;
LDIA #1111B;
OUTA P4;
:
WATCH-DOG-TIMER
Watch-dog-timer (WDT) can help user to detect the malfunction (runaway) of CPU and give system a time
up signal every certain time. User can use the time up signal to give system a reset signal when system is fail.
The watch-dog-timer is enabled or disabed by mask option. If the mask option of WDT is enabled and the
CPU is reseted or waked up, the WDT will be cleared and counting. When the CPU is sleeping, the WDT
will be disabled.
The basic structure of watch-dog-timer control is composed by a 4-stage binary counter and a control unit.
The WDT counter counts for a certain time to check the CPU status, if there is no malfunction happened, the
counter will be cleared and counting. Otherwise, if there is a malfunction happened, the WDT control will
send a signal (low active) to reset CPU. The WDT checking period is assign by P21 (WDT command port).
* This specification are subject to be changed without notice.
7.20.1999
18
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
m
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P
WDT counter
17
fc/2
0
1
2
3
WDT control
counter clear request
system reset
F/F
RQ
S
RESET pin
P21
WDT
command port
P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to reset pin, user can
use this time up signal (active low) to reset CPU and initialize system.
P21
3
2
CWC *
1
0
initial value :0000
* WDT
CWC
0
1
Clear watch-dog-timer counter
Clear counter then return to 1
Nothing
WDT
Set watch-dog-timer System clock frequency
detect time
4MHz
32KHz
3 x 217 /fc
98ms
12sec
17
229ms
28sec
7 x 2 /fc
0
1
Program example:
To clear WDT with 7 x 217/fc detection time.
LDIA #0001B;
OUTA P21
:
; set WDT detection time and clear WDT counter
:
RESETTING FUNCTION
When CPU in normal working condition and RESET pin holds in low level for three instruction cycles
at least, then CPU begins to initialize the whole internal states, and when RESET pin changes to high
level, CPU begins to work in normal condition.
The CPU internal state during reset condition is as following table :
Hardware condition in RESET state
Program counter
Status flag
Interrupt enable flip-flop ( EI )
MASK0 ,1, 2, 3
Interrupt latch(IL)
P4, P5, P16, P25, P28
P1, P7, P8
XIN
* This specification are subject to be changed without notice.
Initial value
000h
01h
00h
00h
00h
00h
0Fh
Start oscillation
7.20.1999 19
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
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The RESET pin is a hysteresis input pin and has a pull-up resistor avavailable by mask option.
The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD.
RESET
EM73201 I/O PORT DESCRIPTION :
Port
0 E
1
2
3
4
5
6
7 E
8 E
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Input function
Input port , wakeup function
------Input port
Input port, external interrupt input
--------
Output function
E
I
I
E
E
I
I
I
I
Note
with LED driving, P1.0 is shared with CLKOUT
--Infrared signal control register
Infrared signal control register
-Output port
Output port
-------Sleep/Hold mode control register
----WDT control register
---Timebase control register
--Timer/counter A control register
----
* This specification are subject to be changed without notice.
7.20.1999
20
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
ABSOLUTE MAXIMUM RATINGS
Items
inary
m
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P
Sym.
Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
Ratings
VDD
VIN
VO
PD
TOPR
TSTG
Conditions
-0.5V to 6V
-0.5V to VDD+0.5V
-0.5V to VDD+0.5V
300mW
0oC to 50oC
-55oC to 125oC
TOPR=50oC
RECOMMANDED OPERATING CONDITIONS
Items
Sym.
Supply Voltage
Input Voltage
VDD
VIH
VIL
FC
Operating Frequency
Ratings
Condition
2.4V to 6.0V
0.90xVDD to VDD
0V to 0.10xVDD
32K to 4MHz
32K to 5MHz
CLK (RC osc)
XIN,XOUT (crystal osc)
DC ELECTRICAL CHARACTERISTICS (VDD=5±0.5V, VSS=0V, TOPR=25oC)
Parameters
Supply current
Sym.
Typ. Max.
-
0.7
60
2
110
Frequency stability
0.50VDD
0.20VDD
5
5
20
2.4
3.5
3.0
30
100
-
0.1
90
300
10
1
0.75VDD
0.40VDD
±1
±1
1
1.5
1
150
450
-
Frequency variation
-
20
-
Low voltage reset level
3.3
-
4.0
Hysteresis voltage
IDD
Min.
Input current
VHYS+
VHYSIIH
Output current
(Port 1)
IOH
IOL
Output voltage
(Port 7 Port8)
VOH
VOL
Leakage current
Input resistor
IOL
RIN
* This specification are subject to be changed without notice.
Unit
Conditions
mA VDD=5.5V,no load Fc=4.19MHz (crystal osc)
µA VDD=5.5V,no load
sleep mode, low voltage reset enable
µA VDD=5.5V, sleep mode, low voltage reset disable
V
RESET, P0, P8
V
µA RESET , P0, VDD=5.5V,VIH=5.5/0V
µA Open-drain:VDD=5.5V,VIH=5.5/0V
mA P1 normal source, VDD=4.5V ,VOH=3.5V
mA P1 normal sink, VDD=4.5V ,VOL=1.0V
mA P1 high sink, VDD=4.5V ,VOL=1.0V
V
P7,P8 low source,VDD=4.5V, IOH=-250µA
V
P7,P8 normal source,VDD=4.5V,IOH=-5mA
V
P7,P8 high source,VDD=4.5V,IOH=-20mA
V
P7,P8 normal sink,VDD=4.5V,IOL=5mA
V
P7,P8 high sink,VDD=4.5V,IOL=20mA
µA Open drain,VDD=5.5V,VO =5.5V
KΩ P0
KΩ RESET
%
Fc=4MHz, RC osc (R=7.5kΩ, C=20pF)
[Fc=(4.5V)-F(3.6V)]/F(4.5V)
%
Fc=4MHz, VOL=4.5V, RC osc
[F(typical)-F(worse case)]/F(typical)
V
7.20.1999 21
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4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
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P
RESET PIN TYPE
TYPE RESET-A
RESET
mask option
OSCILLATION PIN TYPE
TYPE OSC-A
TYPE OSC-C
XIN
Crystal
Osc.
RC Osc.
(comparator)
CLK
XOUT
INPUT PIN TYPE
TYPE INPUT-A
TYPE INPUT-C
WAKEUP function mask option
: mask option
OUTPUT PIN TYPE
TYPE OUTPUT
P0.0/WAKEUP0
TYPE INPUT-A
P0.1/WAKEUP1
TYPE INPUT-A
P0.2/WAKEUP2
TYPE INPUT-A
P0.3/WAKEUP3
TYPE INPUT-A
TYPE OUTPUT-C
Input
data
TYPE
OUTPUT
Output
data
latch
Output
data
maskoption
option
::mask
* This specification are subject to be changed without notice.
7.20.1999
22
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
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P
TYPE OUTPUT-B
Input
data
TYPE
OUTPUT
MUX
Output
data
latch
Output
data
Special function
control output
I/O PIN TYPE
TYPE I/O_T
TYPE I/O-U
path B
path A
Output
data
latch
TYPE I/O_T
Input
data
Output
data
: mask option
TYPE I/O-V
TYPE I/O-W
path B
path A
Input
data
path B
SEL
path A
TYPE I/O_T
Path A :
Path B :
Output
data
latch
Output
data
TYPE I/O_T
Output
data
latch
Special function
control input
Input data
Output
data
For set and clear bit of port instructions, data goes through path A from output data latch to CPU.
For input and test instructions, data from output pin go through path B to CPU and the output data latch
will be set to high.
* This specification are subject to be changed without notice.
7.20.1999 23
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
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P
APPLICATION CIRCUIT
VDD
P0.3
P0.2
P0.1
P0.0
P7.3
P7.2
P7.1
P7.0
P1.1
P1.2
P1.3
P8.0
P8.1
EM73201 P8.2
P8.3
RESET
INFRARED SIGNAL
P1.0
NC/XOUT
RC OSC
CLK/XIN
V
SS
CRYSTAL OSC
CRYSTAL OSC (32KHz)
(4MHz)
C
C
XOUT/NC
C
XIN/CLK
C=20pF
* This specification are subject to be changed without notice.
C
R
XOUT
XIN
Recommended values :
C = 100~150pF
R = 10KΩ
7.20.1999
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
m
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P
PAD DIAGRAM
P7.0
P8.3
P8.0
VDD
3
2
1
22
P8.2 RESET
21
P7.1
4
P7.2
5
P7.3
6
Y
P1.0
7
(0,0)
20
P8.1
19
18
XOUT
17
XIN
16
TEST
15
P0.3
14
P0.2
X
EM73201
P1.1
8
9
10
P1.2 P1.3
Chip Size : 1820 µm x 1510 µm
PadNo.
Symbol
1
P8.0
2
P8.3
3
P7.0
4
P7.1
5
P7.2
6
P7.3
7
P1.0
8
P1.1
9
P1.2
10
P1.3
11
VSS
12
P0.0
13
P0.1
14
P0.2
15
P0.3
16
TEST
17
XIN
18
XOUT
19
P8.1
20
RESET
21
P8.2
22
VDD
11
12
VSS P0.0
X
-301.5
-465.9
-661.2
-818.2
-818.2
-818.2
-818.2
-829.2
-706.2
-583.0
-457.4
-298.0
705.5
828.4
814.7
814.7
790.1
790.1
692.1
564.5
433.8
-123.2
13
P0.1
Y
661.2
661.2
661.2
603.1
405.1
240.7
59.8
-650.5
-650.5
-650.5
-636.4
-651.4
-651.4
-651.4
-454.3
-303.0
194.6
374.5
643.1
643.1
643.1
661.2
Unit : µm
Note : For PCB layout, IC substrate must be floated, or connect to VSS .
* This specification are subject to be changed without notice.
7.20.1999 25
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
m
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P
INSTRUCTION TABLE
(1) Data Transfer
Mnemonic
Object code ( binary )
Operation description
LDA
x
LDAM
LDAX
LDAXI
LDH
#k
LDHL x
LDIA #k
LDL
#k
STA
x
STAM
STAMD
STAMI
STD
#k,y
STDMI #k
THA
TLA
0110 1010 xxxx xxxx
0101 1010
0110 0101
0110 0111
1001 kkkk
0100 1110 xxxx xx00
1101 kkkk
1000 kkkk
0110 1001 xxxx xxxx
0101 1001
0111 1101
0111 1111
0100 1000 kkkk yyyy
1010 kkkk
0111 0110
0111 0100
Acc←RAM[x]
Acc ←RAM[HL]
Acc←ROM[DP]L
Acc←ROM[DP]H,DP+1
HR←k
LR←RAM[x],HR←RAM[x+1]
Acc←k
LR←k
RAM[x]←Acc
RAM[HL]←Acc
RAM[HL]←Acc, LR-1
RAM[HL]←Acc, LR+1
RAM[y]←k
RAM[HL]←k, LR+1
Acc←HR
Acc←LR
Object code ( binary )
Operation description
Byte
2
1
1
1
1
2
1
1
2
1
1
1
2
1
1
1
Cycle
2
1
2
2
1
2
1
1
2
1
1
1
2
1
1
1
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C
Flag
Z
Z
Z
S
C'
C'
C
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
S
C'
C'
C'
C'
C'
C'
C'
C
C
C
C'
S
1
1
1
1
1
1
1
1
1
1
C
C'
1
C'
1
1
(2) Rotate
Mnemonic
RLCA
RRCA
0101 0000
0101 0001
←CF←Acc←
→CF→Acc→
Byte
1
1
Cycle
1
1
(3) Arithmetic operation
Mnemonic
Object code ( binary )
Operation description
Byte
ADCAM
ADD
#k,y
ADDA #k
ADDAM
ADDH #k
ADDL #k
ADDM #k
DECA
DECL
DECM
INCA
0111
0100
0110
0111
0110
0110
0110
0101
0111
0101
0101
Acc←Acc + RAM[HL] + CF
RAM[y]←RAM[y] +k
Acc←Acc+k
Acc←Acc + RAM[HL]
HR←HR+k
LR←LR+k
RAM[HL]←RAM[HL] +k
Acc←Acc-1
LR←LR-1
RAM[HL]←RAM[HL] -1
Acc←Acc + 1
1
2
2
1
2
2
2
1
1
1
1
0000
1001 kkkk yyyy
1110 0101 kkkk
0001
1110 1001 kkkk
1110 0001 kkkk
1110 1101 kkkk
1100
1100
1101
1110
* This specification are subject to be changed without notice.
Cycle
1
2
2
1
2
2
2
1
1
1
1
7.20.1999
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
inary
m
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P
INCL
INCM
SUBA #k
SBCAM
SUBM #k
0111 1110
0101 1111
0110 1110 0111 kkkk
0111 0010
0110 1110 1111 kkkk
LR←LR + 1
RAM[HL]←RAM[HL]+1
Acc←k-Acc
Acc←RAM[HLl - Acc - CF'
RAM[HL]←k - RAM[HL]
1
1
2
1
2
1
1
2
1
2
C
-
Z
Z
Z
Z
Z
C'
C'
C
C
C
(4) Logical operation
Object code ( binary )
Operation description
Byte
ANDA #k
ANDAM
ANDM #k
ORA
#k
ORAM
ORM #k
XORAM
0110
0111
0110
0110
0111
0110
0111
Acc←Acc&k
Acc←Acc & RAM[HL]
RAM[HL]←RAM[HL]&k
Acc←Acc k
Acc ←Acc RAM[HL]
RAM[HL]←RAM[HL] k
Acc←Acc^RAM[HL]
2
1
2
2
1
2
1
--
1110 0110 kkkk
1011
1110 1110 kkkk
1110 0100 kkkk
1000
1110 1100 kkkk
1001
----
Mnemonic
Cycle
2
1
2
2
1
2
1
Flag
C
Z
Z
Z
Z
Z
Z
Z
Z
S
Z'
Z'
Z'
Z'
Z'
Z'
Z'
Flag
Z
S
(5) Exchange
Mnemonic
Object code ( binary )
Operation description
Byte
Cycle
EXA x
EXAH
EXAL
EXAM
EXHL x
0110 1000 xxxx xxxx
0110 0110
0110 0100
0101 1000
0100 1100 xxxx xx00
Acc↔RAM[x]
Acc↔HR
Acc↔LR
Acc↔RAM[HL]
LR↔RAM[x],
HR↔RAM[x+1]
2
1
1
1
2
2
2
1
2
2
Mnemonic
Object code ( binary )
Operation description
Byte
SBR a
00aa aaaa
1
1
LBR a
1100 aaaa aaaa aaaa
If SF=1 then PC←PC11-6.a5-0
else null
If SF= 1 then PC←a else null
2
2
Operation description
Byte
k-RAM[y]
RAM[x]-Acc
RAM[HL] - Acc
k - HR
k - Acc
k-LR
2
2
1
2
1
2
C
-
Z
Z
Z
Z
1
1
1
1
-
-
1
C
Flag
Z
S
-
-
1
Flag
C
Z
S
(6) Branch
Cycle
-
-
1
(7) Compare
Mnemonic
CMP #k,y
CMPA x
CMPAM
CMPH #k
CMPIA #k
CMPL #k
Object code ( binary )
0100 1011 kkkk yyyy
0110 1011 xxxx xxxx
0111 0011
0110 1110 1011 kkkk
1011 kkkk
0110 1110 0011 kkkk
* This specification are subject to be changed without notice.
Cycle
2
2
1
2
1
2
C
C
C
C
-
Z
Z
Z
Z
Z
Z
Z'
Z'
Z'
C
Z'
C
7.20.1999 27
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
(8) Bit manipulation
inary
m
i
l
e
r
P
Mnemonic
Object code ( binary )
Operation description
Byte
CLM
CLP
CLPL
CLR
SEM
SEP
SEPL
SET
TF
TFA
TFM
TFP
TFPL
TT
TTP
1111 00bb
0110 1101 11bb pppp
0110 0000
0110 1100 11bb yyyy
1111 01bb
0110 1101 01bb pppp
0110 0010
0110 1100 01bb yyyy
0110 1100 00bb yyyy
1111 10bb
1111 11bb
0110 1101 00bb pppp
0110 0001
0110 1100 10bb yyyy
0110 1101 10bb pppp
RAM[HL]b←0
PORT[p]b←0
PORT[LR3-2+4]LR1-0←0
RAM[y]b←0
RAM[HL]b←1
PORT[p]b←1
PORT[LR3-2+4]LRl-0←1
RAM[y]b←1
SF←RAM[y]b'
SF←Accb'
SF←RAM[HL]b'
SF←PORT[p]b'
SF←PORT[LR3-2+4]LR1-0'
SF←RAM[y]b
SF←PORT[p]b
1
2
1
2
1
2
1
2
2
1
1
2
1
2
2
Mnemonic
Object code ( binary )
Operation description
Byte
LCALL a
0100 0aaa aaaa aaaa
2
SCALL a
1110 nnnn
STACK[SP]←PC,
SP←SP -1, PC←a
STACK[SP]←PC,
SP←SP - 1, PC←a,
RET
0100 1111
b
p,b
y,b
b
p,b
y,b
y,b
b
b
p,b
y,b
p,b
Cycle
Flag
Z
-
S
1
1
1
1
1
1
1
1
*
*
*
*
*
*
*
2
Flag
C
Z
-
S
-
1
2
-
-
-
SP←SP + 1, PC←STACK[SP]
1
2
-
-
-
1
2
2
2
1
2
2
2
2
1
1
2
2
2
2
C
-
(9) Subroutine
a = 8n +6 (n=1~15),0086h (n =0)
Cycle
(10) Input/output
Mnemonic
Object code ( binary )
Operation description
Byte
INA
INM
OUT
OUTA
OUTM
0110 1111 0100 pppp
0110 1111 1100 pppp
0100 1010 kkkk pppp
0110 1111 000p pppp
0110 1111 100p pppp
Acc←PORT[p]
RAM[HL]←PORT[p]
PORT[p]←k
PORT[p]←Acc
PORT[p]←RAM[HL]
2
2
2
2
2
p
p
#k,p
p
p
Cycle
2
2
2
2
2
C
-
Flag
Z
Z
-
S
Z'
Z'
1
1
1
C
0
Flag
Z
-
S
1
1
*
(11) Flag manipulation
Mnemonic
Object code ( binary )
Operation description
Byte
CGF
SGF
TFCFC
0101 0111
0101 0101
0101 0011
GF←0
GF←1
SF←CF', CF←0
1
1
1
* This specification are subject to be changed without notice.
Cycle
1
1
1
7.20.1999
28
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
TGS
TTCFS
TZS
0101 0100
0101 0010
0101 1011
inary
m
i
l
e
r
P
SF←GF
SF←CF, CF←1
SF←ZF
1
1
1
1
1
1
1
-
-
*
*
*
(12) Interrupt control
Mnemonic
Object code ( binary )
Operation description
Byte
CIL
r
DICIL r
EICIL r
EXAE
RTI
0110 0011 11rr rrrr
0110 0011 10rr rrrr
0110 0011 01rr rrrr
0111 0101
0100 1101
IL←IL & r
EIF←0,IL←IL&r
EIF←1,IL←IL&r
MASK↔Acc
SP←SP+1,FLAG.PC
←STACK[SP],EIF ←1
2
2
2
1
1
Mnemonic
Object code ( binary )
Operation description
Byte
NOP
0101 0110
no operation
1
Cycle
2
2
2
1
2
C
*
Flag
Z
*
S
1
1
1
1
*
C
-
Flag
Z
-
S
-
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(13) CPU control
Cycle
1
(14) Timer/Counter & Data pointer & Stack pointer control
Mnemonic
Object code ( binary )
Operation description
Byte
LDADPL
LDADPM
LDADPH
LDASP
LDATAL
LDATAM
LDATAH
LDATBL
LDATBM
LDATBH
STADPL
STADPM
STADPH
STASP
STATAL
STATAM
STATAH
STATBL
STATBM
STATBH
0110 1010 1111 1100
0110 1010 1111 1101
0110 1010 1111 1110
0110 1010 1111 1111
0110 1010 1111 0100
0110 1010 1111 0101
0110 1010 1111 0110
0110 1010 1111 1000
0110 1010 1111 1001
0110 1010 1111 1010
0110 1001 1111 1100
0110 1001 1111 1101
0110 1001 1111 1110
0110 1001 1111 1111
0110 1001 1111 0100
0110 1001 1111 0101
0110 1001 1111 0110
0110 1001 1111 1000
0110 1001 1111 1001
0110 1001 1111 1010
Acc←[DP]L
Acc←[DP]M
Acc←[DP]H
Acc←SP
Acc←[TA]L
Acc←[TA]M
Acc←[TA]H
Acc←[TB]L
Acc←[TB]M
Acc←[TB]H
[DP]L←Acc
[DP]M←Acc
[DP]H←Acc
SP←Acc
[TA]L←Acc
[TA]M←Acc
[TA]H←Acc
[ TB]L←Acc
[TB]M←Acc
[TB]H←Acc
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
* This specification are subject to be changed without notice.
Cycle
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
7.20.1999 29
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
**** SYMBOL DESCRIPTION
Symbol
inary
m
i
l
e
r
P
Description
Symbol
HR
PC
SP
ACC
CF
SF
EI
MASK
ΤΑ
RAM[HL]
ROM[DP]L
[DP]L
[DP]H
H register
Program counter
Stack pointer
Accumulator
Carry flag
Status flag
Enable interrupt register
Interrupt mask
Timer/counter A
Data memory (address : HL )
Low 4-bit of program memory
Low 4-bit of data pointer register
High 4-bit of data pointer register
LR
DP
STACK[SP]
FLAG
ZF
GF
IL
PORT[p]
ΤΒ
RAM[x]
ROM[DP]H
[DP]M
[TA]L([TB]L)
[TA]M([TB]M)
Middle 4-bit of timer/counter A
(timer/counter B) register
Transfer
Addition
Logic AND
Logic XOR
Concatenation
8-bit RAM address
4-bit or 5-bit port address
6-bit interrupt latch
Contents of bit assigned by bit
1 to 0 of LR
Bit 3 to 2 of LR
[TA]H([TB]H)
LR 1-0
LR3-2
↔
'
#k
y
b
PC11-6
a5-0
--
←
+
&
^
.
x
p
r
* This specification are subject to be changed without notice.
Description
L register
Data pointer
Stack specified by SP
All flags
Zero flag
General flag
Interrupt latch
Port ( address : p )
Timer/counter B
Data memory (address : x )
High 4-bit of program memory
Middle 4-bit of data pointer register
Low 4-bit of timer/counter A
(timer/counter B) register
High 4-bit of timer/counter A
(timer/counter B) register
Exchange
Substraction
Logic OR
Inverse operation
4-bit immediate data
4-bit zero-page address
Bit address
Bit 11 to 6 of program counter
Bit 5 to 0 of destination address for
branch instruction
7.20.1999
30