EMC EM73362

EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
GENERAL DESCRIPTION
EM73362 is an advanced single chip CMOS 4-bit micro-controller. It contains 3K-byte ROM, 52-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, one 12-bit timer for the kernal function and one high
speed counter. EM73362 also contains 5 interrupt sources, 1 input port, 4 bidirection ports, built-in watchdog-timer and LCD driver (27x3 to 15x3).
Except low-power consumption and high speed, EM73362 has the STOP mode and IDLE mode operation for
power saving function.
FEATURES
• Operation voltage
• Clock source
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
: 1.2V to 1.8V.(clock frequency : 32 K Hz)
: Single clock system for crystal, connect a external resistor or external clock
source, available by mask option.
Instruction set
: 109 powerful instructions.
Instruction cycle time
: Up to 122µs for 32 K Hz.
ROM capacity
: 3072 x 8 bits.
RAM capacity
: 52 x 4 bits.
Input port
: 1 port (4-bit).
Bidirection port
: 4 ports (P4, P6, P7, P8) are available by mask option. P4 is a high current port.
(P4.0 and TONE available by mask option. P4.1~P4.3 are shared with the input/
output of RFO.) P6, P7 and P8 are shared with SEG15-SEG26.
12-bit timer
: One 12-bit timer is programmable for timer.
High speed counter
: The high speed counter includes one 8-bit high speed counter, one 12-bit general
counter and a resistor frequency oscillator. It has resistor to frequency oscillation
mode, melody mode and auto load timer mode.
Built-in time base counter: 22 stages.
Subrountine nesting
: Up to 13 levels.
Interrupt
: External interrupt . . . . . . 2 input interrupt sources.
Internal interrupt . . . . . . 2 timer overflow interrupts,
1 time base interrupt.
LCD driver
: 27x3 to 15x3 dots available by mask option. 1/3, 1/2 and static three kinds of duty
(1/2 bias) selectable. The programming method of LCD driver is RAM mapping.
Built-in watch-dog-timer is available by mask option.
Built-in low battery detector.
Power saving function : STOP mode and IDLE mode.
Package type
: Chip form 49 pins.
* This specification are subject to be changed without notice.
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FUNCTION BLOCK DIAGRAM
XIN XOUT
RESET
Reset
Control
Clock
WDT Generator
Frequency
doubler
Timing
Generator
P0.0(INT1)/WAKEUP0
P0.1/WAKEUP1
P0.2(INT0)/WAKEUP2
P0.3/WAKEUP3
Sleep Mode
Control
System Control
Data pointer
Instruction Decoder
Instruction Register
ROM
12-bit
timer
(TA)
P6,P7,P8/SEG(26..15)
ALU
Stack
Flag
RAM
Z C S G
HR
PC
LCD
driver
ACC
Data Bus
Interrupt
Control
Time
Base
Stack pointer
VA
VB
VEE
COM0~COM2
SEG0~SEG14
Low battery detector
BAT
Tone generator
TONE
LR
P4.0(RX)/TONE
P4.1(CS)
P4.2(RY)
P4.3(RZ)
I/O Control
High speed counter
* This specification are subject to be changed without notice.
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PIN DESCRIPTIONS
Pin name
VDD
VSS
RESET
XIN
XOUT
P0.0(INT1)/WAKEUP0,
P0.2(INT0)/WAKEUP2
P0(1,3)/WAKEUP1,3
P4.0(RX)/TONE
P4.1(CS)
P4.2(RY), P4.3(RZ)
P6(0..3)/SEG(23..26),
P7(0..3)/SEG(19..22),
P8(0..3)/SEG(15..18)
BAT
TONE
VA, VB, VEE
COM0 ~ COM2
SEG0 ~ SEG14
TEST
Function
PIN type
Power supply (+)
Power supply (-)
System reset input signal, low active
RESET_A
mask option : none
pull-up
Crystal / external resistor or external clock source
OSC_A / OSC_F
connecting pin
Crystal / external resistor connecting pin
OSC_A / OSC_F
2-bit input pins with external interrupt sources input
INPUT_J
and STOP/IDLE releasing function
mask option : wake-up enable, pull-up
wakeup enable, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
2-bit input pins with STOP / IDLE releasing function
INPUT_H
mask option : wakeup enable, pull-up
wakeup enable, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
1-bit bidirection I/O pin or inverse sound effect output or
I/O_O
RF oscillation
mask option : TONE enable, push-pull, high current PMOS
TONE disable, open-drain(apply to RF oscillation)
TONE disable, push-pull, high current PMOS
TONE disable, push-pull, low current PMOS
1-bit bidirection I/O pin or RF oscillation bias pin
I/O_X
mask option : open-drain(apply to RF oscillation)
push-pull, high current PMOS
push-pull, low current PMOS
2-bit bidirection I/O pins or RF oscillation input pins
I/O_Y
mask option : open-drain(apply to RF oscillation)
push-pull, high current PMOS
push-pull, low current PMOS
12-bit bidirection I/O pins are shared with LCD segment pin
I/O_O
mask option : segment enable, open-drain
segment disable, open-drain
segment disable, push-pull, high current PMOS
segment disable, push-pull, low current PMOS
Connect the capacitor for built-in low battery detector
Built-in tone generator output
Connect the capacitors for LCD bias voltage
LCD common output pins
LCD segment output pins
Tie Vss as package type, no connecting as COB type.
* This specification are subject to be changed without notice.
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FUNCTION DESCRIPTIONS
PROGRAM ROM ( 3K X 8 bits )
3 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of program ROM can be divided into 4 parts.
1. Address 000h: Reset start address.
2. Address 002h - 00Ch : 5 kinds of interrupt service routine entry addresses.
3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh,
036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h, 07Eh, 086h.
4. Address 000h - 7FFh : LCALL subroutine entry address.
5. Address 000h - BFFh : Except used as above function, the other region can be used as user's program region.
address
000h
002h
004h
006h
008h
00Ah
00Ch
00Eh
086h
3072 x 8 bits
Reset start address
INT0; External interrupt service toutine entry address
TRGA; Timer/counter A interrupt service routine entry address
TRGB; Timer/counter B interrupt service routine entry address
TBI; Time base interrupt service routine entry address
INT1; External interrupt service routine entry address
SCALL, subroutine call entry address
..
.
BFFh
User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code. Fixed data can be read out by table-look-up instruction.
Table-look-up instruction is depended on the Data Pointer (DP) to indicate to ROM address, then to get the
ROM code data.
LDAX
LDAXI
Acc ← ROM[DP]L
Acc ← ROM[DP]H,DP+1
DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code data.
First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can get the
lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI".
* This specification are subject to be changed without notice.
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PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction.
LDIA #07h;
STADPL
STADPM
STADPH
:
LDL #00h;
LDH #03h;
LDAX
STAMI
LDAXI
STAM
;
ORG 777h
DATA 56h;
:
; [DP]L ← 07h
; [DP]M ← 07h
; [DP]H ← 07h, Load DP=777h
; ACC ← 6h
; RAM[30] ← 6h
; ACC ← 5h
; RAM[31] ← 5h
DATA RAM ( 52-nibble )
There is total 52 - nibble data RAM from address 00 to 33h
Data RAM includes 3 parts: zero page region, stacks and data area.
Increment
Address
Level 0
Level 1
Level 2
Level 3
10h - 1Fh
Level 4
Level 5
Level 6
Level 7
20h - 2Fh
Level 8
Level 9
Level 10
Level 11
30h - 33h
Level 12
Stack
Increment
00h - 0Fh
Zero-page
ZERO- PAGE:
From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero-page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE: To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.
STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]2 ← 0
STACK:
There are 13-level (maximum) stack for user using for subroutine (including interrupt and CALL). User can
assign any level be the starting stack by giving the level number to stack pointer (SP).
When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address
will be saved into stack until return from those subroutines, the PC value will be restored by the data saved
in stack.
DATA AREA:
Except the special area used by user, the whole RAM can be used as data area for storing and loading general
data.
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ADDRESSING MODE
(1) Indirect addressing mode:
Indirect addressing mode indicates the RAM address by specified HL register.
For example: LDAM ; Acc ← RAM[HL]
STAM ; RAM[HL] ← Acc
(2) Direct addressing mode:
Direct addressing mode indicates the RAM address by immediate data.
For example: LDA x ; Acc← RAM[x]
STA x ; RAM[x] ← Acc
(3) Zero-page addressing mode
For zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit
manupulated operation directly.
For example: STD #k,y ; RAM[y] ← #k
ADD #k,y; RAM[y] ← RAM[y] + #k
LCD DISPLA
Y RAM
DISPLAY
RAM address from 40h ~ 46h, 50h ~ 56h, 60h ~ 66h are LCD display RAM, the RAM data of this region can't
be operated by instruction “LDHL xx” and “EXHL”.
bit
Address Increment
0 1 2 30 1 2
Increment
40h~46h (COM0)
50h~56h (COM1)
60h~66h (COM2)
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
PROGRAM COUNTER (3K ROM)
Program counter ( PC ) is composed by a 12-bit counter, which indicates the next executed address for the
instruction of program ROM.
For a 3K - byte size ROM, PC can indicate address form 000h - BFFh, for BRANCH and CALL instructions,
PC is changed by instruction indicating.
(1) Branch instruction:
SBR a
Object code: 00aa aaaa
Condition: SF=1; PC ← PC 11-6.a ( branch condition satisified )
PC Hold original PC value+1 a a
a
a
a
a
SF=0; PC← PC +1( branch condition not satisified)
PC
Original PC value + 1
LBR a
Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC ← a ( branch condition satisified)
PC a
a
a
a
a
a
a
a
a
a
a
* This specification are subject to be changed without notice.
a
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SF=0 ; PC ← PC + 2 (branch condition not satisfied)
PC
Original PC value + 2
(2) Subroutine instruction:
SCALL a
Object code: 1110 nnnn
Condition : PC ← a ; a=8n+6 ; n=1..15 ; a=86h, n=0
PC
0
0
0
0
a
a
a
a
a
a
a
a
LCALL a
Object code: 0100 0aaa aaaa aaaa
Condition: PC ← a
PC 0
a
a
a
a
a
a
a
a
a
a
a
RET
Object code: 0100 1111
Condition: PC ← STACK[SP]; SP + 1
PC
The return address stored in stack
RT I
Object code: 0100 1101
Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1
PC
The return address stored in stack
(3) Interrupt acceptance operation:
When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC. The interrupt vectors are as following:
INT0 (External interrupt from P0.2)
PC 0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
TRGA (Timer A overflow interrupt)
PC 0
0
0
0
0
TRGB (Time B overflow interrupt)
PC 0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
TBI (Time base interrupt)
PC 0
0
0
* This specification are subject to be changed without notice.
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INT1 (External interrupt from P0.0)
PC 0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
(4) Reset operation:
PC 0
(5) Other operations:
For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
ACCUMULATOR
Accumulator is a 4-bit data register for temporary data. For the arithematic, logic and comparative opertion
.., ACC plays a role which holds the source data and result.
FLAGS
There are four kinds of flag, CF (Carry flag), ZF (Zero flag), SF (Status flag) and GF (General flag),
these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation.
All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction executed.
(1) Carry Flag ( CF )
The carry flag is affected by following operation :
a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1",
in another word, if the operation has no carry-out, CF will be "0".
b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF
will be "0", in another word, if no borrow-in, CF will be "1".
c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction
operation.
d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after
rotation.
e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0".
For TTSFC instruction, the content of CF sends into SF then set itself "1".
(2) Zero Flag ( ZF )
ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1",
otherwise, the ZF will be "0".
(3) Status Flag ( SF )
The SF is affected by instruction operation and system status.
* This specification are subject to be changed without notice.
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a. SF is initiated to "1" for reset condition.
b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise,
branch condition will not be satisified by SF = 0.
(4) General Flag ( GF )
GF is a one bit general purpose register which can be set, clear, test by instruction SGF, CGF and TGS.
PROGRAM EXAMPLE :
Check following arithematic operation for CF, ZF, SF
CF
-
LDIA #00h;
LDIA #03h;
ADDA #05h;
ADDA #0Dh;
ADDA #0Eh;
ZF
1
0
0
0
0
SF
1
1
1
0
0
ALU
The arithematic operation of 4 - bit data is performed in ALU unit. There are 2 flags can be affected by
the result of ALU operation, ZF and SF. The operation of ALU can be affected by CF only.
ALU STRUCTURE
ALU supported user arithematic operation function, including : addition, subtraction and rotaion.
DATA BUS
ALU
ZF CF SF GF
ALU FUNCTION
(1) Addition:
For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function.
The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1",
otherwise, not equal "0", ZF will be "0". When the addition operation has a carry-out, CF will be "1",
otherwise, CF will be "0".
EXAMPLE:
Operation
3+4=7
7+F=6
0+0=0
8+8=0
Carry
0
1
0
1
Zero
0
0
1
1
(2) Subtraction:
For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function. The
subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will
* This specification are subject to be changed without notice.
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be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result
of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "1".
EXAMPLE:
Operation
8-4=4
7-F= -8(1000)
9-9=0
Carry
1
0
1
Zero
0
0
1
(3) Rotation:
There are two kinds of rotation operation, one is rotation left, the other is rotation right.
RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data
will be hold in CF.
MSB LSB
ACC
CF
RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and
the shift out data will be hold in CF.
MSB LSB
ACC
CF
PROGRAM EXAMPLE: To rotate Acc right and shift a "1" into the MSB bit of Acc.
TTCFS; CF ← 1
RRCA; rotate Acc right and shift CF=1 into MSB.
HL REGISTER
HL register are two 4-bit registers, they are used as a pair of pointer for the address of RAM memory and also
2 independent temporary 4-bit data registers. For some instruction, L register can be a pointer to indicate the
pin number (Port4, Port6, Port7).
HL REGISTER STRUCTURE
3
2
1
0
3
2
1
0
H REGISTER L REGISTER
HL REGISTER FUNCTION
(1) For instruction : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH, HL register used as a
temporary register.
PROGRAM EXAMPLE: Load immediate data "5h" into L register, "Dh" into H register.
LDL #05h;
LDH #0Dh;
(2) For instruction LDAM, STAM, STAMI .., HL register used as a pointer for the address of RAM memory.
* This specification are subject to be changed without notice.
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PROGRAM EXAMPLE: Store immediate data #Ah into RAM of address 35h.
LDL #5h;
LDH #3h;
STDMI #0Ah; RAM[35] ← Ah
(3) For instruction : SELP, CLPL, TFPL, L register be a pointer to indicate the bit of I/O port.
When LR = 0 - 1, indicate P4.0 - P4.1.
PROGRAM EXAMPLE: To set bit 1 of Port 4 to "1"
LDL #01h;
SEPL ; P4.1 ← 1
STACK POINTER (SP)
Stack pointer is a 4-bit register which stores the present stack level number.
Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition.
When a new subroutine is accepted, the SP will be decreased one automatically, in another word, if
returning from a subroutine, the SP will be increased one.
The data transfer between ACC and SP is by instruction of "LDASP" and "STASP".
DATA POINTER (DP)
Data pointer is a 12-bit register which stores the address of ROM can indicate the ROM code data
specified by user (refer to data ROM).
CLOCK AND TIMING GENERATOR
The clock generator is supported by a single clock system, the clock source comes from crystal (resonator)
or RC oscillation, the working frequency range is 32 KHz to 100 KHz depending on the working voltage.
CLOCK AND TIMING GENERATOR STRUCTURE
The clock generator connects outside compoments (crystal or resonator by XIN and XOUT pin for crystal
osc type, capacitor for RC osc type, these two type is decided by mask option) the clock generator
generates a basic system clock "fc".
When CPU sleeping, the clock generator will be stopped until the sleep condition released.
The system clock control generates 4 basic phase signals (S1, S2, S3, S4) and system clock.
Mask option
sleep
Mask option for choose Crystal or RC oscillation
XIN
clock generator
fc
System clock
System clock control
XOUT
S1
* This specification are subject to be changed without notice.
S2
S3
S4
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XIN
XIN
XOUT
XOUT
Crystal connection
Resistor connection
CLOCK AND TIMING GENERATOR FUNCTION
The frequency of fc is the oscillation frequency for XIN, XOUT by crystal (resonator) or by RC osc.
When CPU sleeps, the XOUT pin will be in "high" state.
The instruction cycle equal 4 basic clock fc.
1 instructure cycle = 4 / fc
OPERATION MODE CONTROL
EM73362 has 3 operation modes. They are Normal, Idle, and Stop mode.
Reset
se
lea
Input pin or
Internal timer wakeup
Command
(P19)
IDLE
mode
NORMAL
operating
mode
Com
re
set
Re
ma
Inp
t
ese
ut t
R
RESET
operation
Operation Mode
Normal
Idle
Stop
Reset
Oscillator
Oscillating
Oscillating
Stop
CPU
Run
Run
Stop
* This specification are subject to be changed without notice.
nd
(P1
6)
ime
rw
ake
up
STOP
mode
Available Function
LCD, RFC, Low battery detector
LCD
All disable
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ST
OP OPERA
TION MODE
STOP
OPERATION
During STOP operation mode, CPU holds the system’s internal status with a low power consumption, for
the STOP mode, the system clock will be stopped in the STOP condition and system need a warm up time
for the stability of system clock running after wakeup.
The STOP operation mode is controlled by Port 16 and released by P0(0..3)/ WAKEUP 0.. 3 .
P16
3
2
1
0
Initial value : 0000
SPME
SPME
0 1
* *
SWWT
Enable STOP mode
Enable STOP mode
Reserved
SWWT
0 0
0 1
1 0
1 1
Set wake-up warm-up time
29 / XIN
214 / XIN
216 / XIN
Reserved
STOP operation mode condition :
1. Osc stop and CPU internal status held.
2. Internal time base clear to "0".
3. CPU internal memory, flags, register, I/O held original states.
4. Program counter hold the executed address after STOP release.
Release condition :
1. Release STOP operation mode by the falling edge of any one of P0(0..3)/ WAKEUP 0.. 3 .
2. Osc start to oscillating.
3. Warm-up time passing.
4. According PC to execute the following program.
Note : There are 4 independent mask options for wakeup function in EM73362. So, the wakeup function of
P0(0..3)/ WAKEUP 0.. 3 are enabled or disabled independently.
IDLE OPERA
TION MODE
OPERATION
The IDLE operation mode retains the internal status with low power consumption without stopping the
system clock function and LCD display.
The IDLE operation mode is controlled by Port 19 and released by P0(0..3)/ WAKEUP 0..3 or the internal
timing generator.
P19
3
2
1
0
Initial value : 0000
IDME
SIDR
IDME
0 1
* *
Enable IDLE mode
Enable IDLE mode
Reserved
SIDR
0 0
0 1
1 0
1 1
* This specification are subject to be changed without notice.
Select IDLE releasing condition
P0(0..3) pin input
P0(0..3) pin input and 1 sec signal
P0(0..3) pin input and 0.5 sec signal
P0(0..3) pin input and 15.625m sec signal
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TIMING GENERATOR AND TIME BASE
The timing generator produces the system clock from basic clock pulse which can be normal mode or slow
mode clock.
1 instruction cycle = 4 basic clock pulses
There are 22 stages time base.
Binary counter
Prescaler
fc
0 1 2 3
4
5 6 7
8 9 10 11 12 13 14 15 16 17 18 19 20 21
When working in the single clock mode, the timebase clock source is come from fc.
Time base provides basic frequency for following function:
1. TBI (time base interrupt).
2. Timer/counter, internal clock source.
3. Warm-up time for STOP - mode releasing.
TIME BASE INTERRUPT (TBI)
The time base can be used to generate a fixed frequency interrupt. There are 8 kinds of frequencies can be
selected by setting "P25"
Single clock mode
P25 3 2 1 0
( initial value 0000 )
0 0 x x: Interrupt disable
0 1 0 0: Interrupt frequency XIN / 29 Hz
0 1 0 1: Interrupt frequency XIN / 210 Hz
0 1 1 0: Interrupt frequency XIN / 212 Hz
0 1 1 1: Interrupt frequency XIN / 213 Hz
1 1 0 0: Interrupt frequency XIN / 214 Hz
1 1 0 1: Interrupt frequency XIN / 215 Hz
1 1 1 0: Interrupt frequency XIN / 216 Hz
1 1 1 1: Interrupt frequency XIN / 217 Hz
1 0 x x: Reserved
* This specification are subject to be changed without notice.
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TIMER ( TIMERA, TIMERB)
EM73362 only can support timer function for timerA.
For timerA, the timer data is saved in timer register TAH, TAM, TAL, which user can set timer initial
value and read the timer value by instruction "LDATAH(M,L), STATAH(M,L)".
This counter can be set initial value and send counter value to timer register, P28 is the command port for
timerA, user can choose different internal clock rate by setting this port. When timer overflows, it will
generate a TRGA interrupt request to interrupt control unit.
INTERRUPT CONTROL
DATA BUS
12 BIT COUNTER
internal clock
TIMER CONTROL
P28
TMSA
IPSA
TIMER CONTROL
Timer command port: P28 is the command port for timerA.
Port 28
3 2 1 0
TMSA IPSA
Initial state: 0000
TMSA
Mode Selection
00
Stop
01
Reserved
10
Timer mode
11
Reserved
IPSA
00
Clock rate Selection
XIN/2 5 Hz
01
XIN/2 Hz
10
XIN/2 Hz
11
XIN/215 Hz
7
11
* This specification are subject to be changed without notice.
10.8.2001
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TIMER FUNCTION
For timer mode, timerA increase one at any rising edge of internal pulse. User can choose 4 kinds of internal
pulse rate by setting IPSA for timerA.
When timerA counts overflow, TRGA will be generated to interrupt control unit.
Internal pulse
TimerA value
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock XlN=32K Hz
LDIA
#0100B;
EXAE; enable mask 2
EICIL 110111B; interrupt latch ←0, enable EI
LDIA
#04H;
STATAL;
LDIA
#0CH;
STATAM;
LDIA
#0FH;
STATAH;
LDIA
#1000B;
OUTA P28; enable timerA with internal pulse rate: XIN/25 Hz
NOTE:
The preset value of timer/counter register is calculated as following procedure.
Internal pulse rate: XIN/25 ; XIN = 32KHz
The time of timer counter count one = 25 /XIN = 32/32K=1ms
The number of internal pulse to get timer overflow = 60 ms/ 1ms = 60 = 03CH
The preset value of timer/counter register = 1000H - 03CH = 0FC4H
INTERRUPT FUNCTION
There are 3 internal interrupt sources and 2 external interrupt sources. Multiple interrupts are admitted
according the priority.
Type
External
Internal
Internal
Internal
Internal
External
Interrupt source
External interrupt (INT0)
Reserved
TimerA overflow interrupt (TRGA)
TimerB overflow interrupt (TRGB)
Time base interrupt(TBI)
External interrupt (INT1)
Priority
Interrupt
Latch
Interrupt
Enable condition
Program ROM
entry address
1
2
3
4
5
6
IL5
IL4
IL3
IL2
IL1
IL0
EI=1
EI=1,MASK3=1
EI=1,MASK2=1
EI=1,MASK1=1
002H
004H
006H
008H
00AH
00CH
* This specification are subject to be changed without notice.
EI=1,MASK0=1
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INTERRUPT STRUCTURE
MASK0 MASK1 MASK1 MASK2 MASK3
INT1
r0
Reset by system reset and program
instruction
IL0
TBI
r1
TRGB
r2
IL1
IL2
TRGA Reserved
r3
r4
IL3
IL4
INT0
r5
IL5
Priority checker
Reset by system reset and program
instruction
Set by program instruction
EI
Interrupt request
Entry address generator
Interrupt entry address
Interrupt controller:
IL0-IL5
: Interrupt latch. Hold all interrupt requests from all interrupt sources. ILr can not be
set by program, but can be reset by program or system reset, so IL only can decide
which interrupt source can be accepted.
MASK0-MASK3
: MASK register can promit or inhibit all interrupt sources.
EI
: Enable interrupt Flip-Flop can promit or inhibit all interrupt sources, when interrupt happened, EI is cleared to "0" automatically, after RTI instruction happened,
EI will be set to "1" again.
Priority checker: Check interrupt priority when multiple interrupts happened.
INTERRUPT FUNCTION
The procedure of interrupt operation:
1. Push PC and all flags to stack.
2. Set interrupt entry address into PC.
3. Set SF= 1.
4. Clear EI to inhibit other interrupts happened.
5. Clear the IL for which interrupt source has already be accepted.
6. To execute interrupt subroutine from the interrupt entry address.
7. CPU accept RTI, restore PC and flags from stack. Set EI to accept other interrupt requests.
PROGRAM EXAMPLE: To enable interrupt of "TRGA"
LDIA #1100B;
EXAE; set mask register "1100B"
EICIL 111111B ; enable interrupt F.F.
* This specification are subject to be changed without notice.
10.8.2001
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
LCD DRIVER
EM73362 can directly drive the liquid crystal display (LCD) and has 27 segment, 3 common output pins.
There are total 27 x 3 dots can be display. The VDD, VEE, VA, VB and VSS pins are the bias voltage
inputs of the LCD driver. The method of LCD programming is RAM mapping.
CONTR
OL OF LCD DRIVER
CONTROL
The LCD driver control command register is P27. When LDC is 00, the LCD is disabled and changes the
duty only. When LDC is 01, the LCD is blanking, the COM pins are inactive and the SEG pins continuously
output the display data. When LDC is 11, the LCD driver enables, the power switch is turned on and it
cannot be turned off forever except the CPU is reseted or in the STOP operation mode. Users must enable
the LCD driver by self when the CPU is woke up.
P27
3
2
LDC
LDC
0 0
0 1
1 0
1 1
1
0
Initial value : 0000
DUTY
LCD display control
LCD display disable
Blanking
Reserved
LCD display enable
DUTY
0 0
0 1
1 0
1 1
Driving method select
Reserved
1/3 duty ( 1/2 bias )
1/2 duty ( 1/2 bias )
Static
LCD driving methods
There are four kinds of driving methods can be selected by DUTY ( P27.0 ~ P27.1 ). The driving wave
forms of LCD driver are as below :
1/3 duty (1/2 bias)
C
O
M
0
C
O
M
1
C
O
M
2
1/2 duty (1/2 bias)
Static
COM0
COM1
SEG0
SEG1
ON OFF
COM2
SEG2
:
SEG0
SEG0 - COM0
ON
SEG0 - COM1
OFF
Frame
* This specification are subject to be changed without notice.
Frame
Frame
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
LCD frame frequency : According to the drive method to set the frame frequency.
Driving method
1/3 duty
1/2 duty
Static
Frame frequency (Hz)
86 x (3/3) = 86
86 x (3/2) = 129
86
LCD drive voltage
When the power supply is 1.5V, the VEE is connected a capacitor to VSS and the VA is connected a
capacitor to VB for the voltage doubler. The output of VEE is 2 x 1.5V for LCD bias voltage.
VA VEE
0.1uF
0.1uF
VDD
1.5V
VB VSS
PROGRAM EXAMPLE
LDIA
OUTA
LDIA
OUTA
:
:
#0001B
P27
#1100B
P27
; set LCD mode 1/3 duty 1/2 bias
; enable LCD
* This specification are subject to be changed without notice.
10.8.2001
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
LCD DISPLA
Y D
ATA AREA
DISPLAY
DA
The LCD display data is stored in RAM from address 40h ~ 46h, 50h ~ 56h and 60h ~ 66h. The relation of
data area and COM / SEG pin is as below :
bit
Address Increment
0 1 2 30 1 2
Increment
40h~46h (COM0)
50h~56h (COM1)
60h~66h (COM2)
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
Read automatically by the display data from the display data area and send to the LCD driver by the
hardware. Therefore, the display patterns can be changed only by overwritting the contents of the display
data area with the software.
The relation between LCD display RAM and driving method
Driving method
1/3 duty
1/2 duty
Static
LCD display RAM address
40h ~ 46h 50h ~ 56h 50h ~ 66h
COM0
COM1
COM2
COM0
COM1
COM0
-
HIGH SPEED COUNTER
EM73362 has one high speed counter for resistor to frequency oscillation mode, melody mode and auto load
timer mode. The resistor to frequency oscillation (RFO) circuit as show below :
P18(1..0)
P18(3..2)
P3
P5
P4.0(RX)
P4.2(RY)
P4.3(RZ)
MUX
FRF/2X
Resistor FRF
Counter
8-bit Counter
to
frequency
oscillator
P17(1..0)
P17(3..2)
P4.1(CS)
Rate
TCB
TONE
Mode
clock gating
rate rate
* This specification are subject to be changed without notice.
10.8.2001
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
CONTR
OL OF HIGH SPEED COUNTER
CONTROL
The high speed counter is controlled by the command registers (P17, P18) :
P17
3
1
0
Initial value : 0000
MODE
RATE
MODE
0 0
0 1
1 0
1 1
Selection of HTC mode
Disable HTC
Melody mode
Auto load timer mode
Resistor to frequency oscillation mode
RATE
( Hz )
Internal pulse rate / Counter start request frequency
Resistor to frequency
Auto load timer mode / Melody
oscillation mode
mode internal pulse rate
XIN / 20
XIN / 210
12
XIN / 2
XIN / 22
14
XIN / 2
XIN / 24
XIN / 215
XIN / 26
0
0
1
1
P18
2
3
0
1
0
1
2
1
0
Initial value : 0000
RFIP
RFIN
RFIP
0 0
0 1
1 0
1 1
Input frequency of RFO
FRF / 2
FRF / 4
FRF / 8
FRF / 16
RFIN
0 0
0 1
1 0
1 1
Selection of RFO Pin
Normal I/O
P4.0 (RX) for RFO
P4.2 (RY) for RFO
P4.3 (RZ) for RFO
P3 and P5 are the 8-bit binary counter registers of the HTC. P3 is lower nibble register and P5 is higher
nibble register.
P5
3
2
1
0
Higher nibble register
P3
3
2
1
0
Lower nibble register
Initial value : 0000 0000
The HTC consist of one auto-reload and presetable 8-bit binary counter, 12-bit general counter and clock
source selectors. The command register can select the internal clock pulse for the melody, auto load counter
and resistor to frequency oscillation modes. The HTC increases one at the rising edge of the clock pulses.
When the first rising edge occurs by the HTC enabled, the HTC starts counting.
* This specification are subject to be changed without notice.
10.8.2001
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
8-BIT BINARY COUNTER
Write the preset value to the registers
The value of 8-bit binary counter can be presetted by P3 and P5. The value of registers can be loaded into
the 8-bit binary counter when the counter starts counting or occurs overflow. If you write values to the
registers before the next overflow occurs, the preset value can be changed.
Read the count value from the registers
The count value of 8-bit binary counter can be read out from P3 and P5. The value is unstable when you
read out the value during counting. Thus, you must disable the counter before reading out the value.
12-BIT GENERAL COUNTER (TCB)
Write the initial value to the registers
The initial value can be written into the 12-bit counter registers by using STATBL, STATBM and STATBH
instructions. The value of registers can be loaded into the 12-bit binary counter (TCB) and the TCB in
creases one when the 8-bit binary counter overflows.
Read the count value from the registers
The count value of 12-bit binary counter can be read out from the counter registers by using LDATBL,
LDATBM and LDATBH instructions.
20-BIT COUNTER FUNCTION
The 8-bit binary counter is connected to TCB which is one 12-bit general counter and becomes to the 20bit counter. The TCB increases one when the 8-bit binary counter overflows and generats an overflow
interrupt (TRGB) when the TCB overflows. In this case, the TCB cannot be used as a 12-bit counter
alone.
FUNCTION OF HIGH SPEED COUNTER
The HTC has three modes which are RFO mode, melody mode and auto load timer mode. In these
mode, the HTC loads the initial values from the counter registers (P3, P5) when it is enabled by P17 and
it also can be auto-reloaded the initial values when it overflows. The HTC is counted by the internal pulse
and the value of TCB increases one when 8-bit binary counter overflows. The TCB can generate an
overflow interrupt (TRGB) when it overflows. The TRGB cannot be generated when the HTC is in the
melody mode or disabled.
The HTC is disabled when the CPU is reseted or in the STOP/IDLE operation mode. Users must enable
it by self when the CPU is waked up.
* This specification are subject to be changed without notice.
10.8.2001
22
EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Resistor to frequency oscillation mode
In this case, the window gate width interval is from the time base output fall to rise and the value of window
gate width setting is the same as the time base interrupt frequency. The time base can be generated a fixed
frequency interrupt when the time base interrupt (TBI) is enabled. The content of the HTC can be read and
initialized by the TBI interrupt service routine.
HTC input pulse
Time base
8-bit binary counter
n
n+1
00
01
FF
00
01
8-bit binary counter
overflow
00
TCB counter
Disable
HTC and
read data.
Program
Enable HTC
and write data.
001
Window gate width
TBI interrupt service routine
ex. TBI interrupt frequency is XIN/215 Hz (P25=1101B). The pulse rate of RFO is XIN/215 Hz (P17=1111B).
The window gate width of RFO is 214/XIN sec.
PROGRAM EXAMPLE
DSEG
ORG
00H
RFCON: RES
1
:
CSEG
ORG
LBR
ORG
LBR
:
00H
MAIN
0AH
TBI
;initial jump
;timebase interrupt vector address
;timebase interrupt service routine
TBI:
CMP
B
STD
LDIA
OUTA
OUTA
STATBL
STATBM
STATBH
B
#00H,RFCON
TBI1
#01H,RFCON
#00H
P5
P3
;initial TCB & HTC register
TBIEND
* This specification are subject to be changed without notice.
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TBI1:
LDIA
OUTA
INA
STA
INA
STA
LDATBL
STA
LDATBM
STA
LDATBH
STA
#00H
P17
P3
00H
P5
01H
;disable RFO before reading the counter value
;store the counter value to RAM[00] - RAM[04]
02H
03H
04H
TBIEND: RTI
;main program
MAIN:
STD
LDIA
OUTA
LDIA
EXAE
EICIL
LDIA
OUTA
LDIA
OUTA
:
#00H,RFCON
#0001B
P18
#0010B
;P4.0 (RX) output
;enable timebase interrupt
0
#1111B
P17
#1101B
P25
14
;enable RFO mode, the window gate width of RFO=2 /XIN sec.
;enable timebase, interrupt frequency : XIN / 215 Hz
Melody mode
The P4.0/ TONE and TONE pins will output the square wave in the melody mode. When the CPU is not
in the melody mode, the P4.0/ TONE is high and TONE is low.
The 8-bit tone frequency register is P5 and P3. The tone frequency will be changed when users output
the different data to P3. Thus, the data must be output to P5 before P3 when users want to change the
8-bit tone frequency (TF).
P5
P3
3
2
1
0
Higher nibble register
3
2
1
0
Initial value : 0000 0000 ( TF )
Lower nibble register
** FTONE = [ (XIN / 2X) / (100H - TF) ] / 2, TF = 0 ~ 255
** Example : XIN = 32KHz, RATE = 01, TF = 11110000B = 0F0H.
FTONE = [ (32K Hz / 22) / (100H - 0F0H) ] / 2 = 256 Hz.
* This specification are subject to be changed without notice.
10.8.2001
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PROGRAM EXAMPLE :
LDIA
#0FH
OUTA
P5
LDIA
#00H
OUTA
P3
OUTA
P18
LDIA
#0101B
OUTA
P17
:
;enable melody mode
Auto load timer mode
In this mode, there are four different internal pulse rates can be selected by P17. The HTC loads the
initial values by the counter registers (P3, P5) and increases at the rising edges of internal pulse generated
by the time base. The value of TCB increases one when the high speed counter overflows and generates
an overflow interrupt (TRGB) when the TCB overflows.
PROGRAM EXAMPLE :
LDIA
#00H
STATBL
STATBM
STATBH
OUTA
P5
OUTA
P3
OUTA
P18
LDIA
#1011B
OUTA
P17
:
LDIA
#00H
OUTA
P17
INA
P3
STA
00H
INA
P5
STA
01H
LDATBL
STA
02H
LDATBM
STA
03H
LDATBH
STA
04H
; initial TCB & HTC register
; auto load timer mode, internal pulse rate : XIN/26
; disable timer mode
; store the counter value to RAM[00] - RAM[04]
* This specification are subject to be changed without notice.
10.8.2001
25
EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
WATCH-DOG-TIMER ( WDT )
Watch-dog-timer can help user to detect the malfunction (runaway) of CPU and give system a time up
signal every certain time. User can use the time up signal to give system a reset signal when system is fail.
This function is available by mask option. If the mask option of WDT is enabled, it will stop counting when
CPU is reseted or in the STOP operation mode.
The basic structure of watch-dog-timer control is composed by a 4-stage binary counter and a control unit.
The WDT counter counts for a certain time to check the CPU status, if there is no malfunction happened,
the counter will be cleared and counting. Otherwise, if there is a malfunction happened, the WDT control
will send a WDT signal (low active) to reset CPU. The WDT checking period is assign by P21 (WDT
command port).
WDT counter
13
XIN / 2
0
1
2
3
RESET pin
counter clear request
WDT control
mask option
P21
WDT
command port
P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to RESET .
P21
3
2
1
CWC *
*
0
Initial value : 0000
WDT
CWC
0
1
Clear watch-dog-timer counter
Clear counter then return to 1
Nothing
WDT
0
1
Set watch-dog-timer detect time
3 x 213/XIN = 3 x 213/32K Hz = 0.75 sec
7 x 213/XIN = 7 x 213/32K Hz = 1.75 sec
PROGRAM EXAMPLE
To enable WDT with 7 x 213/XIN detection time.
LDIA
OUTA
:
:
#0001B
P21
;set WDT detection time and clear WDT counter
* This specification are subject to be changed without notice.
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
LO
W B
ATTER
Y DETECT
OR ( LBD )
LOW
BA
TTERY
DETECTOR
EM73362 has a built-in low battery detector. This function is disabled when CPU is reseted or in the STOP
/IDLE operation mode. User must enable the low battery detector by self when the CPU is waked up. If the
low battery detector is enabled, the operating current of whole chip will increase.
P15.0
BAT
+
_
reference voltage
CONTR
OL OF LO
W B
ATTER
Y DETECT
OR
CONTROL
LOW
BA
TTERY
DETECTOR
Port15 is the control register of low battery detector. P15.1 (Low battery detector status) is a read-only bit.
When LBE is 1, the low battery detector is enabled. When VDD<1.35 ± 0.05V, SLB is 1.
P15 ( write port )
P15 ( read port )
3
2
1
0
3
*
*
*
LBE
*
LBE
0
1
Low battery detector control
Low battery detector disable
Low battery detector enable
2
*
SLB
0
1
* This specification are subject to be changed without notice.
Initial value : **00
1
0
SLB
*
Status of low battery detector
VDD > 1.25 ± 0.05V
VDD < 1.25 ± 0.05V ( Low battery )
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
RESETTING FUNCTION
When CPU in normal working condition and RESET pin holds in low level for three instruction cycles at least,
then CPU begins to initialize the whole internal states, and when RESET pin changes to high level, CPU begins
to work in normal condition.
The CPU internal state during reset condition is as following table :
Hardware condition in RESET state
Program counter
Status flag
Interrupt enable flip-flop ( EI )
MASK0 ,1, 2, 3
Interrupt latch ( IL )
P3, 5, 15, 16, 17, 18, 19, 21, 25, 27
P4, 6, 7, 8
XIN
Initial value
000h
01h
00h
00h
00h
00h
0Fh
Start oscillation
The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option.
The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD.
RESET
* This specification are subject to be changed without notice.
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
EM73362 PORT DESCRIPTION :
Port
Input function
0
E Input port , wake-up function ,
external interrupt input
1
-2
-3
-4
E Input port ,
Resistor to frequency oscillation
5
-6
E Input port
7
E Input port
8
E Input port
9
-10
-11
-12
-13
-14
-15
I P15.1 ( low battery detector status )
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Output function
I
E
I
E
E
E
I
I
I
I
I
I
I
I
I
--High speed counter register
Output port, P4.0/TONE
High speed counter register
Output port , LCD segment pin
Output port , LCD segment pin
Output port , LCD segment pin
------P15.1 ( low battery detector control )
Stop mode control register
HTC control register
HTC control register
Idle mode control register
-WDT control register
---Timebase control register
-LCD control register
Timer A control register
----
* This specification are subject to be changed without notice.
Note
low nibble
high nibble
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ABSOLUTE MAXIMUM RA
TING
RATING
Items
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Sym.
VDD
VIN
VO
PD
TOPR
TSTG
Ratings
-0.5V to 2V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
100mW
0 °C to 50 °C
-55 °C to 125 °C
Conditions
TOPR = 50 °C
RECOMMENDED OPERA
TING CONDITIONS
OPERATING
Items
Supply voltage
Input voltage
Sym.
VDD
VIH
VIL
Ratings
1.2V to 1.8V
0.90 x VDD to VDD
0V to 0.10 x VDD
Conditions
Fc = 32KHz
DC ELECTRICAL CHARA
CTERISTICS ( VDD = 1.5 ± 0.2V
CHARACTERISTICS
0.2V,, VSS = 0V
0V,, TOPR = 25°C )
Parameters
Supply current
Sym. Min.
IDD
Low battery detector VLBD 1.20
Frequency of RFO FRF1 95
F RF2 8.9
F RF3 780
Frequency ratio of F RF1 10.1
RFO
F RF2
F RF2 10.1
F RF3
Hysteresis voltage V HYS+ 0.50VDD
VHYS- 0.20VDD
Input current
IIH
-15
Output voltage
VOH 1.1
Leakage current
Input resistor
LCD bias voltage
VOL
ILO
RIN
VEE
Typ.
6
5
4
3
0.1
80
40
1.25
120
10.5
980
10.6
Max.
10
8
8
6
1
250
60
1.30
140
13
1300
11.1
Unit
µA
µA
µA
µA
µA
µA
µA
V
KHz
KHz
Hz
10.6
11.1
10
-10
-
0.75VDD
0.40VDD
15
1
-
V
V
µA
µA
µA
V
1.1
-
-
V
50
2VDD-0.1
100
2VDD
0.2
1
200
2VDD+0.1
V
µA
KΩ
V
* This specification are subject to be changed without notice.
Conditions
RC osc.
VDD=1.7V, Fc=32KHz, no load,
X’tal osc. RFO off, LBD off
RC osc.
VDD=1.7V, Fc=32KHz, IDLE
X’tal osc. mode, no load
VDD=1.7V, STOP mode
X’tal osc. VDD=1.5V, Fc=32KHz, RFO on
VDD=1.5V, Fc=32KHz, LBD on
R = 10KΩ,VDD=1.5V
R = 100KΩ,VDD=1.5V
R = 1MΩ,VDD=1.5V
VDD=1.5V, R1=10KΩ, R2=100KΩ,
R3=1MΩ
RESET, P0
P0, Pull-down, VIH=VDD
P0, Pull-up, VIH=VSS
P0, None
Push-pull : P4 high current PMOS, TONE
VDD=1.3V, IOH=-500µA
Push-pull : P4 low current PMOS, others,
VDD=1.3V, IOH=-30µA
VDD=1.3V, IOL=500µA
Open-drain, VDD=1.7V, VO=1.7V
RESET
Voltage doubler
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Parameters
COM, SEG pins
output current
Frequency stability
Frequency variation
Sym.
Vo 1
Vo 2
Vo 3
Min.
VEE-0.1
VDD-0.1
-
Typ.
V EE
V DD
V SS
20
Max.
VDD+0.1
VSS+0.1
-
Unit
V
V
V
%
-
20
-
%
* This specification are subject to be changed without notice.
Conditions
Io1 = -5µA
Io2 = ±5µA
Io3 = 5µA
Fc=32K Hz, RC osc, R=620KΩ,
[F(1.5V)-F(1.3V)]/F(1.5V)
Fc=32K Hz, VDD=1.5V, RC osc,R=620KΩ,
[F(typical)-F(worse case)]/F(typical)
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
RESET PIN TYPE
TYPE RESET_A
RESET
mask option
OSCILLATION PIN TYPE
TYPE OSC_A
TYPE OSC_F
XIN
XIN
RC Osc.
Crystal
Osc.
(inverter)
XOUT
XOUT
INPUT PIN TYPE
TYPE INPUT_H
TYPE INPUT_J
WAKEUP function
mask option
WAKEUP function
mask option
input data
special function
control input
: mask option
: mask option
I/O PIN TYPE
TYPE I/O_N
TYPE I/O_O
path B
Input
data
path A
Output
data
TYPE I/O_N
: mask option
* This specification are subject to be changed without notice.
: mask option
latch
Output
data
Special function output
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TYPE I/O_X
TYPE I/O_Y
Special function
control input
path B
SEL
Input
data
path A
path A
TYPE I/O_N
path B
Input data
Output
Output
data
MUX
TYPE I/O_N
data
latch
Output
data
latch
Output
data
Special function control output
PATH A :For set and clear bit of port instructions, data goes through path A from output data latch to CPU.
PATH B :For input and test instructions, data from output pin go through path B to CPU and the output data
latch will be set to high.
* This specification are subject to be changed without notice.
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
PAD DIAGRAM
49
48
47
46
45
44
43
42
41
40
39
38
37
VA
7
VSS
8
XIN
9
10
VDD
11
35
P8.1/SEG16
34
P8.2/SEG17
33
P8.3/SEG18
32
P7.0/SEG19
31
P7.1/SEG20
30
P7.2/SEG21
29
P7.3/SEG22
28
P6.0/SEG23
27
P6.1/SEG24
26
P6.2/SEG25
25
P6.3/SEG26
24
COM2
Y
(0,0)
X
EM73362
12
BAT
XOUT
P8.0/SEG15
13
14
15
16
17
18
19
20
21
22
23
TEST
6
P4.3(RZ)
VB
P4.2(RS)
5
P4.1(CS)
VEE
P4.0(RX)/TONE
4
TONE
COM0
P0.3/WAKEUP3
COM1
3
P0.2(INT0)/WAKEUP2
2
P0.1/WAKEUP1
SEG0
P0.0(INT1)/WAKEUP0
1
RESET
SEG1
36
Chip Size : 2140 x 2070 UM.
Pad No.
1
2
3
4
5
6
7
Symbol
SEG1
SEG0
COM1
COM0
VEE
VB
VA
X
-911.4
-911.4
-911.4
-911.4
-910.5
-910.5
-910.5
* This specification are subject to be changed without notice.
Y
752.3
632.4
512.5
392.0
270.5
148.4
27.4
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34
EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Pad No.
Symbol
X
8
VSS
-896.4
9
XIN
-911.4
10
XOUT
-911.4
11
VDD
-892.4
12
BAT
-705.0
13
RESET
-583.0
14
P0.0(INT1)/WAKEUP0
-463.1
15
P0.1/WAKEUP1
-338.5
16
P0.2(INT0)/WAKEUP2
-213.8
17
PO.3/WAKEUP3
-89.2
18
TONE
47.3
19
P4.0(RX)/TONE
168.8
20
P4.1(CS)
290.4
21
P4.2(RS)
411.9
22
P4.3(RZ)
533.5
23
TEST
655.6
24
COM2
907.9
25
P6.3/SEG26
907.1
26
P6.2/SEG25
907.1
27
P6.1/SEG24
907.1
28
P6.0/SEG23
907.1
29
P7.3/SEG22
907.1
30
P7.2/SEG21
907.1
31
P7.1/SEG20
907.1
32
P7.0/SEG19
907.1
33
P8.3/SEG18
907.1
34
P8.2/SEG17
907.1
35
P8.1/SEG16
907.1
36
P8.0/SEG15
907.1
37
SEG14
692.3
38
SEG13
572.4
39
SEG12
452.5
40
SEG11
332.6
41
SEG10
212.7
42
SEG9
92.8
43
SEG8
-27.1
44
SEG7
-147.0
45
SEG6
-266.9
46
SEG5
-386.8
47
SEG4
-506.7
48
SEG3
-626.6
49
SEG2
-746.5
Unit : µm
For PCB layout, IC substrate must be floated or connected to Vss.
* This specification are subject to be changed without notice.
Y
-132.1
-263.9
-636.1
-857.5
-874.1
-874.1
-874.1
-874.1
-874.1
-874.1
-877.4
-877.4
-877.4
-877.4
-877.4
-874.1
-772.2
-637.8
-516.2
-394.7
-273.1
-151.6
-30.0
91.5
213.1
334.6
456.2
577.7
699.3
874.7
874.7
874.7
874.7
874.7
874.7
874.7
874.7
874.7
874.7
874.7
874.7
874.7
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INSTRUCTION TABLE
(1) Data Transfer
Mnemonic
LDA
x
LDAM
LDAX
LDAXI
LDH
#k
LDHL x
LDIA #k
LDL
#k
STA
x
STAM
STAMD
STAMI
STD
#k,y
STDMI #k
THA
TLA
Object code ( binary )
Operation description
0110 1010 xxxx xxxx
0101 1010
0110 0101
0110 0111
1001 kkkk
0100 1110 xxxx xx00
1101 kkkk
1000 kkkk
0110 1001 xxxx xxxx
0101 1001
0111 1101
0111 1111
0100 1000 kkkk yyyy
1010 kkkk
0111 0110
0111 0100
Acc←RAM[x]
Acc ←RAM[HL]
Acc←ROM[DP]L
Acc←ROM[DP]H,DP+1
HR←k
LR←RAM[x],HR←RAM[x+1]
Acc←k
LR←k
RAM[x]←Acc
RAM[HL]←Acc
RAM[HL]←Acc, LR-1
RAM[HL]←Acc, LR+1
RAM[y]←k
RAM[HL]←k, LR+1
Acc←HR
Acc←LR
Object code ( binary )
Operation description
Byte
2
1
1
1
1
2
1
1
2
1
1
1
2
1
1
1
Cycle
2
1
2
2
1
2
1
1
2
1
1
1
2
1
1
1
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C
Flag
Z
Z
Z
S
C'
C'
C
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
S
C'
C'
C'
C'
C'
C'
C'
C
C
C
C'
S
1
1
1
1
1
1
1
1
1
1
C
C'
1
C'
1
1
(2) Rotate
Mnemonic
RLCA
RRCA
0101 0000
0101 0001
←CF←Acc←
→CF→Acc→
Byte
1
1
Cycle
1
1
(3)
3) Arithmetic operation
Mnemonic
Object code ( binary )
Operation description
Byte
ADCAM
ADD
#k,y
ADDA #k
ADDAM
ADDH #k
ADDL #k
ADDM #k
DECA
DECL
DECM
INCA
0111
0100
0110
0111
0110
0110
0110
0101
0111
0101
0101
Acc←Acc + RAM[HL] + CF
RAM[y]←RAM[y] +k
Acc←Acc+k
Acc←Acc + RAM[HL]
HR←HR+k
LR←LR+k
RAM[HL]←RAM[HL] +k
Acc←Acc-1
LR←LR-1
RAM[HL]←RAM[HL]-1
Acc←Acc + 1
1
2
2
1
2
2
2
1
1
1
1
0000
1001 kkkk yyyy
1110 0101 kkkk
0001
1110 1001 kkkk
1110 0001 kkkk
1110 1101 kkkk
1100
1100
1101
1110
* This specification are subject to be changed without notice.
Cycle
1
2
2
1
2
2
2
1
1
1
1
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INCL
INCM
SUBA #k
SBCAM
SUBM #k
0111 1110
0101 1111
0110 1110 0111 kkkk
0111 0010
0110 1110 1111 kkkk
LR←LR + 1
RAM[HL]←RAM[HL]+1
Acc←k-Acc
Acc←RAM[HLl - Acc - CF'
RAM[HL]←k - RAM[HL]
1
1
2
1
2
1
1
2
1
2
C
-
Z
Z
Z
Z
Z
C'
C'
C
C
C
(4) Logical operation
Object code ( binary )
Operation description
Byte
ANDA #k
ANDAM
ANDM #k
ORA #k
ORAM
ORM #k
XORAM
0110
0111
0110
0110
0111
0110
0111
Acc←Acc&k
Acc←Acc & RAM[HL]
RAM[HL]←RAM[HL]&k
Acc←Acc k
Acc ←Acc RAM[HL]
RAM[HL]←RAM[HL] k
Acc←Acc^RAM[HL]
2
1
2
2
1
2
1
Operation description
Byte
--
1110 0110 kkkk
1011
1110 1110 kkkk
1110 0100 kkkk
1000
1110 1100 kkkk
1001
----
Mnemonic
Cycle
2
1
2
2
1
2
1
Flag
C
Z
Z
Z
Z
Z
Z
Z
Z
S
Z'
Z'
Z'
Z'
Z'
Z'
Z'
C
Flag
Z
S
(5) Exchange
Mnemonic
EXA x
EXAH
EXAL
EXAM
EXHL x
Object code ( binary )
0110 1000 xxxx xxxx
0110 0110
0110 0100
0101 1000
0100 1100 xxxx xx00
Cycle
Acc↔RAM[x]
Acc↔HR
Acc↔LR
Acc↔RAM[HL]
LR↔RAM[x],
HR↔RAM[x+1]
2
1
1
1
2
2
2
1
-
Z
Z
Z
Z
1
1
1
1
2
2
-
-
1
Operation description
Byte
C
Flag
Z
S
(6) Branch
Mnemonic
Object code ( binary )
SBR a
00aa aaaa
LBR a
1100 aaaa aaaa aaaa
Cycle
If SF=1 then PC←PC11-6.a5-0
else null
If SF= 1 then PC←a else null
1
1
-
-
1
2
2
-
-
1
Operation description
Byte
C
Flag
Z
S
C
C
C
C
-
Z
Z
Z
Z
Z
Z
Z'
Z'
Z'
C
Z'
C
(7) Compare
Mnemonic
CMP #k,y
CMPA x
CMPAM
CMPH #k
CMPIA #k
CMPL #k
Object code ( binary )
0100 1011 kkkk yyyy
0110 1011 xxxx xxxx
0111 0011
0110 1110 1011 kkkk
1011 kkkk
0110 1110 0011 kkkk
k-RAM[y]
RAM[x]-Acc
RAM[HL] - Acc
k - HR
k - Acc
k-LR
* This specification are subject to be changed without notice.
2
2
1
2
1
2
Cycle
2
2
1
2
1
2
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
(8) Bit manipulation
Mnemonic
Object code ( binary )
Operation description
Byte
Cycle
C
-
Flag
Z
-
S
1
1
1
1
1
1
1
1
*
*
*
*
*
*
*
S
-
1111 00bb
0110 1101 11bb pppp
0110 0000
0110 1100 11bb yyyy
1111 01bb
0110 1101 01bb pppp
0110 0010
0110 1100 01bb yyyy
0110 1100 00bb yyyy
1111 10bb
1111 11bb
0110 1101 00bb pppp
0110 0001
0110 1100 10bb yyyy
0110 1101 10bb pppp
RAM[HL]b←0
PORT[p]b←0
PORT[LR3-2+4]LR1-0←0
RAM[y]b←0
RAM[HL]b←1
PORT[p]b←1
PORT[LR3-2+4]LRl-0←1
RAM[y]b←1
SF←RAM[y]b'
SF←Accb'
SF←RAM[HL]b'
SF←PORT[p]b'
SF←PORT[LR3-2+4]LR1-0'
SF←RAM[y]b
SF←PORT[p]b
1
2
1
2
1
2
1
2
2
1
1
2
1
2
2
Mnemonic
Object code ( binary )
Operation description
Byte
LCALL a
0100 0aaa aaaa aaaa
2
2
SCALL a
1110 nnnn
1
2
-
-
-
RET
0100 1111
STACK[SP]←PC,
SP←SP -1, PC←a
STACK[SP]←PC,
SP←SP - 1, PC←a,a = 8n + 6
(n =1∼15),0086h (n = 0)
SP←SP + 1, PC←STACK[SP]
Flag
C
Z
-
1
2
-
-
-
Object code ( binary )
Operation description
Byte
CLM
CLP
CLPL
CLR
SEM
SEP
SEPL
SET
TF
TFA
TFM
TFP
TFPL
TT
TTP
b
p,b
y,b
b
p,b
y,b
y,b
b
b
p,b
y,b
p,b
1
2
2
2
1
2
2
2
2
1
1
2
2
2
2
(9) Subroutine
Cycle
(10) Input/output
Mnemonic
INA
INM
OUT
OUTA
OUTM
p
p
#k,p
p
p
0110 1111 0100 pppp
0110 1111 1100 pppp
0100 1010 kkkk pppp
0110 1111 000p pppp
0110 1111 100p pppp
Acc←PORT[p]
RAM[HL]←PORT[p]
PORT[p]←k
PORT[p]←Acc
PORT[p]←RAM[HL]
2
2
2
2
2
Operation description
Byte
Cycle
2
2
2
2
2
C
-
Flag
Z
Z
-
S
Z'
Z'
1
1
1
C
-
Flag
Z
-
S
1
1
(11) Flag manipulation
Mnemonic
CGF
SGF
Object code ( binary )
0101 0111
0101 0101
GF←0
GF←1
* This specification are subject to be changed without notice.
1
1
Cycle
1
1
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EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TFCFC
TGS
TTCFS
TZS
0101 0011
0101 0100
0101 0010
0101 1011
SF←CF', CF←0
SF←GF
SF←CF, CF←1
SF←ZF
1
1
1
1
Operation description
Byte
IL←IL & r
EIF←0,IL←IL&r
EIF←1,IL←IL&r
MASK↔Acc
SP←SP+1,FLAG.PC
←STACK[SP],EIF ←1
2
2
2
1
1
Operation description
Byte
1
1
1
1
0
1
-
-
*
*
*
*
(12) Interrupt control
Mnemonic
CIL
r
DICIL r
EICIL r
EXAE
RTI
Object code ( binary )
0110 0011 11rr rrrr
0110 0011 10rr rrrr
0110 0011 01rr rrrr
0111 0101
0100 1101
Cycle
2
2
2
1
2
Flag
C
Z
*
*
S
1
1
1
1
*
Flag
Z
-
S
-
Flag
C
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10.8.2001
39
(13) CPU control
Mnemonic
NOP
Object code ( binary )
0101 0110
no operation
1
Cycle
1
C
-
(14) Timer/Counter & Data pointer & Stack pointer control
Mnemonic
Object code ( binary )
Operation description
Byte
LDADPL
LDADPM
LDADPH
LDASP
LDATAL
LDATAM
LDATAH
LDATBL
LDATBM
LDATBH
STADPL
STADPM
STADPH
STASP
STATAL
STATAM
STATAH
STATBL
STATBM
STATBH
0110 1010 1111 1100
0110 1010 1111 1101
0110 1010 1111 1110
0110 1010 1111 1111
0110 1010 1111 0100
0110 1010 1111 0101
0110 1010 1111 0110
0110 1010 1111 1000
0110 1010 1111 1001
0110 1010 1111 1010
0110 1001 1111 1100
0110 1001 1111 1101
0110 1001 1111 1110
0110 1001 1111 1111
0110 1001 1111 0100
0110 1001 1111 0101
0110 1001 1111 0110
0110 1001 1111 1000
0110 1001 1111 1001
0110 1001 1111 1010
Acc←[DP]L
Acc←[DP] M
Acc←[DP] H
Acc←SP
Acc←[TA] L
Acc←[TA]M
Acc←[TA] H
Acc←[TB]L
Acc←[TB]M
Acc←[TB]H
[DP] L←Acc
[DP] M←Acc
[DP] H←Acc
SP←Acc
[TA] L←Acc
[TA] M←Acc
[TA] H←Acc
[ TB]L←Acc
[TB]M←Acc
[TB] H←Acc
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
* This specification are subject to be changed without notice.
Cycle
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
**** SYMBOL DESCRIPTION
Symbol
Description
Symbol
HR
PC
SP
ACC
CF
SF
EI
MASK
ΤΑ
RAM[HL]
ROM[DP]L
[DP]L
[DP]H
H register
Program counter
Stack pointer
Accumulator
Carry flag
Status flag
Enable interrupt register
Interrupt mask
Timer/counter A
Data memory (address : HL )
Low 4-bit of program memory
Low 4-bit of data pointer register
High 4-bit of data pointer register
LR
DP
STACK[SP]
FLAG
ZF
GF
IL
PORT[p]
ΤΒ
RAM[x]
ROM[DP]H
[DP]M
[TA]L([TB]L)
[TA]M([TB]M)
Middle 4-bit of timer/counter A
(timer/counter B) register
Transfer
Addition
Logic AND
Logic XOR
Concatenation
8-bit RAM address
4-bit or 5-bit port address
6-bit interrupt latch
Contents of bit assigned by bit
1 to 0 of LR
Bit 3 to 2 of LR
[TA]H([TB]H)
LR 1-0
LR3-2
↔
--
←
+
&
^
.
x
p
r
'
#k
y
b
PC11-6
a5-0
* This specification are subject to be changed without notice.
Description
L register
Data pointer
Stack specified by SP
All flags
Zero flag
General flag
Interrupt latch
Port ( address : p )
Timer/counter B
Data memory (address : x )
High 4-bit of program memory
Middle 4-bit of data pointer register
Low 4-bit of timer/counter A
(timer/counter B) register
High 4-bit of timer/counter A
(timer/counter B) register
Exchange
Substraction
Logic OR
Inverse operation
4-bit immediate data
4-bit zero-page address
Bit address
Bit 11 to 6 of program counter
Bit 5 to 0 of destination address for
branch instruction
10.8.2001
40