EM78P447N
OTP ROM
EM78P447N
8-BIT MICRO-CONTROLLER
Version 1.0
EM78P447N
OTP ROM
Specification Revision History
Version
1.0
Content
Initial version
29/10/2004
Application Note
AN-001: Seven-segment and I/O Port
AN-002: Keystroke Times Displayed by Seven-segment
AN-003: Jumping out of DELAY Subroutine Loop by External Keystroke
AN-004: LED with Controlled Rotating Direction
AN-005: Sing a Song "Draw" of EM78447
AN-006: Stepping Motor
AN-007: EM78P447S v.s. EM78P447 on the DC characteristics and program timing
AN-008: About EM78P447S Sleep2 mode setting
This specification is subject to change without prior notice.
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10.21.2004 (V1.0)
EM78P447N
OTP ROM
1. GENERAL DESCRIPTION
EM78P447N is an 8-bit microprocessor with low-power and high-speed CMOS technology and high
noise immunity. It is equipped with 4K*13-bits Electrical One Time Programmable Read Only Memory
(OTP-ROM). It provides three PROTECTION bits to prevent user’s code in the OTP memory from being
intruded. Seven OPTION bits are also available to meet user’s requirements.
With its OTP-ROM feature, the EM78P447N is able to offer a convenient way of developing and
verifying user’s programs. Moreover, user can take advantage of ELAN Writer to easily program his
development code.
This specification is subject to change without prior notice.
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10.21.2004 (V1.0)
EM78P447N
OTP ROM
2. FEATURES
• Operating voltage range: 2.5V~5.5V.
• Operating temperature range: -40°C~85°C.
• Operating frequency rang( base on 2 clocks)
* Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.5V.
* RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.5V.
• Low power consumption:
* Less then 2.2 mA at 5V/4MHz
* Typically 35 µA, at 3V/32KHz
* Typically 2 µA, during sleep mode
• 4K × 13 bits on chip ROM
• Three protection bits to prevent intrusion of OTP memory codes
• One configuration register to accommodate user’s requirements
• 148× 8 bits on chip registers(SRAM, general purpose register)
• 3 bi-directional I/O ports
• 5 level stacks for subroutine nesting
• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt
• Two clocks per instruction cycle
• Power down (SLEEP) mode
• Two available interruptions
* TCC overflow interrupt
* External interrupt
• Programmable free running watchdog timer
• 10 programmable pull-high pins
• 2 programmable open-drain pins
• 2 programmable R-option pins
• Package types:
* 28 pin DIP 600mil: EM78P447NAP
* 28 pin SOP 300mil : EM78P447NAM
* 28 pin SSOP 209mil: EM78P447NAS
* 32 pin DIP 600mil: EM78P447NBP
* 32 pin SOP 450mil : EM78P447NBWM
This specification is subject to change without prior notice.
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10.21.2004 (V1.0)
EM78P447N
OTP ROM
• 99.9% single instruction cycle commands
• The transient point of system frequency between HXT and LXT is around 400KHz
This specification is subject to change without prior notice.
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10.21.2004 (V1.0)
EM78P447N
OTP ROM
3. PIN ASSIGNMENT
P55
1
32
P56
31
P57
28
/RESET
TCC
3
30
/RESET
OSCI
TCC
2
27
OSCI
VDD
4
29
OSCI
26
OSCO
VDD
3
26
OSCO
NC
5
28
OSCO
4
25
P77
/INT
4
25
P77
Vss
6
27
P77
5
24
P76
P50
5
24
P76
/INT
7
26
P76
23
P75
P51
6
23
P75
P50
8
25
P75
22
P74
P52
7
22
P74
P51
9
24
P74
21
P73
P53
8
21
P73
P52
10
23
P73
20
P72
P60
9
20
P72
P53
11
22
P72
19
P71
P61
10
19
P71
P60
12
21
P71
P70
P62
11
18
P70
P61
13
20
P70
P63
12
17
P62
14
19
P67
16
P66
P63
15
18
P66
15
P65
P64
16
17
P65
28
/RESET
VDD
2
27
NC
3
Vss
/INT
6
P51
7
P52
8
P53
9
P60
10
P61
11
18
P62
12
17
P63
13
16
P66
P64
13
P64
14
15
P65
Vss
14
EM78P447NAP
EM78P447NAM
P50
P67
DIP
SOP
P67
EM78P447NBP
EM78P447NBWM
2
1
1
EM78P447NAS
P54
Vss
TCC
DIP
SOP
SSOP
Fig. 1 Pin Assignment
Table 1 EM78P447NAP and EM78P447NAM Pin Description
Symbol Pin No.
VDD
2
Type
-
OSCI
27
I
OSCO
26
I/O
TCC
1
I
/RESET
28
I
P50~P53
6~9
I/O
P60~P67 10~17
I/O
P70~P77 18~25
I/O
Function
* Power supply.
* XTAL type: Crystal input terminal or external clock input pin.
* RC type: RC oscillator input pin.
* XTAL type: Output terminal for crystal oscillator or external clock input pin.
* RC type: Instruction clock output.
* External clock signal input.
* The real time clock/counter (with Schmitt trigger input pin) must be tied to
VDD or VSS if not in use.
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
* P50~P53 are bi-directional I/O pins.
* P60~P67 are bi-directional I/O pins. These can be pulled-high internally
by software control.
* P70~P77 are bi-directional I/O pins.
* P74~P75 can be pulled-high internally by software control.
* P76~P77 can have open-drain output by software control.
* P70 and P71 can also be defined as the R-option pins.
This specification is subject to change without prior notice.
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EM78P447N
OTP ROM
/INT
VSS
NC
5
4
3
I
-
* External interrupt pin triggered by falling edge.
* Ground.
* No connection.
Table 2 EM78P447NAS Pin Description
Symbol Pin No.
VDD
3
Type
-
OSCI
27
I
OSCO
26
I/O
TCC
2
I
/RESET
28
I
P50~P53
5~8
9~13,
P60~P67
15~17
I/O
P70~P77 18~25
I/O
/INT
VSS
4
1,14
I/O
I
-
Function
* Power supply.
* XTAL type: Crystal input terminal or external clock input pin.
* RC type: RC oscillator input pin.
* XTAL type: Output terminal for crystal oscillator or external clock input pin.
* RC type: Instruction clock output.
* External clock signal input.
* The real time clock/counter (with Schmitt trigger input pin) must be tied to
VDD or VSS if not in use.
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
* P50~P53 are bi-directional I/O pins.
* P60~P67 are bi-directional I/O pins. These can be pulled -high internally
by software control.
* P70~P77 are bi-directional I/O pins.
* P74~P75 can be pulled -high internally by software control.
* P76~P77 can have open-drain output by software control.
* P70 and P71 can also be defined as the R-option pins.
* External interrupt pin triggered by falling edge.
* Ground.
Table 3 EM78P447NBP and EM78P447NBWM Pin Description
Symbol
VDD
Pin No.
4
Type
-
OSCI
29
I
OSCO
28
I/O
TCC
3
I
/RESET
30
I
P50~P57
8~11,2~1,
32~31
I/O
P60~P67
12~19
I/O
P70~P77
20~27
I/O
7
6
5
I
-
/INT
VSS
NC
Function
* Power supply.
* XTAL type: Crystal input terminal or external clock input pin.
* RC type: RC oscillator input pin.
* XTAL type: Output terminal for crystal oscillator or external clock input
pin.
* RC type: Instruction clock output.
* External clock signal input.
* The real time clock/counter (with Schmitt trigger input pin), must be tied
to VDD or VSS if not in use.
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will keep in reset condition.
* P50~P57 are bi-directional I/O pins.
* P60~P67 are bi-directional I/O pins. These can be pulled -high internally
by software control.
* P70~P77 are bi-directional I/O pins.
* P74~P75 can be pulled-high internally by software control.
* P76~P77 can have open-drain output by software control.
* P70 and P71 can also be defined as the R-option pins.
* External interrupt pin triggered by falling edge.
* Ground.
* No connection.
This specification is subject to change without prior notice.
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EM78P447N
OTP ROM
4. FUNCTION DESCRIPTION
OSCI
/R E S E T
OSCO
TCC
/IN T
W D T T im e r
STACK 1
P C
O s c illa to r/T im in g
STACK 2
C o n tro l
STACK 3
P re s c a le
STACK 5
W DT
T im -e o u t
In te rru p t
C o n tro l
R 1 (T C C )
In s tru c tio n
R e g is te r
ALU
In s tru c tio n
D ecoder
RAM
S le e p
&
W ake
C o n tro l
STACK 4
ROM
r
R3
ACC
R4
DATA & CO NTRO L BUS
IO C 5
R5
IO C 6
R6
PPPPPPPP
55555555
0 1 2 3 45 6 7
PPPPPPPP
66666666
0 1 2 3 45 6 7
IO C 7
R7
PPPPPPPP
77777777
0 1 2 3 45 6 7
Fig. 2 Functional Block Diagram
4.1 Operational Registers
1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to act as an indirect addressing pointer.
Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4).
2. R1 (Time Clock /Counter)
• Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or
by the instruction cycle clock.
• Writable and readable as any other registers.
• Defined by resetting PAB (CONT-3).
• The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
This specification is subject to change without prior notice.
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EM78P447N
OTP ROM
• The contents of the prescaler counter will be cleared only when TCC register is written a value.
3. R2 (Program Counter) & Stack
• Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in
Fig.3.
• Generating 1024×13 bits on-chip OTP ROM addresses to the relative programming instruction
codes. One program page is 1024 words long.
• R2 is set as all "0"s when under RESET condition.
• "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC
to go to any location within a page.
• "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus,
the subroutine entry address can be located anywhere within a page.
• "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level
stack.
• "ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits of
the PC are cleared.
• "MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the
ninth and tenth bits of the PC are cleared.
• Any instruction that writes to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will cause the ninth
and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256
locations of a page.
• All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would
change the contents of R2. Such instruction will need one more instruction cycle.
R3
A11 A10 A9 A8
A7
~
A0
Hardware Vector
Software Vector
00 PAGE0 0000~03FF
01 PAGE1 0400~07FF
10 PAGE2 0800~0BFF
11 PAGE3 0C00~0FFF
User Memory
Space
CALL
RET
RETL
RETI
000H
001H
002H
On-chip Program
Memory
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Reset Vector
FFFH
Fig. 3 Program Counter Organization
This specification is subject to change without prior notice.
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10.21.2004 (V1.0)
EM78P447N
OTP ROM
Aaddress
R PAGE registers
IOC PAGE registers
00
R0
(Indirect Addressing Register)
01
R1
(Time Clock Counter)
02
R2
(Program Counter)
Reserve
03
R3
(Status Register)
Reserve
04
R4
(RAM Select Register)
Reserve
05
R5
(Port5)
IOC5
(I/O Port Control Register)
06
R6
(Port6)
IOC6
(I/O Port Control Register)
07
R7
(Port7)
IOC7
(I/O Port Control Register)
Reserve
CONT (Control Register)
08
General Register
Reserve
09
General Register
Reserve
0A
General Register
Reserve
0B
General Register
0C
General Register
Reverse
0D
General Register
Reverse
0E
General Register
IOCE
(WDT,SLEEP2,Open Drain,R -Option
Control Register)
0F
General Register
IOCF
(Interrupt Mask Register)
10
︰
1F
General Registers
20
：
3E
Bank0
3F
R3F
Bank1
IOCB
Bank2
(Wake-Up Control Register for Port6 )
Bank3
(Interrupt Status Register)
Fig. 4 Data Memory Configuration
This specification is subject to change without prior notice.
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10.21.2004 (V1.0)
EM78P447N
OTP ROM
4. R3 (Status Register)
7
GP
6
PS1
5
PS0
4
T
3
P
2
Z
1
DC
0
C
• Bit 7 (GP) General read/write bit.
• Bits 6 (PS1) ~ 5 (PS0) Page select bits. PS1~PS0 are used to pre-select a program memory page.
When executing a "JMP", "CALL", or other instructions which causes the program counter to
change (e.g. MOV R2, A), PS1~PS0 are loaded into the 11th and 12th bits of the program counter
and select one of the available program memory pages. Note that RET (RETL, RETI) instruction
does not change the PS0~PS1 bits. That is, the return will always be to the page from where the
subroutine was called, regardless of the PS1~PS0 bits current setting.
PS1
0
0
1
1
PS0
0
1
0
1
Program memory page [Address]
Page 0 [000-3FF]
Page 1 [400-7FF]
Page 2 [800-BFF]
Page 3 [C00-FFF]
• Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" commands, or during power up, and
reset to 0 with the WDT time-out.
• Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a
"SLEP" command.
• Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
• Bit 1 (DC) Auxiliary carry flag.
• Bit 0 (C) Carry flag
5. R4 (RAM Select Register)
• Bits 7~6 determine which bank is activated among the 4 banks.
• Bits 5~0 are used to select the registers (address: 00~3F) in the indirect addressing mode.
• If no indirect addressing is used, the RSR can be used as an 8-bit general-purpose read/writer
register.
• See the configuration of the data memory in Fig. 4.
6. R5~R7 (Port 5 ~ Port7)
• R5, R6 and R7 are I/O registers
7. R8~R1F and R20~R3E (General Purpose Register)
• R8~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
This specification is subject to change without prior notice.
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EM78P447N
OTP ROM
8. R3F (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
EXIF
-
-
TCIF
• Bit 3 (EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by software
• Bit 0 (TCIF) the TCC overflow interrupt flag. Set as TCC overflows; flag cleared by software.
• Bits 1, 2, 4~7 are not used and read are as “0”.
• "1" means interrupt request, "0" means non-interrupt.
• R3F can be cleared by instruction, but cannot be set by instruction.
• IOCF is the interrupt mask register.
• Note that reading R3F will obtain the result of the R3F "logic AND" and IOCF.
4.2 Special Purpose Registers
1. A (Accumulator)
• Internal data transfer, or instruction operand holding.
• It cannot be addressed.
2. CONT (Control Register)
7
6
5
4
3
2
1
0
/PHEN
/INT
TS
TE
PAB
PSR2
PSR1
PSR0
• Bit 7 (/PHEN) Control bit used to enable the pull-high of P60~P67, P74 and P75 pins
0: Enable internal pull-high.
1: Disable internal pull-high.
• CONT register is both readable and writable.
• Bit 6 (/INT) Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
• Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
• Bit 4 (TE) TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
• Bit 3 (PAB) Prescaler assignment bit.
This specification is subject to change without prior notice.
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EM78P447N
OTP ROM
0: TCC
1: WDT
• Bit 2 (PSR2) ~ Bit 0 (PSR0) TCC/WDT prescaler bits.
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
3. IOC5 ~ IOC7 (I/O Port Control Register)
• "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.
• IOC5 and IOC7 registers are both readable and writable.
4. IOCB (Wake-up Control Register for Port6)
7
6
5
4
3
2
1
0
/WUE7
/WUE6
/WUE5
/WUE4
/WUE3
/WUE2
/WUE1
/WUE0
• Bit 7 (/WUE7) Control bit is used to enable the wake-up function of P67 pin.
• Bit 6 (/WUE6) Control bit is used to enable the wake-up function of P66 pin.
• Bit 5 (/WUE5) Control bit is used to enable the wake-up function of P65 pin.
• Bit 4 (/WUE4) Control bit is used to enable the wake-up function of P64 pin.
• Bit 3 (/WUE3) Control bit is used to enable the wake-up function of P63 pin.
• Bit 2 (/WUE2) Control bit is used to enable the wake-up function of P62 pin.
• Bit 1 (/WUE1) Control bit is used to enable the wake-up function of P61 pin.
• Bit 0 (/WUE0) Control bit is used to enable the wake-up function of P60 pin.
0: Enable internal wake-up.
1: Disable internal wake-up.
• IOCB Register is both readable and writable.
5. IOCE (WDT Control Register)
7
-
6
ODE
5
WDTE
4
SLPC
3
ROC
2
-
1
-
0
/WUE
• Bit 6 (ODE) Control bit is used to enable the open-drain of P76 and P77 pins
0: Disable open-drain output.
This specification is subject to change without prior notice.
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EM78P447N
OTP ROM
1: Enable open-drain output.
The ODE bit can be read and written.
• Bit 5 (WDTE) Control bit used to enable Watchdog timer.
The WDTE bit is useful only when ENWDT, the CODE Option bit, is "0". It is only when the ENWDT bit
is "0" that WDTE bit. is able to disabled/enabled the WDT.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is "1". That is, if the ENWDT bit is
"1", WDT is always disabled no matter what the WDTE bit status is.
The WDTE bit can be read and written.
• Bit 4 (SLPC) This bit is set by hardware at the low level trigger of wake-up signal and is cleared by
software. SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator is
stopped, and the controller enters into SLEEP2 mode) on the high-to-low transition and is enabled
(controller is awakened from SLEEP2 mode) on low-to-high transition. In order to ensure the stable
output of the oscillator, once the oscillator is enabled again, there is a delay for approximately 18ms1
(oscillator start-up timer, OST) before the next instruction of the program is executed. The OST is
always activated by a wake-up event from sleep mode regardless of the Code Option bit ENWDT
status is "0" or otherwise. After waking up, the WDT is enabled if the Code Option ENWDT is "1".
The block diagram of SLEEP2 mode and wake-up invoked by an input trigger is depicted in Fig. 5.
The SLPC bit can be read and written.
• Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of R-option pins
(P70, P71) for the controller to read. Clearing ROC will disable the R-option function. Otherwise, the
R-option function is introduced. Users must connect the P71 pin or/and P70 pin to VSS with a
430KΩ external resistor (Rex). If Rex is connected/disconnected with VDD, the status of P70 (P71)
will be read as "0"/"1" (refer to Fig. 7(b)). The ROC bit can be read and written.
• Bit 0 (/WUE) Control bit is used to enable the wake-up function of P74 and P75.
0: Enable the wake-up function.
1: Disable the wake-up function.
The /WUE bit can be read and written.
• Bits 1~2, and 7 Not used.
1
<Note>: Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 19.6ms ± 30%
This specification is subject to change without prior notice.
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EM78P447N
OTP ROM
6. IOCF (Interrupt Mask Register)
7
-
6
-
5
-
4
-
3
EXIE
2
-
1
-
0
TCIE
• Bit 3 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
• Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
• Bits 1, 2 and 4~7 Not used.
• Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".
• Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction (refer to Fig.
9).
• IOCF register is both readable and writable.
/WUE0
Oscillator
Enable
Disable
/WUE1
Reset
Q
PR D
CLK
Q
Clear
VCC
CL
Set
/WUE7
8
from S/W
P60~P67
VCC
/WUE
/PHEN
2
P74~P75
Fig. 5 Sleep Mode and Wake-Up Circuits on I/O Ports Block Diagram
This specification is subject to change without prior notice.
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EM78P447N
OTP ROM
4.3 TCC/WDT & Prescaler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available for either the
TCC or WDT only at any given time, and the PAB bit of the CONT register is used to determine the
prescaler assignment. The PSR0~PSR2 bits determine the ratio. The prescaler is cleared each time the
instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode,
are cleared by the “WDTC” or “SLEP” instructions. Fig. 6 depicts the circuit diagram of TCC/WDT.
• R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or external clock input
(edge selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at
every instruction cycle (without prescaler). Referring to Fig. 6, CLK=Fosc/2 or CLK=Fosc/4
selection is determined by the CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0",
and CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source comes from external clock input, TCC
is increased by 1 at every falling edge or rising edge of TCC pin.
• The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after
the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode,
a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any
time during normal mode by software programming. Refer to WDTE bit of IOCE register. Without
prescaler, the WDT time-out period is approximately 18 ms1 (default).
Data Bus
CLK(=Fosc/2)
0
TCC
Pin
1
M
U
X
TE
1
M
U
X
0
TS
0
WDT
1
WDTE
(in IOCE)
SYNC
2 cycles
TCC overflow interrupt
PAB
M
U
X
TCC(R1)
8-bit Counter
8-to-1 MUX
PAB
0
PSR0~PSR2
1
MUX
PAB
WDT timeuot
Fig. 6 TCC and WDT Block Diagram
1
<Note>: Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 19.6ms ± 30%
This specification is subject to change without prior notice.
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10.21.2004 (V1.0)
EM78P447N
OTP ROM
4.4 I/O Ports
The I/O registers, Port 5, Port 6, and Port 7, are bi-directional tri-state I/O ports. The functions of
Pull-high, R-option, and Open-drain can be performed internally by CONT and IOCE respectively.
There is input status change wake-up function on Port 6, P74, and P75. Each I/O pin can be defined as
"input" or "output" pin by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control
registers are both readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are
shown in Figures. 7(a) and (b) respectively.
PCRD
Q PR D
Q
PCWR
CLK
CL
IOD
Q PR D
PORT
Q
0
1
PDWR
CLK
CL
M
U
X
PDRD
Fig. 7 (a) The I/O Port and I/O Control Register Circuit
PCRD
VCC
ROC
Q PR D
Weakly
Pull- up
Q
PORT
0
Rex*
1
CLK
PCWR
CL
Q
PR
Q
CL
IOD
D
CLK
M
U
X
PDWR
PDRD
*The Rex is 430K ohm external resistor
Fig.7(b) The I/O Port with R-Option (P70, P71) Circuit
This specification is subject to change without prior notice.
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EM78P447N
OTP ROM
4.5 RESET and Wake-up
1. RESET
A RESET is initiated by one of the following events(1) Power on reset, or
(2) /RESET pin input “low”, or
(3) WDT timeout. (if enabled)
The device is kept in a RESET condition for a period of approx. 18ms1 (one oscillator start-up timer
period) after the reset is detected. Once the RESET occurs, the following functions are performed (refer
to Fig.8).
• The oscillator starts or is running
• The Program Counter (R2) is set to all "1".
• When power is switched on, bits 5~6 of R3 and the upper 2 bits of R4 are cleared.
• All I/O port pins are configured as input mode (high-impedance state).
• The Watchdog timer and prescaler are cleared.
• Upon power on, the bits 5~6 of R3 are cleared.
• Upon power on, the upper 2 bits of R4 are cleared.
• The bits of CONT register are set to all "1" except bit 6 (INT flag).
• IOCB register is set to ”1” (disable P60 ~ P67 wake-up function).
• Bits 3 and 6 of IOCE register are cleared, and Bits 0, 4, and 5 are set to "1".
• Bits 0 and 3 of R3F register and Bits 0 and 3 of IOCF registers are cleared.
The sleep (power down) mode is asserted by executing the “SLEP” instruction. While entering sleep
mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by(1) External reset input on /RESET pin;
(2) WDT time-out (if enabled)
1
NOTE: Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 19.6ms ± 30%
This specification is subject to change without prior notice.
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10.21.2004 (V1.0)
EM78P447N
OTP ROM
The above two cases will cause the controller EM78P447N to reset. The T and P flags of R3 can be
used to determine the source of the reset (wake-up).
In addition to the basic SLEEP1 MODE, EM78P447N has another sleep mode (designated as SLEEP2
MODE and is invoked by clearing the IOCE register “SLPC” bit). In the SLEEP2 MODE, the controller
can be awakened by(A) Any of the wake-up pins is “0” as illustrated in Figure. 5. Upon waking, the controller will continue to
execute the succeeding address. Under this case, before entering SLEEP2 MODE, the wake-up
function of the trigger sources (P60~P67 and P74~P75) should be selected (e.g., input pin) and
enabled (e.g., pull-high, wake-up control). It should be noted that after waking up, the WDT is enabled
if the Code Option bit ENWDT is “0”. The WDT operation (to be enabled or disabled) should be
appropriately controlled by software after waking up.
(B) WDT time-out (if enabled) or external reset input on /RESET pin will trigger a controller reset.
Table 4 Usage of Sleep1 and Sleep2 Mode
Usage of Sleep1 and Sleep2 Mode
SLEEP2
SLEEP1
(a) Before SLEEP
1. Set Port6 or P74 or P75 Input
2. Enable Pull-High and set WDT prescaler over
1:1 (Set CONT.7 and CONT.3 ~ CONT.0)
3. Enable Wake-up (Set IOCB or IOCE.0)
4. Execute Seep2 (Set IOCE.4)
(b) After Wake-up
1. Next instruction
2. Disable Wake-up
3. Disable WDT (Set IOCE.5)
(a) Before SLEEP
1. Execute SLEP instruction
(b) After Wake-up
1. Reset
If Port6 Input Status Changed Wake-up is used to wake-up the EM78P447S (Case [a] above), the
following instructions must be executed before entering SLEEP2 mode:
MOV
IOW
MOV
CONTW
MOV
IOW
MOV
IOW
After Wake-up
NOP
MOV
A, @11111111b ; Set Port6 input
R6
A, @0xxx1010b ; Set Port6 pull-high, WDT prescaler, prescaler must set over 1:1
A, @00000000b ; Enable Port6 wake-up function
RB
A, @xx00xxx1b ; Enable SLEEP2
RE
A, @11111111b ; Disable Port6 wake-up function
This specification is subject to change without prior notice.
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10.21.2004 (V1.0)
EM78P447N
OTP ROM
IOW
MOV
IOW
RB
A, @ xx01xxx1b ; Disable WDT
RE
Note:
After waking up from the SLEEP2 mode, WDT is automatically enabled. The WDT enabled/disabled
operation after waking up from SLEEP2 mode should be appropriately defined in the software.
To avoid reset from occurring when the port6 status changed interrupt enters into interrupt vector or is
used to wake-up the MCU, the WDT prescaler must be set above 1:1 ratio.
Table 4 The Summary of the Initialized Values for Registers
Address
Name
N/A
IOC5
N/A
N/A
N/A
0x00
0x01
0x02
IOC6
IOC7
CONT
R0(IAR)
R1(TCC)
R2(PC)
Reset Type
Bit Name
Type
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Bit 7
C57
A
B
0
1
0
1
Bit 6
C56
A
B
0
1
0
1
Bit 5
C55
A
B
0
1
0
1
Bit 4
C54
A
B
0
1
0
1
0
0
0
0
P
P
P
P
Bit 3
C53
1
1
Bit 2
C52
1
1
Bit 1
C51
1
1
Bit 0
C50
1
1
P
P
P
P
C67
1
1
C66
1
1
C65
1
1
C64
1
1
C63
1
1
C62
1
1
C61
1
1
C60
1
1
P
P
P
P
P
P
P
P
C77
1
1
C76
1
1
C75
1
1
C74
1
1
C73
1
1
C72
1
1
C71
1
1
C70
1
1
P
P
P
P
P
P
P
P
/PHEN
1
1
/INT
0
P
TS
1
1
TE
1
1
PAB
1
1
P
P
P
P
P
P
P
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
P
P
P
P
P
P
P
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
**0/P
**0/P
**0/P
**0/P
**0/P
**0/P
**0/P
**0/P
GP
PS1
PS0
T
P
Z
DC
C
This specification is subject to change without prior notice.
20
PSR2 PSR1 PSR0
1
1
1
1
1
1
10.21.2004 (V1.0)
EM78P447N
OTP ROM
0x03
0x04
0x05
0x06
0x07
0x3F
0x0B
0x0E
0x0F
0x08
R3(SR)
R4(RSR)
R5(P5)
R6(P6)
R7(P7)
R3F(ISR)
IOCB
IOCE
IOCF
R8
0x09~0x3
R9~R3E
E
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
0
0
0
0
0
0
1
t
1
t
U
P
U
P
U
P
P
P
P
t
t
P
P
P
RSR.1
0
0
RSR.0
0
0
U
P
U
P
U
P
U
P
U
P
U
P
P
P
P
P
P
P
P
P
P57
U
P
P56
U
P
P55
U
P
P54
U
P
P53
U
P
P52
U
P
P51
U
P
P50
U
P
P
P
P
P
P
P
P
P
P67
U
P
P66
U
P
P65
U
P
P64
U
P
P63
U
P
P62
U
P
P61
U
P
P60
U
P
P
P
P
P
P
P
P
P
P77
U
P
P76
U
P
P75
U
P
P74
U
P
P73
U
P
P72
U
P
P71
U
P
P70
U
P
P
P
P
P
P
P
P
P
U
U
U
U
U
U
U
U
EXIF
0
0
U
U
U
U
TCIF
0
0
U
U
U
U
P
U
U
P
Bit Name
/WUE7
/WUE6
/WUE5
/WUE4
Power-On
/RESET and WDT
Wake-Up from Pin
Change
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
U
U
ODE
0
0
WDTE
1
1
SLPC
1
1
ROC
0
0
U
U
U
U
/WUE
1
1
U
P
1
1
P
U
U
P
U
U
U
U
U
U
U
U
EXIE
0
0
U
U
U
U
TCIE
0
0
U
U
U
U
P
U
U
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
-
-
-
-
-
-
-
-
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
Wake-Up from Pin
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
This specification is subject to change without prior notice.
21
/WUE /WUE /WUE /WUE
3
2
1
0
1
1
1
1
1
1
1
1
10.21.2004 (V1.0)
EM78P447N
OTP ROM
Change
** To execute next instruction after the ”SLPC” bit status of IOCE register being on high-to-low transition.
X: Not used. U: Unknown or don’t care. P: Previous value before reset. t: Check Table 5
2. The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by one of the following events:
1. A power-on condition,
2. A high-low-high pulse on /RESET pin, and
3. Watchdog timer time-out.
The values of T and P (listed in Table 5 below) are used to verify the event that triggered the processor
to wake up.
Table 6 shows the events that may affect the status of T and P.
Table 5 The Values of RST, T and P after RESET
Reset Type
Power on
/RESET during Operating mode
/RESET wake-up during SLEEP1 mode
/RESET wake-up during SLEEP2 mode
WDT during Operating mode
WDT wake-up during SLEEP1 mode
WDT wake-up during SLEEP2 mode
Wake-Up on pin change during SLEEP2 mode
T
P
1
*P
1
*P
0
0
0
*P
1
*P
0
*P
*P
0
*P
*P
*P: Previous status before reset
Table 6 The Events that may Affect the T and P Status
Event
Power on
WDTC instruction
WDT time-out
SLEP instruction
Wake-Up on pin change during SLEEP2 mode
T
P
1
1
0
1
*P
1
1
*P
0
*P
*P: Previous value before reset
This specification is subject to change without prior notice.
22
10.21.2004 (V1.0)
EM78P447N
OTP ROM
VDD
D
CLK
Oscillator
Q
CLK
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT
WDT Timeout
Setup Time
RESET
/RESET
Fig. 8 Controller Reset Block Diagram
4.6 Interrupt
The EM78P447N has two interrupts listed below:
(1) TCC overflow interrupt
(2) External interrupt (/INT pin).
R3F is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF is
the interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the
DISI instruction. When one of the interrupts (enabled) occurs, the next instruction will be fetched from
address 001H. Once in the interrupt service routine, the source of an interrupt can be determined by
polling the flag bits in R3F. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (R3F) is set regardless of the status of its mask
bit or the execution of ENI. Note that the outcome of R3F are the logic AND of R3F and IOCF (refer to
Fig. 9). The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of
ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction will be fetched from
address 002H.
This specification is subject to change without prior notice.
23
10.21.2004 (V1.0)
EM78P447N
OTP ROM
VCC
D
/IRQn
P
R
CLK
RF
C
L
Q
IRQn
INT
_
Q
IRQm
RFRD
ENI/DISI
Q
IOCF
_
Q
P
R
C
L
IOD
D
CLK
IOCFWR
/RESET
IOCFRD
RFWR
Fig. 9 Interrupt Input Circuit
4.7 Oscillator
1. Oscillator Modes
The EM78P447N can operate in three different oscillator modes, i.e., high XTAL (HXT) oscillator
mode, low XTAL (LXT) oscillator mode, and External RC oscillator mode (ERC) oscillator mode.
User can select one of them by programming MS, HLF and HLP in the Code Option Register. Table
7 depicts how these three modes are defined.
The maximum limit for operational frequencies of crystal/resonator under different VDDs is listed in
Table 8.
Table 7 Oscillator Modes Defined by MS and HLP
Mode
MS
HLF
HLP
0
1
1
*X
1
0
*X
*X
0
ERC(External RC oscillator mode)
HXT(High XTAL oscillator mode)
LXT(Low XTAL oscillator mode)
<Note>
1. X, Don’t care
2. The transient point of system frequency between HXT and LXY is around 400 KHz.
This specification is subject to change without prior notice.
24
10.21.2004 (V1.0)
EM78P447N
OTP ROM
Table 8 The Summary of Maximum Operating Speeds
Conditions
VDD
2.3
3.0
5.0
Two cycles with two clocks
Fxt max.(MHz)
4.0
8.0
20.0
2. Crystal Oscillator/Ceramic Resonators(XTAL)
EM78P447N can be driven by an external clock signal through the OSCI pin as shown in Fig. 10
below.
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator
to generate oscillation. Fig. 12 depicts such circuit. The same thing applies whether it is in the HXT
mode or in the LXT mode. Table 9 provides the recommended values of C1 and C2. Since each
resonator has its own attribute, user should refer to its specification for appropriate values of C1 and
C2. RS. A serial resistor may be necessary for AT strip cut crystal or low frequency mode.
OSCI
Ext. Clock
OSCO
EM 78P447S
Fig. 10 Crystal/Resonator Circuit
C1
OSCI
EM 78P447S
XTAL
OSCO
RS
C2
Fig. 11 Crystal/Resonator Circuit
This specification is subject to change without prior notice.
25
10.21.2004 (V1.0)
EM78P447N
OTP ROM
Table 9 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Frequency Mode
Ceramic Resonators
HXT
LXT
Crystal Oscillator
HXT
Frequency
C1(pF)
C2(pF)
455 kHz
2.0 MHz
4.0 MHz
32.768kHz
100KHz
200KHz
455KHz
1.0MHz
2.0MHz
4.0MHz
100~150
20~40
10~30
25
25
25
20~40
15~30
15
15
100~150
20~40
10~30
15
25
25
20~150
15~30
15
15
3. External RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC oscillator (Fig. 15)
offers a lot of cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator
is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even
by the operation temperature. Moreover, the frequency also changes slightly from one chip to
another due to the manufacturing process variation.
In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF,
and that the value of Rext should not be greater than 1 M ohm. If they cannot be kept in this range,
the frequency is easily affected by noise, humidity, and leakage.
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the contrary, for very
low Rext values, for instance, 1 KΩ, the oscillator becomes unstable because the NMOS cannot
discharge the current of the capacitance correctly.
Based on the above reasons, it must be kept in mind that all of the supply voltage, the operation
temperature, the components of the RC oscillator, the package types, the way the PCB is layout,
will affect the system frequency.
This specification is subject to change without prior notice.
26
10.21.2004 (V1.0)
EM78P447N
OTP ROM
VCC
Rext
OSCI
Cext
EM 78P447S
Fig. 12 External RC Oscillator Mode Circuit
Table 10 RC Oscillator Frequencies
<Note>
Cext
Rext
20 pF
3.3k
5.1k
10k
100k
4.32 MHz
2.83 MHz
1.62MHz
184 KHz
3.56 MHz
2.8 MHz
1.57 MHz
187 KHz
100 pF
3.3k
5.1k
10k
100k
1.39 MHz
950 KHz
500 KHz
54KHz
1.35 MHz
930 KHz
490 KHz
55 KHz
300 pF
3.3k
5.1k
10k
100k
580 KHz
390 KHz
200 KHz
21 KHz
550 KHz
380 KHz
200 KHz
21 KHz
Average Fosc 5V,25°C Average Fosc 3V,25°C
1. Measured on DIP packages.
2. For design reference only.
4.8 CODE Option Register
The EM78P447N has one CODE option word that is not a part of the normal program memory. The
option bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register arrangement distribution:
Word 0
Bit12~Bit0
This specification is subject to change without prior notice.
Word 1
Bit12~Bit0
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10.21.2004 (V1.0)
EM78P447N
OTP ROM
1. Code Option Register (Word 0)
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
-
-
EC
-
CLKS
ENWDTB
Word 0
Bit6
TYPE
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HLF
OSC
HLP
PR2
PR1
PR0
• Bit 12 、11:Not used.
Reserved.
The bit set to “1” all the time.
• Bit 10 (EC): Error recovery Bit.
0: Enable
1: Disable
• Bit 9: Not used.
Reserved.
The bit set to “0” all the time.
• Bit 8 (CLKS): Instruction period option bit.
0: two oscillator periods.
1: four oscillator periods.
Refer to the section on Instruction Set.
• Bit 7(ENWDTB): Watchdog timer enable bit.
0: Enable
1: Disable
• Bit 6: Type selection for EM78P447NA or EM78P447NB
0: EM78P447NB
1: EM78P447NA
• Bit 5 (HLF): XTAL frequency selection
0: XTAL2 type (low frequency, 32.768KHz)
1: XTAL1 type (high frequency)
This bit will affect system oscillation only when Bit4 (OSC) is “1”. When OSC is”0”, HLF must be “0”.
<Note>: The transient point of system frequency between HXT and LXY is around 400 KHz.
This specification is subject to change without prior notice.
28
10.21.2004 (V1.0)
EM78P447N
OTP ROM
• Bit 4 (OSC):Oscillator type selection.
0:RC type
1:XTAL type (XTAL1 and XTAL2)
• Bit 3 (HLP): Power selection.
0: Low power
1: High power
• Bit 2~0 (PR2~PR0): Protect Bit
PR2~PR0 are protect bits, protect type as following
PR2
0
0
0
0
1
1
1
1
PR1
0
0
1
1
0
0
1
1
PR0
0
1
0
1
0
1
0
1
Protect
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Disable
2. Customer ID Register (Word 1)
Word 1
Bit 12~Bit 0
XXXXXXXXXXXXX
• Bit 12~0: Customer’s ID code
4.9 Power On Considerations
Any microcontroller is not guaranteed to start and operate properly before the power supply stays at its
steady state. EM78P447N is equipped with Power On Voltage Detector(POVD) with a detecting level is
2.0V. It will work well if Vdd rises fast enough (10 ms or less). In many critical applications, however,
extra devices are still required to assist in solving power-up problems.
This specification is subject to change without prior notice.
29
10.21.2004 (V1.0)
EM78P447N
OTP ROM
4.10 External Power On Reset Circuit
The circuit shown in Fig.16 implements an external RC to produce the reset pulse. The pulse width
(time constant) should be kept long enough for Vdd to reached minimum operation voltage. This circuit
is used when the power supply has slow rise time. Because the current leakage from the /RESET pin is
about ±5µA, it is recommended that R should not be greater than 40 K. In this way, the /RESET pin
voltage is held below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The
capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent high current or
ESD (electrostatic discharge) from flowing to pin /RESET.
Vdd
R
/RESET
D
EM78P447N
Rin
C
Fig. 13 External Power-Up Reset Circuit
This specification is subject to change without prior notice.
30
10.21.2004 (V1.0)
EM78P447N
OTP ROM
4.11 Residue-Voltage Protection
When battery is replaced, device power (Vdd) is taken off but residue-voltage remains. The
residue-voltage may trips below Vdd minimum, but not to zero. This condition may cause a poor power
on reset. Fig.16 and Fig.17 show how to build the residue-voltage protection circuit.
Vdd
Vdd
33K
EM78P447N
Q1
10K
/RESET
40K
1N4684
Fig. 14 The Residue Voltage Protection Circuit 1
Vdd
Vdd
R1
EM78P447N
Q1
/RESET
R2
40K
Fig. 15 The Residue Voltage Protection Circuit 2
This specification is subject to change without prior notice.
31
10.21.2004 (V1.0)
EM78P447N
OTP ROM
4.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more
operands. Normally, all instructions are executed within one single instruction cycle (one instruction
consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A",
"ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6",
"CLR R2", ⋅⋅⋅⋅). In this case, the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try
modifying the instruction as follows:
(A) Change one instruction cycle to consist of 4 oscillator periods.
(B) Executed within two instruction cycles, "JMP", "CALL", "RET", "RETL", "RETI", or the
conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") instructions which were tested to be
true. Also execute within two instruction cycles, the instructions that are written to the program
counter.
Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle consists of two oscillator
clocks if CLK is low, and four oscillator clocks if CLK is high.
Note that once the 4 oscillator periods within one instruction cycle is selected as in Case (A), the internal
clock source to TCC should be CLK=Fosc/4, not Fosc/ 2 as indicated in Fig. 5.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction can operate
on I/O register.
The symbol "R" represents a register designator that specifies which one of the registers (including
operational registers and general purpose registers) is to be utilized by the instruction. "b" represents a
bit field designator that selects the value for the bit which is located in the register "R", and affects
operation. "k" represents an 8 or 10-bit constant or literal value.
0
0
0
0
0
0
INSTRUCTION
BINARY
0000 0000 0000
0000 0000 0001
0000 0000 0010
0000 0000 0011
0000 0000 0100
0000 0000 rrrr
HEX
MNEMONIC
OPERATION
STATUS AFFECTED
0000
0001
0002
0003
0004
000r
NOP
DAA
CONTW
SLEP
WDTC
IOW R
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
None
C
None
T,P
T,P
None <Note1>
This specification is subject to change without prior notice.
32
10.21.2004 (V1.0)
EM78P447N
OTP ROM
INSTRUCTION
BINARY
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
HEX
MNEMONIC
OPERATION
STATUS AFFECTED
0010
0011
0012
ENI
DISI
RET
None
None
None
0 0000 0001 0011
0013
RETI
0 0000 0001 0100
0 0000 0001 rrrr
0014
001r
CONTR
IOR R
0 0000 0010 0000
0020
TBL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
0 0110 00rr rrrr
06rr
RRCA R
0 0110 01rr rrrr
06rr
RRC R
0 0110 10rr rrrr
06rr
RLCA R
0 0110 11rr rrrr
06rr
RLC R
0 0111 00rr rrrr
07rr
SWAPA R
0
0
0
0
0
0
0
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
1kkk
CALL k
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
CONT → A
IOCR → A
R2+A → R2,
Bits 8~9 of R2 unchanged
A→R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A∨R→A
A∨R→R
A&R→A
A&R→R
A⊕R→A
A⊕R→R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP],
(Page, k) → PC
0000
0000
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
0111
0111
0111
100b
101b
110b
111b
01rr
1000
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
01rr
10rr
11rr
bbrr
bbrr
bbrr
bbrr
rrrr
0000
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
1 00kk kkkk kkkk
This specification is subject to change without prior notice.
33
None
None
None <Note1>
Z,C,DC
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
None
C
C
C
C
None
None
None
None
None <Note2>
None <Note3>
None
None
None
10.21.2004 (V1.0)
EM78P447N
OTP ROM
1
1
1
1
1
1
1
1
1
INSTRUCTION
BINARY
01kk kkkk kkkk
1000 kkkk kkkk
1001 kkkk kkkk
1010 kkkk kkkk
1011 kkkk kkkk
1100 kkkk kkkk
1101 kkkk kkkk
1110 0000 0010
1111 kkkk kkkk
HEX
MNEMONIC
OPERATION
STATUS AFFECTED
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1E02
1Fkk
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
INT
ADD A,k
(Page, k) → PC
k→A
A∨k→A
A&k→A
A⊕k→A
k → A, [Top of Stack] → PC
k-A → A
PC+1 → [SP], 002H → PC
k+A → A
None
None
Z
Z
Z
None
Z,C,DC
None
Z,C,DC
<Note1> This instruction is applicable to IOC5 ~ IOC7, IOCB, IOCE, IOCF only.
<Note2> This instruction is not recommended for R3F operation.
<Note3> This instruction cannot operate under R3F.
This specification is subject to change without prior notice.
34
10.21.2004 (V1.0)
EM78P447N
OTP ROM
4.13 Timing Diagram
AC Test Input/O utput W aveform
2.4
2.0
0.8
TE S T P O IN T S
2.0
0.8
0.4
AC T estin g : In p u t is d riven at 2.4V fo r lo g ic "1",an d 0.4V fo r lo g ic "0".T im in g m easu rem en ts are
m ad e at 2.0V fo r lo g ic "1",an d 0.8V fo r lo g ic "0".
R E S E T Tim ing (C LK ="0")
NOP
In struction 1
E xecu ted
CLK
/R ES ET
T d rh
TC C Input Tim ing (C LK S ="0")
T in s
CLK
TCC
T tcc
This specification is subject to change without prior notice.
35
10.21.2004 (V1.0)
EM78P447N
OTP ROM
5. ABSOLUTE MAXIMUM RATINGS
Items
Temperature under bias
Storage temperature
Input voltage
Output voltage
Operating Frequency (2clk)
Operating Voltage
-40°C
-65°C
VSS-0.3V
VSS-0.3V
32.768KHz
2.5V
This specification is subject to change without prior notice.
36
Rating
to
to
to
to
to
to
85°C
150°C
VDD+0.5V
VDD+0.5V
20MHz
5.5V
10.21.2004 (V1.0)
EM78P447N
OTP ROM
6. DC ELECTRICAL CHARACTERISTICS
6.1 DC Electrical Characteristic
(Ta= 25 °C, VDD= 5.0V±5%, VSS= 0V )
Symbol
FXT
ERC
IIL
VIH1
VIL1
VIHT1
VILT1
VIHX1
VILX1
VIH2
VIL2
VIHT2
VILT2
VIHX2
VILX2
VOH1
VOL1
VOL2
IPH
ISB1
ISB2
ICC1
ICC2
ICC3
ICC4
Parameter
Condition
Min
XTAL: VDD to 3V
Two cycle with two clocks
DC
XTAL: VDD to 5V
Two cycle with two clocks
DC
ERC: VDD to 5V
R: 5.1KΩ, C: 100 pF
F±30%
Input Leakage Current for input pins
VIN = VDD, VSS
Input High Voltage (VDD=5V)
Ports 5, 6,7
2.0
Input Low Voltage (VDD=5V)
Ports 5, 6,7
Input High Threshold Voltage
/RESET, TCC,INT
2.0
(VDD=5V)
Input Low Threshold Voltage
/RESET, TCC,INT
(VDD=5V)
Clock Input High Voltage (VDD=5V)
OSCI
3.5
Clock Input Low Voltage (VDD=5V)
OSCI
Input High Voltage (VDD=3V)
Ports 5, 6,7
1.5
Input Low Voltage (VDD=3V)
Ports 5, 6,7
Input High Threshold Voltage
/RESET, TCC,INT
1.5
(VDD=3V)
Input Low Threshold Voltage
/RESET, TCC,INT
(VDD=3V)
Clock Input High Voltage (VDD=3V)
OSCI
2.1
Clock Input Low Voltage (VDD=3V)
OSCI
Output High Voltage
IOH = -10.0 mA
2.4
(Ports 5, 6, 7)
Output Low Voltage
IOL = 9.0 mA
(Ports 5, 6)
Output Low Voltage
IOL = 14.0 mA
(Port7)
Pull-high current
Pull-high active, input pin at VSS
-50
All input and I/O pins at VDD,
Power down current
output pin floating, WDT disabled
All input and I/O pins at VDD,
Power down current
output pin floating, WDT enabled
Operating supply current
/RESET= 'High', Fosc=32KHz
(VDD=3V)
(Crystal type,CLKS="0"), output
at two cycles/four clocks
pin floating, WDT disabled
Operating supply current
/RESET= 'High', Fosc=32KHz
(VDD=3V)
(Crystal type,CLKS="0"), output
at two cycles/four clocks
pin floating, WDT enabled
Operating supply current
/RESET= 'High', Fosc=4MHz
(VDD=5V)
(Crystal type, CLKS="0"), output
at two cycles/two clocks
pin floating, WDT enabled
Operating supply current
/RESET= 'High', Fosc=10MHz
(VDD=5V)
(Crystal type, CLKS="0"), output
at two cycles/four clocks
pin floating, WDT enabled
This specification is subject to change without prior notice.
37
Typ.
950
Max
8.0
20.0
F±30%
±1
0.8
Unit
MHz
MHz
KHz
µA
V
V
V
0.8
1.5
0.4
V
V
V
V
V
V
0.4
V
0.9
V
V
V
0.4
V
0.4
V
-240
µA
1
µA
7
µA
25
30
µA
30
35
µA
1.6
2.2
mA
2.8
5.0
mA
-100
10.21.2004 (V1.0)
EM78P447N
OTP ROM
6.2 AC Electrical Characteristic
(Ta=- -40°C ~ 85 °C, VDD=5V±5%, VSS=0V)
Symbol
Parameter
Dclk
Input CLK duty cycle
Tins
Instruction cycle time
(CLKS="0")
Conditions
Min
Typ
45
50
55
%
Crystal type
100
60000
ns
RC type
500
100000
ns
16.2
21.6
ms
16.2
21.6
ms
Ttcc
TCC input period
Tdrh
Device reset hold time
Ta = 25°C
11.3
(Tins+20)/N*
Trst
/RESET pulse width
Ta = 25°C
2000
Twdt
Watchdog timer period
Ta = 25°C
11.3
Tset
Input pin setup time
Thold
Input pin hold time
Tdelay
Output pin delay time
Max
ns
ns
0
Cload=20pF
Unit
ns
15
20
25
ns
45
50
55
ns
Tiod
I/O delay for EMI enable
Cload=150pF
4
5
6
ns
Ttrr1
Rising time for EMI enable
Cload=150pF
190
200
210
ns
Ttrf1
Falling time for EMI enable
Cload=150pF
190
200
210
ns
Ttrr2
Rising time for EMI enable
Cload=300pF
380
400
420
ns
Ttrf2
Falling time for EMI enable
Cload=300pF
380
400
420
ns
Tdrc
ERC delay time
Ta = 25°C
1
3
5
ns
*Data in Typ. is measured at 5V ,25°C
* N= selected prescaler ratio.
This specification is subject to change without prior notice.
38
10.21.2004 (V1.0)
EM78P447N
OTP ROM
6.3 Device characteristic
The graphic provided in the following pages were derived based on a limited number of samples and
are shown here for reference only. The device characteristic illustrated herein are not guaranteed for it
accuracy. In some graphic, the data maybe out of the specified warranted operating range.
Vih/Vil (Input pins with schmitt inverter)
2
Vih max(-40℃ to 85℃ )
Vih typ 25℃
Vih Vil(Volt)
1.5
Vih min(-40℃ to 85℃)
1
Vil max(-40℃ to 85℃ )
Vil typ 25℃
0.5
Vil min(-40℃ to 85℃)
0
2.5
3
3.5
4
Vdd(Volt)
4.5
5
5.5
Fig. 16 Vih, Vil of TCC, /INT, /RESET Pin
This specification is subject to change without prior notice.
39
10.21.2004 (V1.0)
EM78P447N
OTP ROM
Vth (Input thershold voltage) of I/O pins
2
1.8
Typ 25 ℃
1.6
Vth(Volt)
1.4
Max (-40 ℃ to 85 ℃)
1.2
Min (-40 ℃ to 85 ℃)
1
0.8
0.6
0.4
0.2
0
2.5
3
3.5
4
VDD(Volt)
4.5
5
5.5
Fig. 17 Vth（Threshold Voltage）of P60~P67, P70~P77 VS. VDD
This specification is subject to change without prior notice.
40
10.21.2004 (V1.0)
EM78P447N
OTP ROM
Voh/Ioh (VDD=5V)
Voh/Ioh (VDD=3V)
-5
-2
-10
-4
Ioh(mA)
0
Ioh(mA)
0
Min 85 ℃
Min 85 ℃
-6
-15
Typ 25 ℃
Typ 25 ℃
-8
-20
Max -40 ℃
Max -40 ℃
-10
-25
0
1
2
3
4
0
5
0.5
1
1.5
2
2.5
3
Voh(Volt)
Voh(Volt)
Fig.18 Port5, Port6, and Port7 Voh vs.
Fig.19 Port5, Port6, and Port7 Voh vs. Ioh,
Ioh,VDD=5V
VDD=3V
This specification is subject to change without prior notice.
41
10.21.2004 (V1.0)
EM78P447N
OTP ROM
Vol/Iol (VDD=5V)
Vol/Iol (VDD=3V)
90
40
80
35
Max -40 ℃
70
30
60
Typ 25 ℃
25
50
Iol(mA)
Iol(mA)
Max -40 ℃
Min 85 ℃
40
Typ 25 ℃
20
Min 85 ℃
15
30
10
20
10
5
0
0
0
1
2
3
4
5
0
6
Vol(Volt)
1
1.5
2
2.5
3
Vol(Volt)
Fig. 20 Port5, and Port6 Vol vs, Iol, VDD=5V
This specification is subject to change without prior notice.
0.5
Fig. 21 Port5, and Port6 Vol vs. Iol, VDD=3V
42
10.21.2004 (V1.0)
EM78P447N
OTP ROM
Vol/Iol (5V)
Vol/Iol (3V)
45
100
90
40
Max -40 ℃
Max -40 ℃
80
35
70
Typ 25 ℃
Iol(mA)
60
Iol(mA)
30
Typ 25 ℃
50
Min 85 ℃
40
25
20
Min 85 ℃
15
30
10
20
10
5
0
0
0
1
2
3
4
5
0
6
1
1.5
2
2.5
3
Vol(Volt)
Vol(Volt)
Fig. 22 Port7 Vol vs. Iol, VDD=5V
This specification is subject to change without prior notice.
0.5
Fig. 23 Port7 Vol vs. Iol, VDD=3V
43
10.21.2004 (V1.0)
EM78P447N
OTP ROM
WDT Time_out
35
30
WDT period (mS)
25
Max 85 ℃
20
Max 75 ℃
Typ 25 ℃
15
Min 0 ℃
Min -40 ℃
10
5
0
2
3
4
5
VDD (Volt)
6
Fig. 24 WDT Time Out Period vs. VDD, Prescaler Set to 1 : 1
This specification is subject to change without prior notice.
44
10.21.2004 (V1.0)
EM78P447N
OTP ROM
Cext=100pF, Typical RC OSC Frequency
1.4
R=3.3k
Frequency(M Hz)
1.2
1
R=5.1k
0.8
0.6
R=10k
0.4
0.2
R=100k
0
2.5
3
3.5
4
4.5
VDD(Volt)
5
5.5
Fig. 25 Typical RC OSC Frequency vs. VDD （Cext=100pF, Temperature at 25 ℃）
ERC OSC Frequency vs Temp.(Cext=100pF, Rext=5.1K)
1.005
Fosc/Fosc(25℃)
1
0.995
3V
0.99
5V
0.985
0.98
-40
-20
0
20
40
60
80
Temperature(℃)
Fig. 26 Typical RC OSC Frequency vs. Temperature（R and C are ideal component）
This specification is subject to change without prior notice.
45
10.21.2004 (V1.0)
EM78P447N
OTP ROM
Four conditions exist with the operating current ICC1 to ICC4. these conditions are as follows：
ICC1：VDD=3V, Fosc=32 kHz, 2clock, WDT disable.
ICC2：VDD=3V, Fosc=32 kHz, 2clock, WDT enable.
ICC3：VDD=5V, Fosc=4 MHz, 2clock, WDT enable.
ICC4：VDD=5V, Fosc=10 MHz, 2clock, WDT enable.
Typical ICC1 and ICC2 vs. Temperature
Current (uA)
21
18
Typ ICC2
15
Typ ICC1
12
9
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 27 Typical Operating Current（ICC1 and ICC2） vs. Temperature
Maximum ICC1 and ICC2 vs. Temperature
Current (uA)
27
Max ICC2
24
Max ICC1
21
18
15
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 28 Maximum Operating Current（ICC1 and ICC2） vs. Temperature
This specification is subject to change without prior notice.
46
10.21.2004 (V1.0)
EM78P447N
OTP ROM
Current (mA)
Typical ICC3 and ICC4 vs. Temperature
4
3.5
3
2.5
2
1.5
1
0.5
Typ ICC4
Typ ICC3
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 29 Typical Operating Current（ICC3 and ICC4） vs. Temperature
Maximum ICC3 and ICC4 vs. Temperature
4.5
Current (mA)
4
Max ICC4
3.5
3
Max ICC3
2.5
2
1.5
1
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 30 Maximum Operating Current（ICC3 and ICC4） vs. Temperature
This specification is subject to change without prior notice.
47
10.21.2004 (V1.0)
EM78P447N
OTP ROM
Two conditions exist with the standby current ISB1 and ISB2. these conditions are as follow：
ISB1：VDD=5V, WDT disable
ISB2：VDD=5V, WDT enable
Typical ISB1 and ISB2 vs. Temperature
Current (uA)
12
9
Typ ISB2
6
3
Typ ISB1
0
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 31 Typical Standby Current（ISB1 and ISB2） vs. Temperature
Maximum ISB1 and ISB2 vs. Temperature
15
Current (uA)
12
Max ISB2
9
6
3
Max ISB1
0
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 32 Maximum Standby Current（ISB1 and ISB2） vs. Temperature
This specification is subject to change without prior notice.
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EM78P447N
OTP ROM
Operating voltage (-40℃~85℃)
Frequency (M Hz)
25
20
15
10
5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (Volt)
Fig. 33 Operating Voltage In Temperature Range from -40 ℃ to 85 ℃
This specification is subject to change without prior notice.
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EM78P447N
OTP ROM
EM78P447N HXT I-V
3
2.5
I(mA)
2
1.5
Max
1
Min
0.5
0
0
1
2
3
4
5
6
Volt(V)
Fig. 34 EM78P447N I-V Curve Operating at 4 MHz
EM78P447N LXT I-V
40
35
30
I(uA)
25
Max
20
15
Min
10
5
0
0
1
2
3
4
5
6
Volt(V)
Fig. 35 EM78P447N I-V Curve Operating at 32.768 kHz
This specification is subject to change without prior notice.
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EM78P447N
OTP ROM
APPENDIX
Package Types:
OTP MCU
EM78P447NAP
EM78P447NAM
EM78P447NAS
EM78P447NBP
EM78P447NBWM
Package Type
DIP
SOP
SSOP
DIP
SOP
This specification is subject to change without prior notice.
Pin Count
28
28
28
32
32
51
Package Size
600 mil
300 mil
209 mil
600 mil
450 mil
10.21.2004 (V1.0)
EM78P447N
OTP ROM
Package Information
28-Lead plastic dual inline package（DIP）－ 600 mil
This specification is subject to change without prior notice.
52
10.21.2004 (V1.0)
EM78P447N
OTP ROM
32-Lead plastic dual inline package（DIP）－ 600 mil
This specification is subject to change without prior notice.
53
10.21.2004 (V1.0)
EM78P447N
OTP ROM
28-Lead plastic small outline package（SOP）－ 300 mil
This specification is subject to change without prior notice.
54
10.21.2004 (V1.0)
EM78P447N
OTP ROM
32-Lead plastic small outline package（SOP）－ 300 mil
This specification is subject to change without prior notice.
55
10.21.2004 (V1.0)
EM78P447N
OTP ROM
28-Lead Shrink Small Outline Package（SSOP）－ 209 mil
This specification is subject to change without prior notice.
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10.21.2004 (V1.0)
EM78P447N
OTP ROM
ELAN (HEADQUARTER) MICROELECTRONICS CORP., LTD.
Address : No. 12, Innovation 1st. Rd. Science-Based Industrial Park, Hsinchu City, Taiwan.
Telephone: 886-3-5639977
Facsimile : 886-3-5639966
ELAN (H.K.) MICROELECTRONICS CORP., LTD.
Address : Rm. 1005B, 10/F, Empire Centre, 68 Mody Road, Tsimshatsui, Kowloon, Hong Kong.
Telephone: 852-27233376
Facsimile : 852-27237780
E-mail : [email protected]
ELAN MICROELECTRONICS SHENZHEN, LTD.
Address : SSMEC Bldg. 3F , Gaoxin S. Ave. 1st , South Area , Shenzhen High-tech Industrial Park., Shenzhen
Telephone: 86-755-26010565
Facsimile : 86-755-26010500
ELAN MICROELECTRONICS SHANGHAI, LTD.
Address : #23 Building No.115 Lane 572 BiBo Road. Zhangjiang, Hi-tech Park, Shanghai
Telephone: 86-21-50803866
Facsimile : 86-21-50804600
Elan Information Technology Group.
Address: 1821 Saratoga Avenue, suite 250, Saratoga, CA 95070, USA
Telephone: 1-408-366-8225
Facsimile : 1-408-366-8220
Elan Microelectronics Corp. (Europe)
Address: Dubendorfstrasse 4, 8051 Zurich, Switzerland
Telephone: 41-43-2994060
Facsimile : 41-43-2994079
Email : [email protected]
Web-Site : www.elan-europe.com
Copyright © 2004 ELAN Microelectronics Corp. All rights reserved.
ELAN owns the intellectual property rights, concepts, ideas, inventions, know-how (whether patentable
or not) related to the Information and Technology (herein after referred as " Information and
Technology") mentioned above, and all its related industrial property rights throughout the world, as now
may exist or to be created in the future. ELAN represents no warranty for the use of the specifications
described, either expressed or implied, including, but not limited, to the implied warranties of
merchantability and fitness for particular purposes. The entire risk as to the quality and performance of
the application is with the user. In no even shall ELAN be liable for any loss or damage to revenues,
profits or goodwill or other special, incidental, indirect and consequential damages of any kind, resulting
from the performance or failure to perform, including without limitation any interruption of business,
whatever resulting from breach of contract or breach of warranty, even if ELAN has been advised of the
possibility of such damages.
The specifications of the Product and its applied technology will be updated or changed time by time. All
the information and explanations of the Products in this website is only for your reference. The actual
specifications and applied technology will be based on each confirmed order.
ELAN reserves the right to modify the information without prior notification. The most up-to-day
information is available on the website http://www.emc.com.tw.
This specification is subject to change without prior notice.
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10.21.2004 (V1.0)