ST16C2550 DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFOS DESCRIPTION The ST16C2550 (2550) is a dual universal asynchronous receiver and transmitter (UART). The ST16C2550 is an improved version of the NS16C550 UART with higher operating speed and lower access time. The 2550 provides enhanced UART functions with 16 byte FIFOs, a modem control interface, and data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by external software to meet specific user requirements. An internal loopback capability allows onboard diagnostics. Independent programmable baud rate generators are provided to select transmit and receive clock rates from 50 Bps to 1.5 Mbps. The Baud rate generator can be configured for either crystal or external clock input. The 2550 is available in a 40-pin plastic-DIP, 44-pin PLCC, and 48-pin TQFP packages. The 40 pin package does not offer TXRDY and RXRDY pins (DMA Signal monitoring). Otherwise the three package versions are the same. The 2550 is functionally compatible with the 16C2450. The 2550 is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements. FEATURES D4 D3 D2 D1 D0 -TXRDYA VCC -RIA -CDA -DSRA -CTSA 5 4 3 2 1 44 43 42 41 40 D5 7 39 RESET D6 8 38 -DTRB D7 9 37 -DTRA RXB 10 36 -RTSA RXA 11 35 -OPA -TXRDYB 12 34 -RXRDYA TXA 13 33 INTA ST16C2550CJ44 A2 -CTSB 28 29 -RTSB 27 17 -RIB 26 A1 -CSB -IOR 24 30 -DSRB 25 16 -RXRDYB 23 A0 -CSA GND 22 INTB 31 -CDB 21 32 15 -IOW 20 14 XTAL2 19 TXB -OPB XTAL1 18 • Pin and functionally compatible to ST16C2450/ Software compatible with INS8250, NS16C550 • 1.5Mbps transmit/receive operation (24MHz Max.) • 16 byte transmit FIFO to reduce the bandwidth requirement of the external CPU. • 16 byte receive FIFO with error flags to reduce the bandwidth requirement of the external CPU. • Independent transmit and receive UART control • Four selectable Receive FIFO interrupt trigger levels • Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD, and Software controllable line break) • Programmable character lengths (5, 6, 7, 8) with Even, odd, or no parity • Status report register • Crystal or external clock input • 460.8 Kbps transmit/receive operation with 7.3728 MHz crystal or external clock source • TTL compatible inputs, outputs 6 PLCC Package ORDERING INFORMATION Part number Pins Package ST16C2550CP40 40 ST16C2550CJ44 44 ST16C2550CQ48 48 PDIP PLCC TQFP Operating temperature 0° C to + 70° C 0° C to + 70° C 0° C to + 70° C Part number ST16C2550IP40 ST16C2550IJ44 ST16C2550IQ48 Pins Package 40 44 48 PDIP PLCC TQFP Operating temperature -40° C to + 85° C -40° C to + 85° C -40° C to + 85° C Rev. 3.20 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 ST16C2550 Figure 1, Package Descriptions, 40 pin, 48 pin ST16C2550 D4 D3 D2 D1 D0 -TXRDYA VCC -RIA -CDA -DSRA -CTSA N.C. 48 47 46 45 44 43 42 41 40 39 38 37 48 Pin TQFP Package 40 Pin DIP Package D0 1 40 VCC 1 36 RESET D1 2 39 -RIA D6 2 35 -DTRB D2 3 38 -CDA D7 3 34 -DTRA D3 4 37 -DSRA RXB 4 33 -RTSA RXA 5 32 -OPA D4 5 36 -CTSA -TXRDYB 6 31 -RXRDYA D5 6 35 RESET TXA 7 30 INTA D6 7 34 -DTRB TXB 8 29 INTB D7 8 33 -DTRA -OPB 9 28 A0 32 -RTSA -CSA 10 27 A1 11 26 A2 -OPA -CSB 31 N.C. 12 25 N.C. 30 INTA 29 INTB 13 14 15 16 17 18 19 20 21 22 23 24 XTAL1 XTAL2 -IOW -CDB GND -RXRDYB -IOR -DSRB -RIB -RTSB -CTSB N.C. ST16C2550CQ48 Rev. 3.20 2 ST16C2550CP40 D5 RXB 9 RXA 10 TXA 11 TXB 12 -OPB 13 28 A0 -CSA 14 27 A1 -CSB 15 26 A2 XTAL1 16 25 -CTSB XTAL2 17 24 -RTSB -IOW 18 23 -RIB -CDB 19 22 -DSRB GND 20 21 -IOR ST16C2550 Inter Connect Bus Lines & Control signals Transmit FIFO Registers Transmit Shift Register TX A/B Receive FIFO Registers Receive Shift Register RX A/B Rev. 3.20 3 XTAL2 Clock & Baud Rate Generator XTAL1 INTA INTB -TXRDY -RXRDY Register Select Logic A0-A2 -CSA -CSB Interrupt Control Logic D0-D7 -IOR -IOW RESET Data bus & Control Logic Figure 2, Block Diagram Modem Control Logic -DTR A/B -RTS A/B -OP A/B -CTS A/B -RI A/B -CD A/B -DSR A/B ST16C2550 SYMBOL DESCRIPTION Symbol 40 Pin 44 48 Signal type A0 28 31 28 I Address-0 Select Bit. - Internal register address selection. A1 27 30 27 I Address-1 Select Bit. - Internal register address selection. A2 26 29 26 I Address-2 Select Bit. - Internal register address selection. 14,15 16,17 10,11 I Chip Select A, B (active low) - This function is associated with individual channels, A through B. These pins enable data transfers between the user CPU and the 2550 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a logic 0 on the respective -CS AB pin. D0-D7 1-8 2-9 44-48 1-3 I/O GND 20 22 17 Pwr 30,29 33,32 30,29 O Interrupt A, B (three state) - This function is associated with individual channel interrupts, INT A-B. INT A-B are enabled when MCR bit-3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. -IOR 21 24 19 I Read strobe. (active low Strobe) - A logic 0 transition on this pin will load the contents of an Internal register defined by address bits A0-A2 onto the 2550 data bus (D0-D7) for access by an external CPU. -IOW 18 20 15 I Write strobe. (active low strobe) - A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2. 31,13 35,15 32,9 O Output -2 (User Defined). - This function is associated with -CS A-B INT A-B -OP2 A-B Pin Description Data Bus (Bi-directional) - These pins are the eight bit, three state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Signal and power ground. Rev. 3.20 4 ST16C2550 SYMBOL DESCRIPTION Symbol 40 Pin 44 48 Signal type Pin Description individual channels, A through B. The state at these pin(s) are defined by the user and through the software setting of MCR register bit-3. INT A-B are set to the active mode and OP2 to a logic 0 when MCR-3 is set to a logic 1. INT A-B are set to the three state mode and OP2 to a logic 1 when MCR3 is set to a logic 0. See bit-3, Modem Control Register (MCR bit-3). RESET 35 39 36 I Reset. (active high) - A logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See ST16C2550 External Reset Conditions for initialization details.) -RXRDY A-B - 34,23 31,18 O Receive Ready A-B (active low) - This function is associated with 44 pin PLCC and 48 pin TQFP packages only. This function provides the RX FIFO/RHR status for individual receive channels (A-B). RXRDY is primarily intended for monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0 indicates there is receive data to read/ unload, i.e., receive ready status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed trigger level has not been reached. This signal can also be used for single mode transfers (DMA mode 0). -TXRDY A-B - 1,12 43,6 O Transmit Ready A-B (active low) - This function is associated with 44 pin PLCC and 48 pin TQFP packages only. These outputs provide the TX FIFO/THR status for individual transmit channels (A-B). TXRDY is primarily intended for monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual channels -TXRDY A-B buffer ready status is indicated by logic 0, i.e., at least one location is empty and available in the FIFO or THR. This pin goes to a logic 1 when there are no more empty locations in the FIFO or THR. This signal can also be used for single mode transfers (DMA mode 0). 40 44 42 Pwr VCC Power supply input. Rev. 3.20 5 ST16C2550 SYMBOL DESCRIPTION Symbol 40 Pin 44 48 Signal type Pin Description XTAL1 16 18 13 I Crystal or External Clock Input - Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit. This configuration requires an external 1 MW resistor between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to this pin to provide custom data rates (see Baud Rate Generator Programming). XTAL2 17 19 14 O Output of the Crystal Oscillator or Buffered Clock - (See also XTAL1). Crystal oscillator output or buffered clock output. Should be left open if an external clock is connected to XTAL1. -CD A-B 38,19 42,21 40,16 I Carrier Detect (active low) - These inputs are associated with individual UART channels A through B. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. -CTS A-B 36,25 40,28 38,23 I Clear to Send (active low) - These inputs are associated with individual UART channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the 2550. Status can be tested by reading MSR bit-4. This pin has no effect on the UARTs transmit or receive operation. -DSR A-B 37,22 41,25 39,20 I Data Set Ready (active low) - These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UARTs transmit or receive operation. -DTR A-B 33,34 37,38 34,35 O Data Terminal Ready (active low) - These outputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates that the 2550 is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR bit-0 will set the -DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR bit-0, or after a reset. This Rev. 3.20 6 ST16C2550 SYMBOL DESCRIPTION Symbol 40 Pin 44 48 Signal type Pin Description pin has no effect on the UARTs transmit or receive operation. -RI A-B 39,23 43,26 41,21 I Ring Indicator (active low) - These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt. -RTS A-B 32,24 36,27 33,22 O Request to Send (active low) - These outputs are associated with individual UART channels, A through B. A logic 0 on the -RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register (MCR bit-1) will set this pin to a logic 0 indicating data is available. After a reset this pin will be set to a logic 1. This pin has no effect on the UARTs transmit or receive operation. RX A-B 10,9 11,10 5,4 I Receive Data (A-B) - These inputs are associated with individual serial channel data to the 2550 receive input circuits, A-B. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the RX input pin is disabled and TX data is connected to the UART RX Input, internally. TX A-B 11,12 13,14 7,8 O Transmit Data (A-B) - These outputs are associated with individual serial transmit channel data from the 2550. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX Input. Rev. 3.20 7 ST16C2550 GENERAL DESCRIPTION The 2550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The 2550 represents such an integration with greatly enhanced features. The 2550 is fabricated with an advanced CMOS process. The 2550 is capable of operation to 1.5Mbps with a 24 MHz. With a crystal or external clock input of 7.3728 MHz the user can select data rates up to 460.8 Kbps. The rich feature set of the 2550 is available through internal registers. Selectable receive FIFO trigger levels, selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power on reset or an external reset, the 2550 is software compatible with the previous generation, ST16C2450. FUNCTIONAL DESCRIPTIONS UART A-B Functions The UART provides the user with the capability to Bidirectionally transfer information between an external CPU, the 2550 package, and an external serial device. A logic 0 on chip select pins -CSA and/or -CSB allows the user to configure, send data, and/or receive data via UART channels A-B. Individual channel select functions are shown in Table 2 below. The 2550 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The 2550 is designed to work with high speed modems and shared network environments, that require fast data processing time. Increased performance is realized in the 2550 by the transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in 93 microseconds (This example uses a character length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO less than every 100 microseconds. However with the 16 byte FIFO in the 2550, the data buffer will not require unloading/loading for 1.53 ms. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the 4 selectable receive FIFO trigger interrupt levels is uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. Table 2, SERIAL PORT SELECTION GUIDE CHIP SELECT Function -CS A-B = 1s -CS A = 0 -CS B = 0 None UART CHANNEL A UART CHANNEL B Internal Registers The 2550 provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These resisters are shown in Table 3 below. The UART registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user assessable scratchpad register (SPR). Rev. 3.20 8 ST16C2550 Table 3, INTERNAL REGISTER DECODE A2 A1 A0 READ MODE WRITE MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note 1* 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Receive Holding Register Interrupt Status Register Line Status Register Modem Status Register Scratchpad Register Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register Scratchpad Register Baud Rate Register Set (DLL/DLM): Note *2 0 0 0 0 0 1 LSB of Divisor Latch MSB of Divisor Latch LSB of Divisor Latch MSB of Divisor Latch Note 1* The General Register set is accessible only when CS A/B is a logic 0. Note 2* The Baud Rate register set is accessible only when CS A/B is a logic 0 and LCR bit-7 is a logic 1. FIFO Operation register is empty. This interrupt must be serviced prior to continuing operations. The LSR register provides the current singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition can exist where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt will the lower priority CTS/ RTS interrupt(s) be reflected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors. The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit-0. The user can set the receive trigger level via FCR bits 67 but not the transmit trigger level. The transmit interrupt trigger level is set to 16 following a reset. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER bit-3). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case the 2550 FIFO may hold more characters than the programmed trigger level. Follow- Hardware/Software and Time-out Interrupts The interrupts are enabled by IER bits 0-3. Care must be taken when handling these interrupts. Following a reset the transmitter interrupt is enabled, the 2550 will issue an interrupt to indicate that transmit holding Rev. 3.20 9 ST16C2550 ing the removal of a data byte, the user should recheck LSR bit-0 for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time out counter is reset at the center of each stop bit received or each time the receive holding register (RHR) is read.. The actual time out value is T (Time out length in bits) = 4 X P (Programmed word length) + 12. To convert the time out value to a character value, the user has to consider the complete word length, including data information length, start bit, parity bit, and the size of stop bit, i.e., 1X, 1.5X, or 2X bit times. allel resonant/ 22-33 pF load) is connected externally between the XTAL1 and XTAL2 pins, with an external 1 MΩ resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. (see Baud Rate Generator Programming). The generator divides the input 16X clock by any divisor from 1 to 216 -1. The 2550 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard and custom applications using the same system design. The rate table is configured via the DLL and DLM internal register functions. Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Example -A: If the user programs a word length of 7, with no parity and one stop bit, the time out will be: T = 4 X 7( programmed word length) +12 = 40 bit times. The character time will be equal to 40 / 9 = 4.4 characters, or as shown in the fully worked out example: T = [(programmed word length = 7) + (stop bit = 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4 characters. Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 4 below, shows the selectable baud rate table available when using a 1.8432 MHz external clock input. Example -B: If the user programs the word length = 7, with parity and one stop bit, the time out will be: T = 4 X 7(programmed word length) + 12 = 40 bit times. Character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 characters. Crystal oscillator connection XTAL1 The 2550 supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example a 33.6Kbps modem that employs data compression may require a 115.2Kbps input data rate. A 128.0Kbps ISDN modem that supports data compression may need an input data rate of 460.8Kbps. The 2550 can support a standard data rate of 921.6Kbps. XTAL2 Programmable Baud Rate Generator R1 50-120 R2 1M X1 Single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock up to 24 MHz, as required for supporting a 1.5Mbps data rate. The 2550 can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal (par- 1.8432 MHz C1 22pF Rev. 3.20 10 C2 33pF ST16C2550 Table 4, BAUD RATE GENERATOR PROGRAMMING TABLE (1.8432 MHz CLOCK): Output Baud Rate Output 16 x Clock Divisor (Decimal) User 16 x Clock Divisor (HEX) DLM Program Value (HEX) DLL Program Value (HEX) 50 75 110 150 300 600 1200 2400 3600 4800 7200 9600 19.2k 38.4k 57.6k 115.2k 2304 1536 1047 768 384 192 96 48 32 24 16 12 6 3 2 1 900 600 417 300 180 C0 60 30 20 18 10 0C 06 03 02 01 09 06 04 03 01 00 00 00 00 00 00 00 00 00 00 00 00 00 17 00 80 C0 60 30 20 18 10 0C 06 03 02 01 Rev. 3.20 11 ST16C2550 DMA Operation the UART TX/RX circuits. The 2550 FIFO trigger level provides additional flexibility to the user for block mode operation. LSR bits 56 provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR bit-3). When the transmit and receive FIFOs are enabled and the DMA mode is deactivated (DMA Mode 0), the 2550 activates the interrupt output pin for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the receive trigger level and the transmit FIFO. In this mode, the 2550 sets the interrupt output pin when characters in the transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger level. In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using lower four bits of the Modem Control Register (MCR bits 0-3) instead of the four Modem Status Register bits 4-7. The interrupts are still controlled by the IER. Loop-back Mode The internal loop-back capability allows onboard diagnostics. In the loop-back mode the normal modem interface pins are disconnected and reconfigured for loop-back internally. MCR register bits 0-3 are used for controlling loop-back diagnostic testing. In the loop-back mode INT enable and MCR bit-2 in the MCR register (bits 3/2) control the modem -RI and -CD inputs respectively. MCR signals -DTR and -RTS (bits 0-1) are used to control the modem -CTS and -DSR inputs respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally (See Figure 4). The -CTS, -DSR, CD, and -RI are disconnected from their normal modem control inputs pins, and instead are connected internally to -DTR, -RTS, INT enable and MCR bit-2. Loop-back test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loopback connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface, D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error free operation of Rev. 3.20 12 ST16C2550 XTAL1 XTAL2 TX A/B MCR Bit-4=1 Receive Shift Register I n te r C o n n e c t B u s L in e s & C o n tr o l s ig n a ls Register Select Logic Receive FIFO Registers RX A/B -RTS A/B -CD A/B -DTR A/B Modem Control Logic INT A/B -RXRDY -TXRDY Transmit Shift Register Interrupt Control Logic A0-A2 -CS A/B Transmit FIFO Registers Clock & Baud Rate Generator D0-D7 -IOR,-IOW RESET Data bus & Control Logic Figure 4, INTERNAL LOOP-BACK MODE DIAGRAM -RI A/B (-OP1 A/B) -DSR A/B (-OP A/B) -CTS A/B Rev. 3.20 13 ST16C2550 REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the twelve 2550 internal registers. The assigned bit functions are more fully defined in the following paragraphs. Table 5, ST16C2550 INTERNAL REGISTERS A2 A1 A0 Register [Default] Note 3* BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 General Register Set: Note 1* 0 0 0 RHR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 THR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 IER  0 0 0 0 Modem Status Interrupt Receive Line Status interrupt Transmit Holding Register interrupt Receive Holding Register 0 1 0 FCR  RCVR trigger (MSB) RCVR trigger (LSB) 0 0 DMA mode select XMIT FIFO reset RCVR FIFO reset FIFO enable 0 1 0 ISR  FIFOs enabled FIFOs enabled 0 0 INT priority bit-2 INT priority bit-1 INT priority bit-0 INT status 0 1 1 LCR  divisor latch enable set break set parity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 MCR  0 0 0 loop back -OP2/ INT enable -OP1 -RTS -DTR 1 0 1 LSR  FIFO data error THR & TSR empty THR. empty break interrupt framing error parity error overrun error receive data ready 1 1 0 MSR [X0] CD RI DSR CTS delta -CD delta -RI delta -DSR delta -CTS 1 1 1 SPR [FF] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 Special Register Set: Note *2 0 0 0 DLL [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 DLM [XX] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 Note 1* The General Register set is accessible only when CS A/B is a logic 0. Note 2* The Baud Rate register set is accessible only when CS A/B is a logic 0 and LCR bit-7 is a logic 1. Note 3* The value between the square brackets represents the registers initialized HEX value, X = N/A. Rev. 3.20 14 ST16C2550 Transmit (THR) and Receive (RHR) Holding Registers FIFO has reached the programmed trigger level. It will be cleared when the receive FIFO drops below the programmed trigger level. The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to the TSR and UART via the THR, providing that the THR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = FIFO full, logic 1= at least one FIFO location available). B) Receive FIFO status will also be reflected in the user accessible ISR register when the receive FIFO trigger level is reached. Both the ISR register receive status bit and the interrupt will be cleared when the FIFO drops below the trigger level. C) The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty. D) When the Transmit FIFO and interrupts are enabled, an interrupt is generated when the transmit FIFO is empty due to the unloading of the data by the TSR and UART for transmission via the transmission media. The interrupt is cleared either by reading the ISR register or by loading the THR with new data characters. The serial receive section also contains an 8-bit Receive Holding Register, RHR and a Receive Serial Shift Register (RSR). Receive data is removed from the 2550 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16x clock rate. After 7 1/2 clocks the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR. IER Vs Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1; resetting IER bits 0-3 enables the 2550 in the FIFO polled mode of operation. In this mode interrupts are not generated and the user must poll the LSR register for TX and/or RX data status. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). Interrupt Enable Register (IER) The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the INT A-B output pins. A) LSR BIT-0 will be a logic 1 as long as there is one byte in the receive FIFO. IER Vs Transmit/Receive FIFO Interrupt Mode Operation B) LSR BIT 1-4 will provide the type of receive errors, or a receive break, if encountered. When the receive FIFO (FCR BIT-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the receive interrupts and register status will reflect the following: C) LSR BIT-5 will indicate when the transmit FIFO is empty. D) LSR BIT-6 will indicate when both the transmit FIFO and transmit shift register are empty. A) The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU when the receive Rev. 3.20 15 ST16C2550 DMA MODE Mode 0 Set and enable the interrupt for each single transmit or receive operation, and is similar to the ST16C450 mode. Transmit Ready (-TXRDY) on 44/48 pin packages will go to a logic 0 when ever an empty transmit space is available in the Transmit Holding Register (THR). Receive Ready (-RXRDY) on 44,/48 pin packages will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with a character. Mode 1 Set and enable the interrupt in a block mode operation. The transmit interrupt is set when the transmit FIFO is below the programmed trigger level. -TXRDY on 44/48 pin packages remains a logic 0 as long as one empty FIFO location is available. The receive interrupt is set when the receive FIFO fills to the programmed trigger level. However the FIFO continues to fill regardless of the programmed level until the FIFO is full. -RXRDY on 44/48 pin packages remains a logic 0 as long as the FIFO fill level is above the programmed trigger level. E) LSR BIT-7 will show if any FIFO data errors occurred. IER BIT-0: In the 16C450 mode, This interrupt will be issued when the RHR has data or is cleared when the RHR is empty. In the FIFO mode, this interrupt will be issued when the FIFO has reached the programmed trigger level or is cleared when the FIFO drops below the trigger level. Logic 0 = Disable the receiver ready (ISR level 2, RXRDY) interrupt. (normal default condition) Logic 1 = Enable the RXRDY (ISR level 2) interrupt. IER BIT-1: In the 16C450 mode, this interrupt will be issued whenever the THR is empty and is associated with bit5 in the LSR register. In the FIFO modes, this interrupt will be issued whenever the FIFO and THR are empty Logic 0 = Disable the Transmit Holding Register Empty (TXRDY) interrupt. (normal default condition) Logic 1 = Enable the TXRDY (ISR level 3) interrupt. FCR BIT-0: Logic 0 = Disable the transmit and receive FIFO. (normal default condition) Logic 1 = Enable the transmit and receive FIFO. This bit must be a 1 when other FCR bits are written to or they will not be programmed. IER BIT-2: This interrupt will be issued whenever an receive data error condition exists as reflected in LSR bits 1-4. Logic 0 = Disable the receiver line status interrupt. (normal default condition) Logic 1 = Enable the receiver line status interrupt. FCR BIT-1: Logic 0 = No FIFO receive reset. (normal default condition) Logic 1 = Clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. IER BIT-3: This interrupt will be issued whenever there is a modem status change as reflected in MSR bits 0-3. Logic 0 = Disable the modem status register interrupt. (normal default condition) Logic 1 = Enable the modem status register interrupt. IER BIT 4-7: Not Used - initialized to a logic 0. FCR BIT-2: Logic 0 = No FIFO transmit reset. (normal default condition) Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: Rev. 3.20 16 ST16C2550 FCR BIT-3: Logic 0 = Set DMA mode 0. (normal default condition) Logic 1 = Set DMA mode 1. An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level. However the FIFO will continue to be loaded until it is full. Transmit operation in mode 0: When the 2550 is in the ST16C450 mode (FIFOs disabled, FCR bit-0 = logic 0) or in the FIFO mode (FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3 = logic 0) and when there are no characters in the transmit FIFO or transmit holding register, the -TXRDY pin in 44/48 pin packages will be a logic 0. Once active the -TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register. BIT-7 BIT-6 RX FIFO trigger level 0 0 1 1 0 1 0 1 01 04 08 14 Interrupt Status Register (ISR) Receive operation in mode 0: When the 2550 is in mode 0 (FCR bit-0 = logic 0) or in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 0) and there is at least one character in the receive FIFO, the -RXRDY pin will be a logic 0. Once active the -RXRDY pin on 44/48 pin packages will go to a logic 1 when there are no more characters in the receiver. The 2550 provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is cleared. However it should be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after rereading the interrupt status bits. The Interrupt Source Table 6 (below) shows the data values (bits 0-3) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels: Transmit operation in mode 1: When the 2550 is in FIFO mode ( FCR bit-0 = logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin on 44/48 pin packages will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. Receive operation in mode 1: When the 2550 is in FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 1) and the trigger level has been reached, or a Receive Time Out has occurred, the RXRDY pin on 44/48 pin packages will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO. FCR BIT 4-5: Not Used - initialized to a logic 0. FCR BIT 6-7: (logic 0 or cleared is the default condition, RX trigger level = 1) These bits are used to set the trigger level for the receive FIFO interrupt. Rev. 3.20 17 ST16C2550 Table 6, INTERRUPT SOURCE TABLE Priority Level [ ISR BITS ] Bit-3 Bit-2 Bit-1 Bit-0 1 2 2 3 4 0 0 1 0 0 1 1 1 0 0 1 0 0 1 0 0 0 0 0 0 Source of the interrupt LSR (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data time out) TXRDY (Transmitter Holding Register Empty) MSR (Modem Status Register) ISR BIT-0: Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic 1 = No interrupt pending. (normal default condition) ISR BIT 1-3: (logic 0 or cleared is the default condition) These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (See Interrupt Source Table). BIT-1 BIT-0 Word length 0 0 1 1 0 1 0 1 5 6 7 8 LCR BIT-2: (logic 0 or cleared is the default condition) The length of stop bit is specified by this bit in conjunction with the programmed word length. ISR BIT 4-5: (logic 0 or cleared is the default condition) Not Used - initialized to a logic 0. ISR BIT 6-7: (logic 0 or cleared is the default condition) These bits are set to a logic 0 when the FIFOs are not being used in the 16C450 mode. They are set to a logic 1 when the FIFOs are enabled in the ST16C2550 mode. Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. BIT-2 Word length Stop bit length (Bit time(s)) 0 1 1 5,6,7,8 5 6,7,8 1 1-1/2 2 LCR BIT-3: Parity or no parity can be selected via this bit. Logic 0 = No parity. (normal default condition) Logic 1 = A parity bit is generated during the transmission, receiver checks the data and parity for transmission errors. LCR BIT 0-1: (logic 0 or cleared is the default condition) These two bits specify the word length to be transmitted or received. LCR BIT-4: If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. Logic 0 = ODD Parity is generated by forcing an odd Rev. 3.20 18 ST16C2550 number of logic 1s in the transmitted data. The receiver must be programmed to check the same format. (normal default condition) Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1s in the transmitted. The receiver must be programmed to check the same format. Logic 1 = Divisor latch and enhanced feature register enabled. Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. LCR BIT-5: If the parity bit is enabled, LCR BIT-5 selects the forced parity format. LCR BIT-5 = logic 0, parity is not forced. (normal default condition) LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. LCR Bit-5 LCR Bit-4 LCR Bit-3 Parity selection X 0 0 1 1 X 0 1 0 1 0 1 1 1 1 No parity Odd parity Even parity Force parity 1 Forced parity 0 MCR BIT-0: Logic 0 = Force -DTR output to a logic 1. (normal default condition) Logic 1 = Force -DTR output to a logic 0. MCR BIT-1: Logic 0 = Force -RTS output to a logic 1. (normal default condition) Logic 1 = Force -RTS output to a logic 0. MCR BIT-2: This bit is used in the Loop-back mode only. In the loop-back mode this bit is use to write the state of the modem -RI interface signal. MCR BIT-3: (Used to control the modem -CD signal in the loop-back mode.) Logic 0 = Forces INT (A-B) outputs to the three state mode and sets -OP2 to a logic 1. (normal default condition) In the Loop-back mode, sets -CD internally to a logic 1. Logic 1 = Forces the INT (A-B) outputs to the active mode and sets -OP2 to a logic 0. In the Loop-back mode, sets -CD internally to a logic 0. LCR BIT-6: When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR bit-6 to a logic 0. Logic 0 = No TX break condition. (normal default condition) Logic 1 = Forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition. MCR BIT-4: Enable the local loop-back mode (diagnostics). In this mode the transmitter output (-TX) and the receiver input (-RX), -CTS, -DSR, -CD, and -RI are disconnected from the 2550 I/O pins. Internally the modem data and control pins are connected into a loop-back data configuration. In this mode, the receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts sources are switched to the lower four bits of the Modem Control. Interrupts continue to be controlled by the IER register. LCR BIT-7: The internal baud rate counter latch and Enhance Feature mode enable. Logic 0 = Divisor latch disabled. (normal default condition) Rev. 3.20 19 ST16C2550 Logic 0 = Disable loop-back mode. (normal default condition) Logic 1 = Enable local loop-back mode (diagnostics). Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. MCR BIT 5-7: Not Used - initialized to a logic 0. LSR BIT-5: This bit is the Transmit Holding Register Empty indicator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. The bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the CPU. In the FIFO mode this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. Line Status Register (LSR) This register provides the status of data transfers between. the 2550 and the CPU. LSR BIT-0: Logic 0 = No data in receive holding register or FIFO. (normal default condition) Logic 1 = Data has been received and is saved in the receive holding register or FIFO. LSR BIT-1: Logic 0 = No overrun error. (normal default condition) Logic 1 = Overrun error. A data overrun error occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case the previous data in the shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. LSR BIT-6: This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one whenever the transmit FIFO and transmit shift register are both empty. LSR BIT-7: Logic 0 = No Error. (normal default condition) Logic 1 = At least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when LSR register is read. LSR BIT-2: Logic 0 = No parity error. (normal default condition) Logic 1 = Parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO. Modem Status Register (MSR) LSR BIT-3: Logic 0 = No framing error. (normal default condition) Logic 1 = Framing error. The receive character did not have a valid stop bit(s). In the FIFO mode this error is associated with the character at the top of the FIFO. This register provides the current state of the control interface signals from the modem, or other peripheral device that the 2550 is connected to. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. LSR BIT-4: Logic 0 = No break condition. (normal default condition) MSR BIT-0: Logic 0 = No -CTS Change (normal default condition) Logic 1 = The -CTS input to the 2550 has changed state since the last time it was read. A modem Status Rev. 3.20 20 ST16C2550 ST16C2550 EXTERNAL RESET CONDITION Interrupt will be generated. MSR BIT-1: Logic 0 = No -DSR Change. (normal default condition) Logic 1 = The -DSR input to the 2550 has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-2: Logic 0 = No -RI Change. (normal default condition) Logic 1 = The -RI input to the 2550 has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated. REGISTERS RESET STATE IER ISR LCR MCR LSR FCR IER BITS 0-7=0 ISR BIT-0=1, ISR BITS 1-7=0 LCR BITS 0-7=0 MCR BITS 0-7=0 LSR BITS 0-4=0, LSR BITS 5-6=1 LSR, BIT 7=0 MSR BITS 0-3=0, MSR BITS 4-7=input signals FCR BITS 0-7=0 SIGNALS RESET STATE TX -OP2 -RTS -DTR INT High High High High Three state mode MSR MSR BIT-3: Logic 0 = No -CD Change. (normal default condition) Logic 1 = Indicates that the -CD input to the has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-4: During normal operation, this bit is the compliment of the -CTS input. During the loop-back mode this bit is equivalent to MCR bit-1 (-RTS). MSR BIT-5: During normal operation, this bit is the compliment of the -DSR input. During the loop-back mode, this bit is equivalent to MCR bit-0 (-DTR). MSR BIT-6: During normal operation, this bit is the compliment of the -RI input. Reading this bit in the loop-back mode produces the state of MCR bit-2 (-OP1) MSR BIT-7: During normal operation, this bit is the compliment of the -CD input. Reading this bit in the loop-back mode produces the state of MCR bit-3 (-OP2). Note: Whenever any MSR bit 0-3: is set to logic 1, a MODEM Status Interrupt will be generated. Scratchpad Register (SPR) The ST16C2550 provides a temporary data register to store 8 bits of user information. Rev. 3.20 21 ST16C2550 AC ELECTRICAL CHARACTERISTICS TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. Symbol T1w,T2w T3w T6s T7d T7w T7h T9d T12d T12h T13d T13w T13h T15d T16s T16h T17d T18d T19d T20d T21d T22d T23d T24d T25d T26d T27d T28d TR N Parameter Clock pulse duration Oscillator/Clock frequency Address setup time -IOR delay from chip select -IOR strobe width Chip select hold time from -IOR Read cycle delay Delay from -IOR to data Data disable time -IOW delay from chip select -IOW strobe width Chip select hold time from -IOW Write cycle delay Data setup time Data hold time Delay from -IOW to output Delay to set interrupt from MODEM input Delay to reset interrupt from -IOR Delay from stop to set interrupt Delay from -IOR to reset interrupt Delay from stop to interrupt Delay from initial INT reset to transmit start Delay from -IOW to reset interrupt Delay from stop to set -RxRdy Delay from -IOR to reset -RxRdy Delay from -IOW to set -TxRdy Delay from start to reset -TxRdy Reset pulse width Baud rate devisor Limits 3.3 Min Max 17 5 10 35 0 40 10 40 0 40 20 5 8 40 1 Rev. 3.20 22 8 35 25 50 40 40 1 45 45 24 45 1 45 45 8 216-1 Limits 5.0 Min Max 17 0 10 25 0 30 10 25 0 30 15 5 8 40 1 Units Conditions 40 35 ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 pF load 100 pF load 35 1 40 40 24 ns Rclk ns ns Rclk 40 1 40 40 8 ns Rclk ns ns Rclk ns Rclk 24 25 15 216-1 100 pF load 100 pF load ST16C2550 ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation 7 Volts GND - 0.3 V to VCC +0.3 V -40° C to +85° C -65° C to 150° C 500 mW DC ELECTRICAL CHARACTERISTICS TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. Symbol VILCK VIHCK VIL VIH VOL VOL VOH VOH IIL ICL ICC CP Parameter Clock input low level Clock input high level Input low level Input high level Output low level on all outputs Output low level on all outputs Output high level Output high level Input leakage Clock leakage Avg power supply current Input capacitance Limits 3.3 Min Max Limits 5.0 Min Max -0.3 2.4 -0.3 2.0 -0.5 3.0 -0.5 2.2 0.6 VCC 0.8 0.4 2.0 Rev. 3.20 23 ±10 ±10 1.3 5 0.6 VCC 0.8 VCC 0.4 2.4 ±10 ±10 3 5 Units V V V V V V V V µA µA mA pF Conditions IOL= 5 mA IOL= 4 mA IOH= -5 mA IOH= -1 mA ST16C2550 Valid Address A0-A2 T6s Active -CSx T13d T13h T13w T15d Active -IOW T16s T16h Data D0-D7 X552-WD-2 General write timing Valid Address A0-A2 T6s Active -CS T7d T7w -IOR T7h Active T12d D0-D7 T9d T12h Data X552-RD-1 General read timing Rev. 3.20 24 ST16C2550 -IOW Active T17d -RTS -DTR Change of state Change of state -CD -CTS -DSR Change of state Change of state T18d T18d INT Active Active Active T19d Active -IOR Active Active T18d Change of state -RI X552-MD-1 Modem input/output timing T1w T2w EXTERNAL CLOCK X654-CK-1 T3w External clock timing Rev. 3.20 25 ST16C2550 START BIT RX STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 5 DATA BITS 6 DATA BITS 7 DATA BITS D6 D7 PARITY BIT NEXT DATA START BIT T20d Active INT T21d Active -IOR 16 BAUD RATE CLOCK Receive timing Rev. 3.20 26 X552-RX-1 ST16C2550 START BIT RX STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 PARITY BIT NEXT DATA START BIT T25d Active Data Ready -RXRDY T26d -IOR Active X552-RX-2 Receive ready timing in none FIFO mode START BIT RX STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 PARITY BIT First byte that reaches the trigger level T25d Active Data Ready -RXRDY T26d -IOR Active Receive timing in FIFO mode Rev. 3.20 27 X552-RX-3 ST16C2550 START BIT TX STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 5 DATA BITS 6 DATA BITS 7 DATA BITS D6 D7 PARITY BIT NEXT DATA START BIT T22d Active Tx Ready INT T24d T23d -IOW Active Active 16 BAUD RATE CLOCK Transmit timing Rev. 3.20 28 X552-TX-1 ST16C2550 START BIT TX STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 PARITY BIT -IOW D0-D7 NEXT DATA START BIT Active T28d BYTE #1 T27d -TXRDY Active Transmitter ready Transmitter not ready X552-TX-2 Transmit ready timing in none FIFO mode Rev. 3.20 29 ST16C2550 START BIT TX DATA BITS (5-8) D0 D1 D2 D3 D4 STOP BIT D5 D6 5 DATA BITS D7 PARITY BIT 6 DATA BITS 7 DATA BITS -IOW Active T28d D0-D7 -TXRDY BYTE #16 T27d FIFO Full X552-TX-3 Transmit ready timing in FIFO mode Rev. 3.20 30 Package Dimensions 40 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) Rev. 1.00 40 21 E1 1 20 E D A2 Seating Plane A L A1 C α B B1 e INCHES SYMBOL eA eB MILLIMETERS MIN MAX MIN MAX A 0.160 0.250 4.06 6.35 A1 0.015 0.070 0.38 1.78 A2 0.125 0.195 3.18 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 1.980 2.095 50.29 53.21 E 0.600 0.625 15.24 15.88 E1 0.485 0.580 12.32 14.73 e 0.100 BSC 2.54 BSC eA 0.600 BSC 15.24 BSC eB 0.600 0.700 15.24 17.78 L 0.115 0.200 2.92 5.08 α 0° 15° 0° 15° Note: The control dimension is the inch column Package Dimensions 44 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) Rev. 1.00 C D D1 Seating Plane 45° x H1 45° x H2 A2 2 1 44 B1 D D1 B D 2 D3 e R D3 A1 A INCHES SYMBOL MIN MAX MILLIMETERS MIN MAX A 0.165 0.180 4.19 4.57 A1 0.090 0.120 2.29 3.05 A2 0.020 –––. 0.51 ––– B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.685 0.695 17.40 17.65 D1 0.650 0.656 16.51 16.66 D2 0.590 0.630 14.99 16.00 D3 0.500 typ. 12.70 typ. e 0.050 BSC 1.27 BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 Note: The control dimension is the inch column Package Dimensions 48 LEAD THIN QUAD FLAT PACK (7 x 7 x 1.0 mm, TQFP) Rev. 1.00 D D1 36 25 37 24 D1 D 48 13 1 12 B e A2 C A Seating Plane α A1 L INCHES SYMBOL MIN MAX MILLIMETERS MIN MAX A 0.039 0.047 1.00 1.20 A1 0.002 0.006 0.05 0.15 A2 0.037 0.041 0.95 1.05 B 0.007 0.011 0.17 0.27 C 0.004 0.008 0.09 0.20 D 0.346 0.362 8.80 9.20 D1 0.272 0.280 6.90 7.10 e 0.020 BSC 0.50 BSC L 0.018 0.030 0.45 0.75 α 0° 7° 0° 7° Note: The control dimension is the millimeter column NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1990 EXAR Corporation Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.