EXAR XRD98L63

XRD98L63
CCD Image Digitizers with
CDS, PGA and 12-Bit A/D
June 2003
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
12-bit Resolution ADC, 30MHz Sampling Rate
10-bit Programmable Gain: 6dB to 36dB PGA
Pixel-by-pixel gain switching
Digitally Controlled Black Level Calibration with
Pixel Averager and Hot Pixel Clipper
DNS Filter Removes Black Level Digital Noise
Programmable Black Level, up to code 255
Black Level Calibration Range: 300 mV
Programmable Aperture Delays
1.0 ns/step for SBLK & SPIX
0.5 ns/step for ADCLK
Manual Control of Offset DACs via Serial Port
for use with High-speed Scanners
Single 2.7V to 3.6V Power Supply
Optimize power with external resistor to 100mW
Low Power for Battery Operation
100µA Stand-by Mode Current
• Three-state Digital Outputs
• 3,000V ESD Protection
• 48-pin TQFP Package
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
Mega pixel Digital Still Cameras
Digital Camcorders
3 CCD Professional/Broadcast Camera
Line Scan Cameras
PC Video Cameras
CCTV/Security Cameras
Industrial/Medical Cameras
2D Bar Code Readers
High Speed Scanners
Digital Copiers
GENERAL DESCRIPTION
The XRD98L63 is a complete, low power CCD Image
Digitizer for digital motion and still cameras. The
product includes a high bandwidth differential Correlated Double Sampler (CDS), 10-bit Programmable
Gain Amplifier (PGA) with pixel rate gain switching, 12bit Analog-to-Digital Converter (ADC) and improved
digitally controlled black level auto-calibration circuitry
with programmable pixel averaging, hot pixel clipping,
and a Digital Noise Suppression (DNS) filter.
The Correlated Double Sampler (CDS) subtracts the
CCD output signal black level from the video level.
Common mode and power supply noise are rejected by
the differential CDS input stage.
The PGA is digitally controlled with 10-bit resolution on
a dB scale, resulting in a gain range of 6dB to 36dB with
0.047dB per LSB of the gain code. The PGA can be
programmed to switch gain every pixel, in a user
defined pattern of up to 4 different gains. Our proprietary control logic allows a camera system to set the
desired gain ratios for color balance. The system gain
can then be changed by writing to a single register,
and the color balance will be maintained.
The black level auto-calibration circuit averages the
results of the Optical Black pixels to compensate for
any internal offset of the XRD98L63 as well as black
level offset from the CCD. The calibration logic uses
proprietary digital filters to eliminate line-to-line offset
noise and noise due to hot pixels in the Optical Black
areas.
The PGA and black level auto-calibration are controlled through a simple 3-wire serial interface. The
timing circuitry is designed to enable users to select a
wide variety of available CCD and image sensors for
their applications. Readback of the serial data registers is available from the digital output bus.
The XRD98L63 is packaged in 48-lead TQFP to reduce
space and weight, and is suitable for hand-held and
portable applications.
ORDERING INFORMATION
Part No.
XRD98L63AIV
Package
Temperature Range
Operating
Power Supply
Maximum
Sampling Rate
48-Pin TQFP
-40°C to 85°C
2.7V to 3.6V
30 MSPS
Rev.1.01
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
18.2 KΩ
VCM
AGND
CAPN
AVDD
CAPP
XRD98L63
BIASRES
Bias
Gain[9:0]
NoCDS
ADCin
RBenable
CCDIN
CDS
REFIN
FSYNC
CLAMP
CAL
SPIX
SBLK
ADCLK
PBLK
EOS
SDI
SCLK
LOAD
+
PGA
+
12-bit ADC
Reg
Gain
Logic
Black Level
Offset Calibration
Loop
FDAC
Timing
Logic
CDAC
Gain[9:0]
Offset Calibration
Logic
Digital Noise
Suppression
Averager
Serial
Interface
Readback data
to output mux
DVDD
DGND
PD
RESET
OE
Figure 1. XRD98L63 Block Diagram
N/C
AGND
N/C
AVDD
VCM
N/C
CCDIN
REFIN
N/C
AVDD
AGND
AGND
PIN CONFIGURATION
36 35 34 33 32 31 30 29 28 27 26 25
BIASRES
CAPP
CAPN
AVDD
AGND
OE
RESET
PD
TESTOUT
LOAD
SDI
SCLK
37
38
39
40
41
42
43
44
45
46
47
48
XRD98L63
(top view)
24
23
22
21
20
19
18
17
16
15
14
13
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
1 2 3 4 5 6 7 8 9 10 11 12
Figure 2. XRD98L63 Pinout
Rev.1.01
2
FSYNC
CLAMP
SPIX
SBLK
CAL
PBLK
EOS
DVDD
ADCLK
DGND
OGND
OVDD
OVDD
DB[11:0]
Readback
data from
Serial Interface
Hot
Pixel
Clipper
OGND
XRD98L63
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
Type
Description
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
OVDD
OGND
DGND
ADCLK
DVDD
EOS
PBLK
CAL
SBLK
SPIX
CLAMP
FSYNC
AGND
AGND
AVDD
N/C
REFIN
CCDIN
N/C
VCM
AVDD
N/C
AGND
N/C
BIASRES
CAPP
CAPN
AVDD
AGND
OE
RESET
PD
TESTOUT
LOAD
SDI
SCLK
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Power
Ground
Ground
Digital in
Power
Digital in
Digital in
Digital in
Digital in
Digital in
Digital in
Digital in
Ground
Ground
Power
ADC Output (LSB)
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output (MSB)
Digital Output Power Supply (must be < AVDD )
Digital Output Ground
On chip Logic Ground
ADC Clock
On chip Logic Power Supply (must = AVDD)
Even/Odd Line select
Pre-Blanking clock
Calibration Control Clock (clamp OB)
CDS Sample Black Clock
CDS Sample Pixel Clock
DC-Restore Input Clamp Control Clock
Frame Sync Clock
Analog Ground
Analog Ground
Analog Power Supply
(Not used)
CCD Reference Signal
CCD Input Signal
(Not used)
Common mode bias by-pass
Analog Power Supply
(Not used)
Analog Ground
(not used)
External Reference Resistor (connect 18.2KΩ resistor to ground)
ADC Reference By-Pass
ADC Reference By-Pass
Analog Power Supply
Analog Ground
Output Enable Control, 1=high-Z, 0=enable, internal pull down
Reset Control, 1=convert, 0=reset, internal pull up
Power Down Control, 1=Power Down, 0=convert, internal pull down
Factory Test Output
Serial Interface Data Load
Serial Interface Data Input
Serial Interface Shift Clock
Analog
Analog
Analog
Power
Ground
Analog
Analog
Analog
Power
Ground
Digital in
Digital in
Digital in
Digital out
Digital in
Digital in
Digital in
Rev.1.01
3
XRD98L63
DC ELECTRICAL CHARACTERISTICS – XRD98L63
U n less otherw ise specified: O V DD = DVDD =AVDD = 3.0V, Pixel Rate = 30MSPS, TA = 25°C
Rext = 18.2 KΩ
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
0.8
1.0
V PP
Pixel (VBLK - VVIDEO), (See Figure 3).
Maximum Dark Voltage Offset
300
mV
At any gain. (See Figure 3).
Reset Pulse
500
mV
75
Ω
CDS Performance
CDSVIN
V DARK
Vrst
r CLAMP
Input Range
Clamp On Resistance
25
40
PGA Parameters
AVMIN
Minimum Gain
6
dB
Gain Code = 0
AVMAX
Maximum Gain
36
dB
Gain Code > 640
PGA n
Resolution
10
bits
Transfer function is linear steps in dB
0.047
dB
PGA Step
Gain Step Size
ADC Parameters (Measured in ADC Test Mode, ADCin=1)
ADC n
fs
Resolution
12
bits
Max Sample Rate
30
MSPS
DNL
Differential Non-Linearity
+0.5
VID
Full Scale Differential Input
+0.9
ADC Reference Voltage
0.9
∆VREF
Rev.1.01
4
+1.0
LSB
V
∆VREF = CapP - CapN
XRD98L63
DC ELECTRICAL CHARACTERISTICS – XRD98L63 (cont'd)
Unless otherwise specified: OVDD = DVDD =AVDD = 3.0V, Pixel Rate = 30MSPS, TA = 25°C
Rext = 18.2 KΩ
Symbol
Parameter
Min.
Typ. Max.
Unit
Conditions
+0.6
LSB
No missing codes, monotonic
System Specifications
DNL S
System DNL
fsmax
Maximum Sample Rate
fsmin
Minimum Sample Rate
500
KSPS
Not tested
+1.0
30
MSPS
en
MAXAV
Input ref. Noise, max.Gain
180
µVrms
Gain Code = 640 (36db)
en
MINAV
Input ref. Noise, min.Gain
400
µVrms
Gain Code = 0 (6dB)
Latency
Pipeline Delay
7.5
cycles
Digital Inputs (Digital Input Thresholds are Set by DVDD)
VIH
Digital Input High Voltage
V IL
Digital Input Low Voltage
V
VDD-0.5
GND+0.5
V
±1.0
µA
VIN between GND and VDD.
-5
100
µA
PD and OE have internal pull-down
resisters
IL
DC Leakage Current
IL
Input Leakage, PD and OE
IL
Input Leakage, RESET
-100
5
µA
RESET has an internal pull-up
resister
IL
Input Leakage, All Other
Digital Inputs
-100
100
nA
Input = VDD or GND
CIN
0.05
Input Capacitance
5
pF
Digital Outputs
VOH
Digital Output High Voltage
V OL
Digital Output Low Voltage
IOZ
High–Z Leakage
V
While sourcing 2mA
0.5
V
While sinking 2mA
±1.0
µA
OE = 1 or PD = 1 or OE bit = 0
OVDD-0.5
0.05
Rev.1.01
5
XRD98L63
DC ELECTRICAL CHARACTERISTICS – XRD98L63 (cont'd)
Unless otherwise specified: OVDD = DVDD =AVDD = 3.0V, Pixel Rate = 30MSPS, TA = 25°C
Rext = 18.2 KΩ
Symbol
Parameter
Min.
Typ.
Max.
Unit
20
27
ns
Conditions
Digital I/O Timing
tDL
Data Valid Delay
10 pF load, Note1
tPW1
Pulse Width of SPIX
10
ns
tPW2
Pulse Width of SBLK
10
ns
tPIX
Pixel Period
33
ns
t BK
Sample Black (SBLK),
Aperture Delay
5
7
ns
SBdly[5:0] = 0, Note 1
tVD
6
8
ns
SPdly[8:0] = 0, Note 1
t SCLK
Sample Video (SPIX),
Aperture Delay
Shift Clock Period
100
ns
tSET
Shift Register Setup Time
10
ns
tHOLD
Shift Register Hold Time
t L1
Load Set-up Time
t L2
Load Hold Time
0
10
ns
ns
0
ns
Power Supplies
AVDD
Analog Supply Voltage
2.7
3.0
3.6
V
DVDD
Digital Supply Voltage
2.7
3.0
3.6
V
Set DVDD = AVDD
OVDD
Digital Output Supply Voltage
2.7
3.0
3.6
V
OVDD < AVDD
40
45
mA
OVDD = AVDD = DVDD = 3.0V
0.02
0.1
mA
PD = 1 or CHIPpd register bit = 1
IDD
Supply Current
IDDPD
Power Down Supply Current
Note 1. Guaranteed by design, not tested
Rev.1.01
6
XRD98L63
OB Pixel
VBlack
Active Pixels
VBlack
VDark
CCD
Waveform
VVideo
Figure 3. Definition of terms for VOut of the CCD waveform:
CDSVIN = (VBlack - VVideo)
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3
VDD to GND
VRT & VRB
VIN
All Inputs
All Outputs
Storage Temperature
+6.6V
Lead Temperature (Soldering 10 seconds)
300°C
Maximum Junction Temperature
150°C
Package Pow erD issipation R atings (T A= +70°C)
TQFP
θJA = 105°C/W
VDD +0.5 to GND -0.5V
VDD +0.5 to GND -0.5V
VDD +0.5 to GND -0.5V
VDD +0.5 to GND -0.5V
-65°C to 150°C
ESD
2000V
Notes:
1
Stresses above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode
clamps from input pin to the supplies. All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100µs.
3
VDD refers to AVDD, OVDD and DVDD. GND refers to AGND, OGND and DGND.
Rev.1.01
7
XRD98L63
SERIAL INTERFACE
The XRD98L63 uses a three wire serial interface
(LOAD, SDI & SCLK) to access the programmable
features and controls of the chip. The serial interface
uses a 16-bit shift register. The first 6 bits shifted in are
the address bits, the next 10 bits are the data bits. The
address bits select which of the internal registers will
receive the 10 data bits.
data will be discarded. There is a readback function
(see the Serial Interface Read Back section) that
outputs the contents of a selected register on pins
DB[11:2] of the digital output bus.
The following is the procedure for writing to the serial
interface:
1) Force LOAD pin low to enable shift register.
2) Shift in 16 bits, 6 address bits (msb first),
followed by 10 data bits (msb first).
3) Force LOAD pin high to transfer data from the
shift register to the serial interface register array.
The interface will only load data from the shift register
into the register array if there are exactly 16 rising edges
of SCLK while LOAD is low. If more or less rising edges
are present, the data is discarded. There is no checking
of the address bits to ensure a valid register is written
to. If the address bits select an undefined register, the
Note: There must be exactly 16 rising edges of
SCLK while LOAD is low.
LOAD
tL 1
tL 2
tS C L K
SCLK
tset
SDI
thold
A5
A4
t1
A3
MSB
A2
A1
A0
D9
LSB
D8
D7
D6
D5
D4
D3
D2
…
t2
D1
t15
D0
t16
Time
Figure 4. Serial Interface Timing Diagram
LSB
MSB
D a ta Bits
Address Bits
SDI
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
A0
A1
A2
A3
SCLK
D a ta Input
LOAD
Register
Address
Select
Decoder
Register Array
Read Back
Output Bus
Figure 5. Serial Interface Block Diagram
Rev.1.01
8
to DB[11:2]
A4
A5
XRD98L63
Address bits
Data bits
Reg. Name A5 A4 A3 A2 A1 A0
PGA00
0
0
0
0
0
D9
PGA00[9]
0
0
Offset
0
0
0
0
0
1
PGA01
0
0
0
0
1
0
PGA10
0
0
0
0
1
1
PGA11
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
OB Even
Gain
OB Odd
Gain
Even Line
0
0
0
1
1
1
Odd Line
0
0
1
0
0
0
Calibration
0
0
1
0
0
1
Wait A
0
0
1
0
1
0
Wait B
0
0
1
0
1
1
OB Lines
0
0
1
1
0
0
CDAC Even 0
0
1
1
0
1
CDAC Odd
0
1
1
1
0
0
FDAC Even 0
FDAC Odd
0
0
1
1
0
1
0
1
0
1
0
Control
0
1
0
0
0
1
Test
0
1
0
0
1
0
Polarity
0
1
0
0
1
1
Clock
0
1
0
1
0
0
SBLKdly
0
1
0
1
0
1
SPIXdly
0
1
0
1
1
0
ADCdly
0
1
0
1
1
1
ReadBack
1
1
1
1
1
0
Reset
1
1
1
1
1
1
PRE[1]
0
PRO[1]
0
WL[11]
0
D8
D7
D6
D5
D4
D3
D2
D1
0
0
OB[7]
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ELP4[0]
0
OLP4[0]
0
Avg[1]
1
0
ELP3[1]
0
OLP3[1]
0
Avg[0]
0
0
ELP3[0]
0
OLP3[0]
0
DNS[1]
0
0
ELP2[1]
1
OLP2[1]
0
DNS[0]
1
0
ELP2[0]
1
OLP2[0]
0
Mode
0
0
ELP1[1]
1
OLP1[1]
0
Hold
0
0
0
0
0
0
0
0
WL[1]
0
OBL[7]
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PGA01[8]
0
0
PGA10[8]
0
0
PGA11[8]
0
0
OBE[8]
0
0
OBO[8]
0
0
PRE[0]
ELP4[1]
1
0
PRO[0] OLP4[1]
1
0
OBdel[1] OBdel[0]
0
0
0
CDE[8]
0
CDO[8]
0
FDE[9]
0
FDO[9]
ADCpd
0
0
AFEpd
0
nofs2
0
SPdly[8]
0
RBenable RBreg[8]
0
0
0
0
0
CHIPpd
OE
MultGain
0
1
0
*Reserved *Reserved *Reserved
0
0
1
PBLKpol EOSpol SBLKpol
0
1
0
ADCLKsel
0
SBdly[5]
0
0
0
0
0
MGsel[1] MGsel[0] MGstart MinClip
0
0
0
1
*Reserved ADCin
NoCDS *Reserved
0
0
0
0
SPIXpol CALpol CLAMPpol FSYNCpol
0
0
0
0
CLAMPopt CALonly SPIXopt RSTreject
0
0
0
0
0
0
0
0
0
ADCdly[7]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note: Shaded cells represent unused bits.
* Reserved Test register bits. Used for factory test only. Please do not modify.
Table 1. Serial Interface Register Address Map & default values
Rev.1.01
9
D0
PGA00[0]
0
OB[0]
0
PGA01[0]
0
PGA10[0]
0
PGA11[0]
0
OBE[0]
0
OBO[0]
0
ELP1[0]
0
OLP1[0]
1
ManCal
0
WL[2]
0
WL[0]
1
OBL[0]
0
CDE[0]
0
CDO[0]
0
FDE[0]
0
FDO[0]
0
OneV
0
*Reserved
0
ADCpol
0
DOclamp
1
SBdly[0]
0
SPdly[0]
0
ADCdly[0]
0
RBreg[0]
0
Reset
0
XRD98L63
PGA00 Register
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PGA00[9] PGA00[8] PGA00[7] PGA00[6] PGA00[5] PGA00[4] PGA00[3] PGA00[2] PGA00[1] PGA00[0]
0
0
0
0
0
0
0
0
0
0
PGA00
default
PGA00[9:0] is used to set the gain of the Programmable Gain Amplifier (PGA).
Code = 0000000000 is minimum gain (6dB). Code ≥ 1001111111 is maximum gain (36dB).
See the “Programmable Gain Amplifier” (pg. 16) and the “Multiple Gain Mode” (pg. 30) sections for more
information.
Offset Register
D9
D8
0
0
Offset
default
D7
OB[7]
1
D6
OB[6]
0
D5
OB[5]
0
D4
OB[4]
0
D3
OB[3]
0
D2
OB[2]
0
D1
OB[1]
0
D0
OB[0]
0
OB[7:0] is used by the Offset Calibration logic as the target output code for Optical Black pixels.
See the “Black Level Offset Calibration” section (pg. 19) for more information.
PGA01, PGA10 and PGA11 Registers
D9
PGA01
default
PGA10
default
PGA11
default
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
PGA01[8] PGA01[7] PGA01[6] PGA01[5] PGA01[4] PGA01[3] PGA01[2] PGA01[1] PGA01[0]
0
0
0
0
0
0
0
0
0
PGA10[8] PGA10[7] PGA10[6] PGA10[5] PGA10[4] PGA10[3] PGA10[2] PGA10[1] PGA10[0]
0
0
0
0
0
0
0
0
0
PGA11[8] PGA11[7] PGA11[6] PGA11[5] PGA11[4] PGA11[3] PGA11[2] PGA11[1] PGA11[0]
0
0
0
0
0
0
0
0
0
PGA01[8:0], PGA10[8:0] and PGA11[8:0] are used in the Multiple Gain mode to program the gain ratios for
different pixel colors. See the “Multiple Gain Mode” section (pg. 30) for more information.
OB Even Gain & OB Odd Gain Registers
D9
OB Even Gain
default
0
D8
OBE[8]
0
D7
OBE[7]
0
D6
OBE[6]
0
D5
OBE[5]
0
D4
OBE[4]
0
D3
OBE[3]
0
D2
OBE[2]
0
D1
OBE[1]
0
D0
OBE[0]
0
OBE[8:0] is used in the Multiple Gain mode to program the gain to be applied to Optical Black pixels on Even
lines during Offset Calibration. OBO[8:0] is used in the Multiple Gain mode to program the gain to be applied
to Optical Black pixels on Odd lines during Offset Calibration. See the “Multiple Gain Mode” section (pg. 30)
for more information.
Even Line and Odd Line Registers
D9
PRE[1]
0
PRO[1]
0
Even Line
default
Odd Line
default
D8
PRE[0]
1
PRO[0]
1
D7
ELP4[1]
0
OLP4[1]
0
D6
ELP4[0]
0
OLP4[0]
0
D5
ELP3[1]
0
OLP3[1]
0
D4
ELP3[0]
0
OLP3[0]
0
D3
ELP2[1]
1
OLP2[1]
0
D2
ELP2[0]
1
OLP2[0]
0
D1
ELP1[1]
1
OLP1[1]
0
D0
ELP1[0]
0
OLP1[0]
1
The Even Line and Odd Line Registers are used to program the pixel patterns for Even and Odd lines in the
Multiple Gain mode. See the “Multiple Gain Mode” section (pg. 30) for more information.
Calibration Register
D9
Calibration
default
0
D8
OBdel[1]
0
D7
OBdel[0]
0
D6
Avg[1]
1
D5
Avg[0]
0
D4
DNS[1]
0
D3
DNS[0]
1
D2
Mode
0
D1
Hold
0
D0
ManCal
0
The Calibration register is used to program various options for the Offset Calibration logic.
OBdel[1:0], sets the number of Fringe pixels which should not be used for Black Level Calibration.
Avg[1:0], sets the number of OB pixels to average, 00=32 pix, 01=64 pix, 10=128 pix, 11=256 pix.
DNS[1:0], sets the Digital Noise Suppression filter width, 00=no filter, 01=narow, 10=med, 11=wide.
Mode, sets Calibration mode. 0=Line mode, 1=Frame mode (not supported at this time).
Hold, used to stop calibration updates. 0=Calibration active. 1=stop, hold current Calibration values.
ManCal, used to manually program the Offset DACs. 0=automatic mode. 1=manual mode.
See the “Black Level Offset Calibration” section (pg. 19) for more information.
Rev.1.01
10
XRD98L63
Wait A, Wait B and OB Lines Registers
WaitA
default
WaitB
default
OB Lines
default
D9
WL[11]
0
D8
WL[10]
0
D7
WL[9]
0
D6
WL[8]
0
D5
WL[7]
0
D4
WL[6]
0
D3
WL[5]
0
D2
WL[4]
0
0
0
0
0
0
OBL[7]
1
0
OBL[6]
0
0
OBL[5]
0
0
OBL[4]
0
0
OBL[3]
0
0
OBL[2]
0
D1
WL[3]
0
WL[1]
0
OBL[1]
1
D0
WL[2]
0
WL[0]
1
OBL[0]
0
WL[11:0] and OBL[7:0] are used by the Black Level Calibration logic in the Frame mode to determine which
lines to use for Calibration. (Frame mode is not currently supported)
See the “Black Level Offset Calibration” section (pg. 19) for more information.
CDAC Even and CDAC Odd Registers
D9
CDAC Even
default
CDAC Odd
default
0
0
D8
CDE[8]
0
CDO[8]
0
D7
CDE[7]
0
CDO[7]
0
D6
CDE[6]
0
CDO[6]
0
D5
CDE[5]
0
CDO[5]
0
D4
CDE[4]
0
CDO[4]
0
D3
CDE[3]
0
CDO[3]
0
D2
CDE[2]
0
CDO[2]
0
D1
CDE[1]
0
CDO[1]
0
D0
CDE[0]
0
CDO[0]
0
CDE[8:0] and CDO[8:0] are used to program the internal Coarse Offset DAC in the Manual Calibration
mode. In the normal, single gain mode the value in CDE[8:0] is used. In the Multiple Gain mode, CDE[8:0] is
used for Even lines and CDO[8:0] is used for Odd lines.
See the “Black Level Offset Calibration” section (pg. 19) for more information.
FDAC Even and FDAC Odd Registers
FDAC Even
default
FDAC Odd
default
D9
FDE[9]
0
FDO[9]
0
D8
FDE[8]
0
FDO[8]
0
D7
FDE[7]
0
FDO[7]
0
D6
FDE[6]
0
FDO[6]
0
D5
FDE[5]
0
FDO[5]
0
D4
FDE[4]
0
FDO[4]
0
D3
FDE[3]
0
FDO[3]
0
D2
FDE[2]
0
FDO[2]
0
D1
FDE[1]
0
FDO[1]
0
D0
FDE[0]
0
FDO[0]
0
FDE[9:0] and FDO[9:0] are used to program the internal Fine Offset DAC in the Manual Calibration mode. In
the normal, single gain mode the value in FDE[9:0] is used. In the Multiple Gain mode, FDE[9:0] is used for
Even lines and FDO[9:0] is used for Odd lines.
See the “Black Level Offset Calibration” section (pg. 19) for more information.
Control Register
Control
default
D9
ADCpd
0
D8
AFEpd
0
D7
CHIPpd
0
D6
OE
1
D5
MultGain
0
D4
MGsel[1]
0
D3
MGsel[0]
0
D2
MGstart
0
D1
MinClip
1
D0
OneV
0
The Control register is used to program various options.
ADCpd, power down the ADC block. 0=normal operation. 1=ADC power down.
AFEpd, power down the AFE block. 0=normal operation. 1=AFE power down.
OE, output enable control. 0=DB[11:0] in high Z mode. 1=DB[11:0] in active drive mode.
MultGain, enable the Multiple Gain mode. 0=single gain mode. 1= Multiple Gain mode.
MGsel[1:0], Multiple Gain timing mode select.
MGstart, Even or Odd starting condition for MGsel[1:0]=11. 0=start with Even line, 1=start with Odd line.
MinClip, minimum clip option. 0=minimum clip disabled, 1=minimum clip enabled.
OneV, 1 volt input range option. 0=0.8V maximum input range. 1=1.0V maximum input range.
See the “Chip Power Down” section (pg. 34) for information about ADCpd, AFEpd, CHIPpd and OE.
See the “Multiple Gain Mode” section (pg. 30) for information about MultGain, MGsel[1:0] and MGstart.
See the “Other Chip Controls and Features” section (pg. 34) for information about MinClip.
See the “One Volt Input Option” section (pg. 16) for information about OneV.
Rev.1.01
11
XRD98L63
Test Register
D9
Test
default
0
D8
nofs2
0
D7
D6
D5
D4
*Reserved *Reserved *Reserved *Reserved
0
0
1
0
D3
ADCin
0
D2
NoCDS
0
D1
D0
*Reserved *Reserved
0
0
The Test register is used to program various special modes of the chip.
* Reserved bits are for Exar Factory test only, do not modify these bits.
nofs2, analog ½ scale offset control. 0=normal CCD signal conversion. 1=no ½ scale offset at PGA.
ADCin, ADC direct analog input mode. 0=normal operation. 1=CCDin & REFin connect directly to ADC.
NoCDS, CDS By-Pass mode. 0=normal operation. 1=CCDin & REFin connect directly to PGA.
See the “Analog Front End” section (pg. 15) for information about nofs2 and NoCDS
See the “Analog to Digital Converter” section (pg. 18) for information about ADCin,
Polarity Register
D9
D8
0
0
Polarity
default
D7
PBLKpol
0
D6
EOSpol
1
D5
SBLKpol
0
D4
SPIXpol
0
D3
CALpol
0
D2
D1
CLAMPpol FSYNCpol
0
0
D0
ADCpol
0
The Polarity register is used to program the polarity of the clock inputs. All the clock inputs (except the serial
interface SCLK) can be programmed to be active high or active low. 0=active low. 1=active high.
See the “Clock Polarity” section (pg. 22) for more information.
Clock Register
D9
D8
D7
D6
0
0
0
0
Clock
default
D5
D4
D3
ADCLKsel CLAMPopt CALonly
0
0
0
D2
SPIXopt
0
D1
D0
RSTreject DOclamp
0
1
The Clock register is used for programming various clocking options.
ADCLKsel, select internal or external ADC clock. 0=external ADCLK pin. 1=internal ADCLK.
CLAMPopt, DC restore biasing. 0=bias powered only when CLAMP is active. 1=bias always powered.
CALonly, line timing option. 0=CAL & CLAMP signals required. 1=only CAL signal required.
SPIXopt, φ2 signal generation option. 0=φ2 is a function of SPIX. 1=φ2 is a function of SBLK & SPIX.
RSTreject, reset pulse rejection option. 0=φ3 always ON. 1=φ3 switched to reject CCD reset pulse.
DOclamp, digital output clamp option. 0=disable clamp function. 1=PBLK forces digital outputs to OB[7:0]
See the “Analog Front End” section (pg. 15) for information about CLAMPopt.
See the “Pixel Rate Clocks, SBLK, SPIX, and ADCLK” section (pgs. 22-25) for information about ADCLKsel,
CAL only, SPIXopt and RSTreject.
See the “Other Chip Controls and Features” section (pg. 34) for information about DOclamp.
SBLK Delay, SPIX Delay and ADC Delay Registers
D9
D8
0
0
0
SPdly[8]
0
0
0
SBLK Delay
default
SPIX Delay
default
ADC Delay
default
D7
D6
D5
D4
D3
D2
D1
D0
SBdly[5] SBdly[4] SBdly[3] SBdly[2] SBdly[1] SBdly[0]
0
0
0
0
0
0
0
0
SPdly[7] SPdly[6] SPdly[5] SPdly[4] SPdly[3] SPdly[2] SPdly[1] SPdly[0]
0
0
0
0
0
0
0
0
ADCdly[7] ADCdly[6] ADCdly[5] ADCdly[4] ADCdly[3] ADCdly[2] ADCdly[1] ADCdly[0]
0
0
0
0
0
0
0
0
SBdly[5:0], SPdly[8:0] and ADCdly[7:0] are used to program the internal aperture delay options. Each
register is divided into 2 or 3 delay parameters. For each delay parameter, minimum delay is all 0’s, and
maximum delay is all 1’s.
See the “Aperture Delays” section (pg. 26) for information about the Programmable Aperture Delays.
Rev.1.01
12
XRD98L63
Readback Register
Readback
default
D9
RBenable
0
D8
RBreg[8]
0
D7
RBreg[7]
0
D6
RBreg[6]
0
D5
RBreg[5]
0
D4
RBreg[4]
0
D3
RBreg[3]
0
D2
RBreg[2]
0
D1
RBreg[1]
0
D0
RBreg[0]
0
RBenable, used to enable the Readback feature. 0=Readback OFF. 1=ReadBacK ON.
RBreg[8:6], used to select internal Calibration or Multiple Gain registers for Readback.
RBreg[5:0], used to select internal Serial Interface registers for Readback.
See the “Serial Interface Readback” section (pg. 14) for more information.
Reset Register
D9
D8
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
Reset
default
D0
Reset
0
The Reset bit is used to reset the chip to power-up default conditions.
Program Reset=1 to reset the chip. After all internal registers are reset, the Reset bit will clear itself.
See the “Chip Reset” section (pg. 34) for more information.
Rev.1.01
13
XRD98L63
Serial Interface Readback
Registers are selected for readback by writing to the
RBreg[8:0] bits in the Readback register, bits D8 to D0.
If RBreg[8:6]=000, then RBreg[5:0] are used to address the serial interface registers. Currently only
register addresses 0 to 23, 62 and 63 are defined. If
RBreg[8:6]≠000, then RBreg[5:0] are ignored and
RBreg[8:6] are used to address registers in the calibration logic.
The readback function is used to view the content of
the serial interface registers as well as several key
registers in the ofset calibration logic. Readback is
enabled by writing a 1 to the RBenable bit (D9) of the
Readback register.
In the readback mode, the content of the selected
register is output on the 10 MSBs of the ADC output
bus pins DB[11:2]. As long as valid clocks and CCD
signal are applied, the calibration will continue to
function properly during readback (internally the ADC
data is still sent to the calibration logic).
RBenable RBreg[8] RBreg[7] RBreg[6] RBreg[5] RBreg[4] RBreg[3] RBreg[2] RBreg[1] RBreg[0]
Selected Register
Register Number
0
x
x
x
x
x
x
x
x
x
none (ADC data output)
1
0
0
0
0
0
0
0
0
0
PGA00
0
1
0
0
0
0
0
0
0
0
1
Offset
1
1
0
0
0
0
0
0
0
1
0
PGA01
2
1
0
0
0
0
0
0
0
1
1
PGA10
3
1
0
0
0
0
0
0
1
0
0
PGA11
4
1
0
0
0
0
0
0
1
0
1
OB Even Gain
5
1
0
0
0
0
0
0
1
1
0
OB Odd Gain
6
1
0
0
0
0
0
0
1
1
1
Even Line
7
1
0
0
0
0
0
1
0
0
0
Odd Line
8
1
0
0
0
0
0
1
0
0
1
Calibration
9
1
0
0
0
0
0
1
0
1
0
Wait A
10
1
0
0
0
0
0
1
0
1
1
Wait B
11
1
0
0
0
0
0
1
1
0
0
OB Lines
12
1
0
0
0
0
0
1
1
0
1
CDAC Even
13
1
0
0
0
0
0
1
1
1
0
CDAC Odd
14
1
0
0
0
0
0
1
1
1
1
FDAC Even
15
1
0
0
0
0
1
0
0
0
0
FDAC Odd
16
1
0
0
0
0
1
0
0
0
1
Control
17
1
0
0
0
0
1
0
0
1
0
Test
18
1
0
0
0
0
1
0
0
1
1
Polarity
19
1
0
0
0
0
1
0
1
0
0
Clock
20
1
0
0
0
0
1
0
1
0
1
SBLKdly
21
1
0
0
0
0
1
0
1
1
0
SPIXdly
22
1
0
0
0
0
1
0
1
1
1
ADCdly
23
1
0
0
0
1
1
1
1
1
0
ReadBack
62
1
0
0
0
1
1
1
1
1
1
Reset
63
1
0
0
1
x
x
x
x
x
x
Average Even (internal)
Cal 1
1
0
1
0
x
x
x
x
x
x
Average Odd (internal)
Cal 2
1
0
1
1
x
x
x
x
x
x
CDAC Even (internal)
Cal 3
1
1
0
0
x
x
x
x
x
x
CDAC Odd (internal)
Cal 4
1
1
0
1
x
x
x
x
x
x
FDAC Even (internal)
Cal 5
1
1
1
0
x
x
x
x
x
x
FDAC Odd (internal)
Cal 6
1
1
1
1
x
x
x
x
x
x
Gain (internal)
Cal 7
Table 2. Readback Register Selection
Rev.1.01
14
XRD98L63
ANALOG FRONT END (AFE)
Correlated Double Sample/Hold (CDS)
The function of the CDS block is to sense the voltage
difference between the black level and video level for
each pixel. The PGA amplifies the difference to the
desired level for the ADC. The CDS and PGA are fully
differential. The CCDIN pin should be connected, via a
capacitor, to the CCD output signal. The REFIN pin
should be connected, via a capacitor, to the CCD
“Common” voltage (typically the CCD ground is used as
the “Common” voltage). These capacitors, C1 and C2,
are typically 0.01µF ± 10% or better matching.
The CLAMPopt bit in the Clock register controls the
circuit which generates the Vbias1 level. When
CLAMPopt=0 (the default condition), the Vbias1 level is
only generated while CLAMP is active. When CLAMP
is not active, the Vbias1 circuit is put in a stand-by
mode, reducing the supply current by about 1 mA.
When CLAMPopt=1, the Vbias1 circuit always runs at
full power.
During the black reference phase of each CCD pixel, the
φ1 (Sample Black Reference) switches are turned on,
shorting the CDSamp inputs to a second bias level
(Vbias2). The Coarse Offset DAC adds an adjustment
to the bias level (Vbias2) to cancel black level offset in
the CCD signal. When the φ1 switches turn off, the pixel
black reference level is held on the internal black
sample capacitors, and the CDSamp is ready to gain up
the CCD video signal.
The internal timing signals φ1, φ2, and φ3, which are
generated from SBLK and SPIX, control the sampling
switches shown in Fig. 6. φ3 (reset reject switches) are
closed to simplify the operation described below.
At the beginning (or end) of every video line, the DC
restore switch forces one side of the external capacitors to an internal bias level (Vbias1=1.2V). The DC
restore switch is controlled by the combination of the
CLAMP input signal ANDed with the φ2 clock.
During the video phase of each CCD pixel, the difference between the pixel black level and video level is
transmitted through the internal black sample capacitors and converted to a fully differential signal by the
CDSamp. At this time, the φ2 (Sample Pixel value)
switches turn on, and the internal video sample capacitors track the amplified difference. The Fine Offset DAC
adds offset adjustment to the PGA2 output (post gain).
V b ias2
CDS
External
DC blocking
capacitors
PGA
Coarse
O ffset
DAC
φ1
φ3
internal
A D C C lock
φ2
Fine
O ffset
DAC
CCDin
CCD
Internal
black sample
capacitors
C1
R E F in
CDS
amp
C2
CLAMP
φ2
Internal
video sam p le
capacitors
DC restore switches
V b ias1=1.2V
Figure 6. CDS and PGA Block Diagram
Rev.1.01
15
PGA1
PGA2
XRD98L63
One Volt Input Option
For gain codes ≥ 640, the gain is fixed at 36 dB. The
gain increases by 6dB (a factor of 2x) every 128 codes.
This should help simplify DSP algorithms and control.
The CDS amp is designed to normally handle a maximum signal of 800mV (VBLACK - VVIDEO). The One Volt
option allows the CDS amp to handle up to 1.0V with no
distortion. The One Volt option is enabled by writing a
1 to the "OneV" bit in the Control register.
An example of setting the gain is as follows: if the CCD
input is limited to 800mVpp (CDSVIN) and the ADC full
scale differential input (VID) is 1.8Vpp, then a minimum gain is calculated by:
Programmable Gain Amplifier (PGA)
The PGA provides gains from 6 dB to 36 dB in
approximately 0.047 dB steps. The desired gain setting is programmed via the 10 bit gain register in the
Serial Interface.
 VID 
 1.8V 
Gain = 20 log
 = 20 log
 = 7.04dB
 CDSVin 
 0.8V 
The gain code would be set to 22 (decimal) for a PGA
gain of 7.03 dB.
For gain codes between 0 and 639, the gain can be
calculated by the following equation:
 Code

Gain[ dB ] = 
× 30  + 6
 640

36
PGA gain [dB]
30
24
18
12
Gain code, PGA00[9:0]
1024
640
512
384
256
0
128
6
Figure 7. PGA Gain vs. Gain Code
Rev.1.01
16
XRD98L63
CDS By-Pass Mode
When using the CDS By-Pass mode, the calibration
logic must be put in either the Hold mode or the ManCal
mode. In the CDS By-Pass mode, the Coarse Offset
DAC does not affect the input, but the Fine Offset DAC
does affect the PGA output. The calibration logic is not
aware that the Coarse Offset DAC is not active, and will
cause errors if left operating in the automatic mode.
The CDS By-Pass mode connects the CCDin and
REFin pins directly to the CDS amp inputs, by-passing
the CDS switching function. This mode is useful for
testing the PGA/ADC with a simple differential or a
single-ended signal.
To enable the CDS By-Pass mode, write a “1” to the No
CDS bit in the Test register. This will disable the CDS
switching functions and turn on switches which connect
the CCDin & REFin pins directly to the CDS amp inputs.
To simplify signal interfacing when using the CDS ByPass mode, write a “1” to the nofs2 bit in the Test
register. This will disable the ½ scale offset introduced
at the PGA ouput (this offset is required for CCD signal
digitization).
In the CDS By-Pass mode, the SPIX signal is required
to clock the switched-capacitor PGA stages, and
ADCLK is required to clock the ADC. The PGA analog
output does not come out to any pin; the ADC digital
output must be monitored instead.
When using the CDS By-Pass mode, the ADC digital
output code will be related to the inputs by the transfer
function below:
ADCout = 2048 + [PGAgain× (REFin − CCDin ) + FineOffsetDAC]×
4096
2(CapP − CapN )
Sample N
Input Signal
Sample N+1
REFin-CCDin
PGA1 tracks
Input Signal
SPIX
non-overlap
ADCLK
DB[11:0]
PGA2 tracks
PGA1 output
Data N-8
ADC tracks
PGA2 output
Data N-7
Figure 8. CDS By-Pass Mode Timing
Rev.1.01
17
tDL
Data N-6
XRD98L63
ANALOG TO DIGITAL CONVERTER (ADC)
Direct ADC Input Mode
The analog-to-digital converter is based on pipeline
architecture with a built in track & hold input stage. The
track & hold and ADC conversion are controlled by the
externally supplied ADCLK.
The Direct ADC Input mode connects the CCDin &
REFin pins directly to the ADC inputs, by-passing the
CDS & PGA circuits. To enable the Direct ADC Input
mode, use the Serial Interface to program:
The polarity of the ADCLK is programmable. If
ADCpol=low, the track & hold circuit tracks the PGA
output while ADCLK is high and holds while ADCLK is
low. If ADCpol=high, the track & hold circuit tracks the
PGA output while ADCLK is low and holds while ADCLK
is high. ADCLK should be a 50% duty cycle clock, and
should be synchronized with SBLK such that ADC
tracking ends at the same time as the CDS sample
black ends. (See Figure 16).
ADCin=1 in the Test register,
DOclamp=0 in the Clock register, and
MinClip=0 in the Control register.
In this mode, the PGA outputs are disabled so there is
no contention at the ADC input nodes. For best performance, we recommend using fully differential signals
with a common mode level around 1.2V.
The ADC reference levels, Vcm, CapP & CapN, are
generated from an internal voltage reference. To minimize noise, these pins should have high frequency
bypass capacitors to AGND. The value of these capacitors will affect the time required for the reference to
charge up and settle after power-down mode.
The ADC output bus, DB[11:0], has 3-state capability
controlled by the OE bit of the Control register and pin
42, OE. The output bus is enabled when both the OE bit
is high and the OE pin is low. The outputs become high
impedance when either the OE bit is low or the OE pin
is high.
Sample N
Input Signal
Sample N+1
REFin-CCDin
ADC tracks
Input Signal
ADCLK
tD L
DB[11:0]
Data N-7
Data N-6
Figure 9. Direct ADC Input Mode Timing
Rev.1.01
18
Data N-5
XRD98L63
BLACK LEVEL OFFSET CALIBRATION
To get the maximum color resolution and dynamic
range, the XRD98L63 uses a digitally controlled calibration circuit to correct for offset in the CCD signal as
well as offset in the CDS, PGA & ADC signal path. This
calibration is done while the CCD outputs Optical Black
(OB) pixels.
CCD
signal
PGA
Offset
Adjust
CDS
12-bit
ADC
Reg
In the default "Line" timing mode, OB pixels are
sampled when CAL is active at the start, or end, of
each CCD scan line. CAL can be programmed to be
active high or active low; please see the Timing section
for more details about clock polarity. Averaging will
span as many lines as needed to get the number of OB
pixels programmed by Avg[1:0]. Updates to the offset
DACs occur during the Optical Black pixel time after a
complete iteration. A complete iteration includes the
pixel clipping, averaging, calculation of the offset
difference, and calculation of the DAC update values.
After a complete iteration, the averager is reset, and
the logic waits for the number of lines programmed in
the “Wait A” & “Wait B” registers, WL[11:0], before
starting the next iteration.
DB[11:0]
Black Level
Offset Calibration
Loop
+
Offset Calibration
Logic
OB[7:0]
-
Figure 10. Simplified Block Diagram of
Black Level Offset Calibration Loop
D9
X
X
D8
X
X
D7
0
0
X
X
X
X
1
1
Offset Register
D6
D5
D4
0
0
0
0
0
0
.
.
.
1
1
1
1
1
1
D3
0
0
D2
0
0
D1
0
0
D0
0
1
1
1
1
1
1
1
0
1
ADC Output
Black Level (LSB)
0
1
.
.
.
254
255
Table 3. Black Level Output Control
Hot Pixel Clipper
Pixel Averager
CCD’s occasionally have hot pixels. These are defective pixels, which always output a bright level. To
ensure the Black Level is not affected by hot pixels in
the OB area, the Hot Pixel Clipper limits pixel data from
the ADC to a maximum value of 511 (1FFh). This
clipping only affects the data used by the internal
calibration logic. Data on the ADC output bus,
DB[11:0], is not clipped.
After the clipper, the logic takes an average of the
Optical Black pixels. The number of pixels to be
averaged can be selected as one of the following: 32,
64, 128, or 256. The Avg[1:0] bits in the Calibration
register are used to program the number of pixels to
average. This averaging function filters out noise and
prevents image artifacts. The calibration logic will
average OB pixels over as many lines as required to get
the programmed number of pixels to average.
C lip p e r O u tp u t
4 0 9 6
In the Multiple Gain Mode, the logic keeps separate
avarages for even and odd lines.
5 1 1
0
0
5 1 1
2 0 4 8
A D C
4 0 9 6
D a ta
Avg[1]
Avg[0]
0
0
1
1
0
1
0
1
# of Pixels
to Average
32
64
128 (default)
256
Table 4. Programming the Pixel Averager
Figure 11. Hot Pixel Clipper
Rev.1.01
19
XRD98L63
Gain[9:0]
+
CDAC
CDS
ManCAL
CDE, CDO
Even & Odd
Coarse
Accumulators
PGA
+
12-bit ADC
Reg
DB[11:0]
FDAC
CCD
signal
Even & Odd
Fine
Accumulators
B lack Level
O ffset Calibration
Loop
Hot Pixel
C lipper
FDE, FDO
From Serial
Interface
Registers
W L[11:0]
DNS
Filter
Offset Calibration Logic
OBL[11:0]
+
+
Pixel
Averager
Mode
Avg[1:0]
OBdel[2:0]
Hold
DNS[1:0]
OB[7:0]
From Gain Logic
Gain[9:0]
Figure 12. Detailed Block Diagram of the Black Level Offset Calibration Logic
Offset Difference
Calibration Options
Next, the Offset register value, OB[7:0], is subtracted
from the OB pixel average. If the difference is positive,
the offset DACs are adjusted to reduce the effective
ADC output code. If the difference is negative, the
offset DACs are adjusted to increase the effective ADC
output code. The DNS option will affect how the DAC
adjustments are made.
Digital Noise Suppression (DNS) Filter
The purpose of this option is to eliminate small
changes in the Black Level offset by making the
calibration system less sensitive to small changes in
the measured offset. In this mode, the user has the
option of selecting from three filter settings, see Table 5.
DNS[1]
0
0
1
1
Coarse & Fine Accumulators
The Coarse and Fine Accumulators are the registers
which hold the digital codes for the Coarse and Fine
Offset DACs. The Offset DAC adjustments are made
by adding to or subtracting from the value in the Fine
accumulator. If there is an overflow or underflow in the
Fine Accumulator, the Fine Accumulator is reset to it’s
mid-scale value, and the Coarse Accumulator is
incremented or decremented accordingly.
DNS[0]
0
1
0
1
DNS Filter Width
OFF
Narrow (default)
Medium
Wide
Table 5. DNS Threshold Programming
To activate the Digital Noise Suppression mode, write
to the DNS[1:0] bits in the Calibration register.
By default, the Digital Noise Suppression is ON and set
to the narrow filter width.
In the Multiple Gain Mode, there are separate accumulators for even and odd lines.
Rev.1.01
20
XRD98L63
Hold Mode
The purpose of this mode is to prevent any changes in
the Fine or Coarse accumulators. This mode is intended to optimize digital still camera applications
(DSC). The idea is to first run the calibration normally
so the Fine and Coarse accumulators converge on the
correct values to achieve the programmed Offset
Code. Then, just before acquiring the final image data,
activate the Hold mode. This will ensure the black level
offset of the CDS/PGA does not change while the final
image is being transferred out of the CCD. Once the
image has been acquired from the CCD, turn off the
Hold mode so the chip can continue to compensate for
any changes in offset due to temperature drift or other
effects.
If the Multiple Gain Mode is enabled, then the CDAC
Odd register and the FDAC Odd register are also used
to program the Offset Adjust DACs.
To activate the Manual mode, write a ”1” to the ManCal
bit in the Calibration register. By default, the Manual
mode is not active.
Ignoring Fringe Pixels
Fringe pixels are the first few OB pixels at the edge of
the metal shield. Usually, these pixels receive some
reflected and/or scattered light, so they do not represent true “Optical Black”. If the CAL signal is active
while the CCD outputs Fringe pixels, the Calibration
logic will not converge properly. The OBdel[1:0] parameter can be used to tell the Calibration logic to ignore (or
delete) the first 0-3 OB pixels every time the CAL signal
is activated.
To activate the Hold mode, write a “1” to the CAL Hold
bit in the Calibration register. By default, the Hold
mode is not active.
Manual Mode
The purpose of the Manual Mode is to disable the
automatic calibration feature and allow a system to
write directly to the Coarse and Fine Offset Adjust
DACs. When Manual mode is enabled, the Coarse
Offset DAC (CDAC) is programmed by writing to the
CDAC Even register, CDE[8:0]; the Fine Offset DAC is
programmed by writing to the FDAC Even register,
FDE[9:0].
OBdel[1:0]
00
01
10
11
Number of
Fringe Pixels
to Ignore
0
1
2
3
Table 6. Ignoring Fringe Pixels
Light
Metal Shield
CCD
V
V
V
V
Active Video pixels
Fr
Fr
Fr
Fringe pixels
OB OB OB OB OB OB OB OB OB OB OB
Good Optical Black pixels
CAL
Ignore these 3 pixels by
setting OBdel[1:0]=11
Figure 13. Example of Ignoring Fringe Pixels Using OBdel[2:0]
Rev.1.01
21
XRD98L63
TIMING: CLOCK BASICS
Clock Polarity
There are 8 clock signals SBLK, SPIX, ADCLK,
CLAMP, CAL, PBLK, EOS and Fsync.
Each of the 8 clock pins has a separate polarity control
bit in the Polarity register. If the polarity bit for a clock
is low, then the clock is active low. If the polarity bit for
a clock is high, then the clock is active high. After reset
(by POR, Reset bit or XRESET pin), all clocks default
to active low; EOS defaults to active high.
The pixel rate clocks are SBLK, SPIX, and ADCLK.
SBLK controls sampling of the Black reference level
for each pixel. SPIX controls sampling of the Video
level for each pixel. ADCLK controls the ADC sampling
of the PGA output and ADC operation.
The line rate clocks are CLAMP, CAL, PBLK and EOS.
CLAMP controls the DC restore function for the external AC coupling capacitors. CAL controls the Black
level calibration by defining the OB pixels at the start
or end of each line. In the One Shot mode (CAL only),
CLAMP is not used. PBLK is used to disconnect the
CDS from the CCDin & REFin pins during vertical shift
time. If the DOclamp bit in the Clock register is high,
PBLK will also force the digital output bus, DB[11:0], to
output the value in the Offset register, OB[7:0]. EOS
is used in the Multiple Gain mode to indicate if a line (or
field) is even or odd.
SBLK
SPIX
ADCLK
CLAMP
CAL
PBLK
EOS
Fsync
Polarity
Aperture
Delays
AFE
Clock
Logic
ADC
Calibration
Figure 15. Clock Polarity & Aperture Delays
Pipeline Delay
The digital outputs, DB[11:0] and OVER, are synchronized to ADCLK. When ADCLKpol=0 (default), the
digital outputs change on the rising edge of ADCLK.
Figure 14 shows the pipeline delay (latency) from
sampling a pixel at the CDS input, until the corresponding data is available at the digital output.
Pixel N
Pixel N+1
Black Level
Video
Level
CCD
Signal
sample
black
SBLK
sample
video
SPIX
sample
sample PGA2out
PGA1out
ADCLK
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bits 1&0
error
correction
t DL
DB[11:0]
Pixel N-8
Pixel N-7
Pixel N-6
Pixel N-5
Pixel N-4
Pixel N-3
Pixel N-2
7.5 Pixel Pipeline Delay
Figure 14. Pixel Timing Showing Pipeline Delay
Rev.1.01
22
Pixel N-1
Pixel N
XRD98L63
PIXEL RATE CLOCKS SBLK, SPIX & ADCLK
(pixel "N")
(pixel "N+1")
tPIX
Black Sample Point
CCD
Signal
tBK
tVD
Video Sample Point
tPW1
SBLK
tPW2
SPIX
ADCLK
tDL
DB[11:0]
Data N-8
Data N-7
Figure 16. Detailed Pixel Rate Clock Timing for Default Register Settings
Note:
The timing descriptions in this section are
correct for the default conditions:
All Polarity bits = 0,
RSTreject = 0 (switch always ON),
SPIXopt = 0
PGA2 and the ADC form an analog pipeline controlled
by ADCLK. When ADCLK is high, PGA2 is sampling the
output of PGA1. When ADCLK goes low, PGA2 gains
up the sampled signal and the first stage of the ADC
samples the output of PGA2. ADCLK should be as
close as possible to 50% duty cycle.
Sampling of the pixel black level is controlled by the
SBLK pulse. When SBLK is low, tPW1, the internal
sample black switches in the CDS are ON, sampling the
pixel black level on the internal black sample capacitors.
If your timing generator does not provide a clock signal
suitable for ADCLK, there is an option to generate
ADCLK internally. Write a "1" to the "ADCLKsel" bit in
the Clock register. This will generate an internal
ADCLK based on the SBLK and SPIX clock signals.
We recommend that the ADCLK pin be tied to ground
when the ADCLKsel option is used.
Sampling of the pixel video level is controlled by the
SPIX pulse. When SPIX is low, tPW2, the video signal
propagates through the CDS amp and is sampled on the
internal video sampling capacitors. When SPIX goes
high, PGA1 gains up the signal from the video sample
capacitors.
Rev.1.01
23
XRD98L63
SPIXopt
When SPIXopt = 1 (Figure 18), φ2 is generated from a
combination of SBLK and SPIX. φ2 will turn ON the
internal sample video switches by a programmed delay
after the SBLK pulse ends. The turn ON delay is
programmed by the addition of SBdly[5:3] and
SPdly[8:6]. φ2 will turn OFF the sample video switches
at the end of the SPIX pulse.
In the default case (Figure 17) SPIXopt=0, the signal
controlling the internal Sample Video switches, φ2, is
generated from only the SPIX pulse. This mode is
intended for camera systems where the designer has
the ability to externally fine tune both the rising and
falling edges of SPIX to achieve the best performance.
Black Level
CCD Signal
Video
Level
SBLK
SPIX
ADCLK
φ2
Figure 17. Pixel Rate Clock Timing with SPIXopt=0 (Default)
Black Level
CCD Signal
Video
Level
SBLK
SPIX
ADCLK
SBdly[5:3] + SPdlyB[8:6]
φ2
Figure 18. Pixel Rate Clock Timing with SPIXopt=1
Rev.1.01
24
XRD98L63
Reset Reject
When RSTreject = 1, the reset reject switches are
turned OFF at the end of the SPIX pulse and turned ON
again at the start of the SBLK pulse. This will effectively reject the reset pulse and prevent it from railing
the PGA.
In the default state, the reset reject switches (φ3) are
always ON; they are not clocked. The reset pulse of
each pixel is transmitted to the first stage of the PGA.
Depending on the PGA gain and the actual voltage
level of the reset pulse, this could cause the first stage
of the PGA to rail. During the Black Level sampling, the
PGA should have enough time to recuperate, but as a
precaution, we have included the Reset Reject option.
Reset Reject
Switches Turn OFF
Black Level
CCD Signal
Video
Level
SBLK
SPIX
ADCLK
φ3
Figure 19. Pixel Rate Clock Timing with RSTreject=1
Rev.1.01
25
XRD98L63
Aperture delays
The ADCdly register is divided into two 4-bit delay
parameters, ADCdly[3:0] and ADCdly[7:5]. Each can
add from 0 to 7.5 ns of delay in 0.5 ns steps.
One of the most difficult tasks in designing a digital
camera is optimizing the pixel timing for the CCD, CDS
and ADC. We have included the programmable aperture delay function to help simplify this job.
ADCdly[3:0] controls the delay added to the leading
edge of ADCLK. This positions the falling edge of the
internal signal φ4.
There are three serial interface registers, SBLKdly,
SPIXdly, and ADCdly, used to program the aperture
delays. Each register is divided into 2 or 3 delay
parameters.
ADCdly[7:4] controls the delay added to the trailing
edge of ADCLK. This positions the rising edge of the
internal signal φ4.
The delays are added to the clock signals after the
polarity control. This means the definition of leading
edge and trailing edge of the external clock signals
(SBLK, SPIX & ADCLK) depends on the polarity
control bit for each clock. For the default case,
SBLKpol=0, SPIXpol=0 & ADCpol=0, the leading edge
is the falling edge and the trailing edge is the rising
edge.
The SBLKdly register is divided into two 3-bit delay
parameters, SBdly[2:0] and SBdly[5:3]. Each can add
from 0 to 7 ns of delay in 1 ns steps.
SBdly[2:0] controls the delay added to the leading
edge of SBLK. This positions the rising edge of the
internal signal φ1.
SBdly[5:3] controls the delay added to the trailing edge
of SBLK. This positions the falling edge of the internal
signal φ1.
The SPIXdly register is divided into three 3-bit delay
parameters, SPdly[2:0], SPdly[5:3] and SPdly[8:6].
Each can add from 0 to 7 ns of delay in 1 ns steps.
SPdly[2:0] controls the delay added to the leading
edge of SPIX. This positions the rising edge of the
internal signal φ2.
SPdly[5:3] controls the delay added to the trailing edge
of SPIX. This positions the falling edge of the internal
signal φ2.
SPdly[8:6] is only used when SPIXopt=1. It controls
the delay from the trailing edge of SBLK to the rising
edge of the internal signal φ2. This delay is in addition
to SBdly[5:3], the SBLK trailing edge delay.
Rev.1.01
26
XRD98L63
tPIX
Black Sample Point
CCD
Signal
tBK
Video Sample Point
tVD
SBdly[2:0]
SBLK
SBdly[5:3]
φ1
SPIX
SPdly[2:0]
φ2
SPdly[5:3]
ADCLK
ADCdly[3:0]
φ4
ADCdly[7:4]
Figure 20. Effects of Aperture Delays with SPIXopt=0 (Default)
tPIX
Black Sample Point
CCD
Signal
tBK
tVD
SBdly[2:0]
Video Sample Point
SBLK
φ1
SBdly[5:3]
SPIX
SPdly[5:3]
φ2
SBdly[5:3] + SPdly[8:6]
ADCLK
ADCdly[3:0]
ADCdly[7:4]
φ4
Figure 21. Effects of Aperture Delays with SPIXopt=1
Rev.1.01
27
XRD98L63
LINE RATE CLOCKS
PBLK (Pre-Blanking Clock)
CLAMP, CAL & PBLK are the three line rate clock
signals. There are two modes of operation for these
clocks, the CAL & CLAMP mode, and the CALonly
mode.
The function of PBLK is the same in both CAL and
CLAMP mode and CAL-Only (One Shot) mode. It is
used to disconnect the CDS from the CCD input signal
during the vertical shift time between CCD lines. If
PBLK and CAL overlap, the CAL signal will overide so
that black level calibration can take place.
EOS can be a line rate clock as well, but it is only used
in the Multiple Gain mode. Please refer to the Multiple
Gain mode section for information about EOS.
If the DOclamp (digital output clamp) option is enabled,
PBLK will also force the digital output bus, DB[11:0], to
the value in the Serial Interface Offset register,
OB[7:0].
CAL & CLAMP Mode
CAL & CLAMP is the default line timing mode
(CALonly=0). In this mode, the CLAMP signal is used
to activate the DC restore Clamp at the CDS input, and
the CAL signal is used to define the Optical Black
pixels to be used for the Black Level calibration
function. Typically the CLAMP pulse comes during the
dummy or optical black pixels at the beginning of each
scan line, and the CAL pulse comes during the longer
string of optical black pixels at the end of each scan
line. CLAMP & CAL must not be active at the same
time.
CAL-Only (OneShot) Mode
In this mode, the CAL signal is used to activate the DC
restore clamp and to define the optical black pixels for
calibration. The CAL pulse should frame the longest
group of OB pixels at either the end or beginning of
each line. The DC restore Clamp switch is turned ON
during the first four pixels of each CAL pulse. The
remaining pixels under the CAL pulse are used for
black level calibration.
Enable the CAL-Only mode by writing a "1" to the
"CALonly" bit in the Clock register.
Rev.1.01
28
XRD98L63
Start of Line N+1
End of Line N
Active Video
Pixels
OB pixels
Vertical Shift
Dummy &
OB pixels
Active Video
pixels
CCD
Signal
t CAL
CAL
(optical black)
tC L A M P
CLAMP
(DC restore)
D isconnect CDS
from input pins
PBLK
(blanking)
If PBLK overlaps with CAL and/or CLAMP, it will not affect the optical black calibration and DC restore functions.
Internally, CAL & CLAMP will overwrite PBLK.
Figure 22. Line Rate Timing with CALonly=0 (CLAMPpol=0, CALpol=0, PBLKpol=0)
Start of Line N+1
End of Line N
Active Video
Pixels
OB pixels
Vertical Shift
Dummy &
OB pixels
CCD
Signal
tC A L
CAL
Internal
(DC restore)
Internal
(optical black)
4 pixels
t C A L - 4 pixels
D isconnect CDS
from input pins
PBLK
(blanking)
Figure 23. Line Rate Timing with CALonly=1 (CALpol=0, PBLKpol=0)
Rev.1.01
29
Active Video
pixels
XRD98L63
MULTIPLE GAIN MODE
The Benefits of Multiple Gain Mode
Overview of Multiple Gain Mode
The Multiple Gain mode switches the gain of the
Programmable Gain Amplifier (PGA) at the pixel rate.
The Multiple Gain logic will switch the PGA gain
according to two user defined patterns. Each pattern
can be from one to four pixels long.
The Multiple Gain mode is designed assuming the color
filter array is made up of lines (rows) which alternate
between two different pixel patterns. We will refer to the
two patterns as the Even pattern and the Odd pattern.
In a typical camera design using an RGB CFA, the even
lines will have Red & Green alternating pixels, while the
Odd lines will have Green & Blue alternating pixels. The
XRD98L63 allows the patterns to be defined with a
single Green gain used on both Even and Odd lines, or
with two different Green gains for Even and Odd lines.
This allows a color digital camera system to set
different PGA (analog) gains for the different color
pixels. Most CCDs with RGB Color Filter Arrays (CFA)
have weaker signal response for the Blue pixels than for
Red or Green pixels. Using the Multiple Gain mode, the
Blue pixels can be amplified with higher gain than the
Red or Green pixels before being digitized by the ADC.
This allows all colors to take advantage of the full ADC
resolution.
There are three main steps to setting up and using the
Multiple Gain mode:
1) Select the appropriate Interlaced or Progressive
scan clocking mode.
2) Program the Even and Odd Line Pattern registers
to match the color filter array used on the CCD.
3) Program the Gain Registers.
Enable the Multiple Gain mode by writing a "1" to the
"MultGain" bit in the Control register.
Even Line Pattern
ELP1[1:0]
ELP2[1:0]
ELP3[1:0]
ELP4[1:0]
PRE[1:0]
01
R
Gr
10
11
00
01
CDS
PGA
ADC
CAL
Even Pixel Repeat
Counter
0 to PRE[1:0]
10
11
0
PGA mux
SBLK
00
1
01
11
1
0
+
00
10
11
+
+
01
+
Σ
Σ
−
Gr
odd pattern G b B
E x a m p le pattern
P G A 11 D ifference
−
P G A 10 D ifference
R
OLP4[1:0]
OLP3[1:0]
OLP2[1:0]
OLP1[1:0]
P G A 01 D ifference
Odd Line Pattern
B
−
−
P G A 00 M aster
Gb
P R O [1:0]
Σ
Σ
Σ
−
B
Gb
R
Gr
Figure 24. Block Diagram of the Multiple Gain Logic
Rev.1.01
30
O B O dd G ain
01
01
O B E ven G ain
00
+
Line
P attern
S elect
Odd Pixel Repeat
Counter
0 to PRO[1:0]
even pattern
10
Line
Pattern
S e lect
XRD98L63
Select Clocking Mode
PRE[1]
PRO[1]
0
0
1
1
The Multiple Gain Mode logic needs to know if the
current scan line is using the Even or the Odd line
pattern. You will select one of four clocking modes
depending on the signals available from your timing
generator and whether the CCD is being clocked in a
progressive or interlaced mode.
Progressive Scanning
In the Progressive scan mode, the CCD outputs alternating Even and Odd lines. Set MGsel[0]=1.
PRE[0]
PRO[0]
0
1
0
1
Number of pixels in pattern
1
2 (default, typ RGB CCD)
3
4
Table 7. Pattern Repeat Programming
ELP1[1:0] through ELP4[1:0] are used to define which
gain register is used for each pixel in the repeated
pattern for Even lines. Each of these 2 bit wide parameters is a pointer to one of the four PGA gain registers.
Likewise, OLP1[1:0] through OLP4[1:0] are used to
define which gain register is used for each pixel in the
repeated pattern for Odd lines.
If your timing generator provides a Line ID signal which
is low for Even lines and high for Odd lines, then
connect this signal to EOS, pin 18, and set MGsel[1]=0.
If your timing generator does not provide a Line ID
signal, then connect EOS (pin 18) to the Horizontal
sync signal (typically called HD), connect Fsync (pin
24) to the Vertical Sync signal (typically called VD), and
set MGsel[1]=1. This mode uses an internal line
counter. At the start of every frame, the Fsync signal
resets this counter to the value of the MGstart bit in the
Control register. Then on every scan line, the PBLK
pulse will toggle the value in the counter.
Programming the Gain Registers
The Multiple Gain mode can switch between any of four
different PGA gains. In a typical digital camera, using
a CCD with a standard RGB CFA, the Even lines will use
2 gains and the Odd line will used 2 gains.
The Multiple Gain logic includes 6 gain registers.
Interlaced Scanning
In the interlaced scan mode, the CCD outputs all the
Even lines during one field, and all the Odd lines during
the next field. Set MGsel[0]=0.
PGA00 is the 10-bit wide, Master Gain register. It
should be assigned to the color which will require the
highest gain (usually this is Blue).
PGA01, PGA10, & PGA11 are the 9-bit wide Gain
Difference registers. The value programmed into any of
these registers is first subtracted from the value in the
PGA00 register before being sent to the analog PGA.
If your timing generator provides a Line ID signal which
is low for Even lines and high for Odd lines, then
connect this signal to EOS, pin 18, and set MGsel[1]=0.
If your timing generator changes the timing relationship
of the Vertical and Horizontal sync signals to indicate
which fields are Even and which are Odd, then connect
EOS (pin 18) to the Horizontal sync signal (typically
called HD), connect Fsync (pin 24) to the Vertical Sync
signal (typically called VD), and set MGsel[1]=1.
OBE (OB Even) and OBO (OB Odd) are also 9-bit wide
Gain Difference registers. These registers are used to
set the gain applied to the Optical Black pixels during
Black Level Calibration.
As described in the Programmable Gain Amplifier
section, the PGA is programmed on a dB scale, where
1 LSB = 0.047 dB. A constant gain difference on a dB
scale is a constant gain ratio on a linear scale.
Programming the Line Pattern Registers
Even Line & Odd Line are the Line Pattern registers.
Each is divided into 5 parameters. The default values
work with RGB CFAs which have Red-Green pixel lines
alternating with Green-Blue pixel lines.
This system of a Master Gain register along with
multiple Gain Difference registers on a dB scale, allows
a camera system to set the desired gain ratios between
all the different colors. Then, the camera can write
values to the Master Gain register (to compensate for
changes in the ambient light level), and the gains of all
the other colors will automatically be adjusted to maintain the desired gain ratios.
PRE[1:0] (Even Line) and PRO[1:0] (Odd Line) are the
pixel repeat parameters. The number of pixels in the
repeated pattern for Even/Odd lines is selected by
programming PRE[1:0]/PRO[1:0] as shown in table 5.
Rev.1.01
31
XRD98L63
MGsel
Functions
00
Sony Interlaced
01
Sony Progressive
10
Panasonic Interlaced
11
Panasonic Progressive
TG
Signal
Name
(Sony Progressive mode)
Exar
Name
Frame "N"
* Line Pattern
Select
0
1
0
0
CCD
VD
FSYNC
ID
EOS
PBLK
PBLK
OBCLP
CAL
CLPDM
CLAMP
Frame "N+1"
1
0
1
0
1
1
2
3
4
5
0
1
0
0
1)
1
0
1
0
1
1
2
3
4
5
1)
CONDITIONS: FSYNCpol=0, PBLKpol=0, CALpol=0, CLAMPpol=0, EOSpol=1
* Internal signals
1) PBLK latches EOS value into Line Pattern Select.
Figure 25. Multiple Gain Mode Timing, Progressive, MGsel[1:0] = 01
TG
Signal
Name
(Panasonic Progresive mode)
Exar
Name
* Line Pattern
Select
MGstart = 0
CCD
VD
FSYNC
HD
EOS
PBLK
PBLK
CPOB
CAL
HCLR/CLPD
CLAMP
1
0
1
0
1
1
2
3
4
5
1)
MGstart = 1
0
1
0
1
0
1
2
3
4
5
1)
2)
2)
CONDITIONS: FSYNCpol=1, PBLKpol=1, CALpol=1, CLAMPpol=1, EOSpol=1
* Internal signals
1) FSYNC resets Line Pattern Select to "MGstart" bit value.
2) PBLK toggles Line Pattern Select value.
Figure 26. Multiple Gain Mode Timing, Progressive, MGsel[1:0] = 11
Rev.1.01
32
XRD98L63
TG
Signal
Name
(Sony Interlaced mode)
Exar
Name
"A" Field
* Line Pattern
Select
1
0
1
CCD
VD
FSYNC
ID
EOS
PBLK
PBLK
OBCLP
CAL
CLPDM
CLAMP
"B" Field
3
5
0
7
1
9
2
1)
4
6
8
10
8
10
1)
CONDITIONS: FSYNCpol=0, PBLKpol=0, CALpol=0, CLAMPpol=0, EOSpol=1
* Internal signals
1) PBLK latches EOS value into Line Pattern Select.
Figure 27. Multiple Gain Mode Timing, Interlaced, MGsel[1:0] = 00
TG
Signal
Name
(Panasonic Interlaced mode)
Exar
Name
Odd Field
* Line Pattern
Select
1
1
CCD
VD
FSYNC
HD
EOS
PBLK
PBLK
CPOB
CAL
HCLR/CLPD
CLAMP
Even Field
3
1)
5
1
7
9
0
2
4
6
1)
2)
2)
CONDITIONS: FSYNCpol=1, PBLKpol=1, CALpol=1, CLAMPpol=1, EOSpol=1
* Internal signals
1) FSYNC latches EOS value.
2) PBLK updates Line Pattern Select to the latched EOS value.
Figure 28. Multiple Gain Mode Timing, Interlaced, MGsel[1:0] = 10
Rev.1.01
33
XRD98L63
OTHER CHIP CONTROLS & FEATURES
Chip Power Down
Minimum Clip
The Power Down mode can be activated by forcing the
PD pin high, or by writing a “1” to the CHIPpd bit in the
Control register. For normal operation, the PD pin must
be low and the CHIPpd bit must be “0”. In the Power
Down mode, all analog circuits are turned off, and the
output bus, DB[11:0], is put in the high impedance
mode. All the digital registers retain their values, so the
PGA gain, offset, and calibration will return to their
previous states. The serial interface pins remain active
in the Power Down mode. The PD pin and the CHIPpd
bit do not reset any internal registers.
The Minimum Clip feature helps reduce noise in black
areas of a digitized image by clipping ADC output data,
such that the minimum code out is the code programmed in to the Offset register, OB[7:0].
In addition to the CHIPpd bit, there are two other power
down bits which only turn off portions of the chip.
AFEpd controls the CDS & PGA circuits. ADCpd
controls the ADC. AFEpd & ADCpd are included for
factory test and characterization purposes, they are not
intended for use in digital camera applications.
Digital Output Clamp
When MinClip=1 (the default condition), the digital
output data will be clipped such that:
DB[11:0] ≥ OB[7:0]
This feature does not clip the data used by the internal
Black level Calibration Logic.
The PBLK (Pre-Blanking) clock is used to disconnect
the CDS inputs from the CCD signal during vertical shift
time. When DOclamp=1 (the default condition), PBLK
is also used to force the digital output data to the code
stored in the Offset register, OB[7:0].
Digital Output Enable Control
If (DOclamp=1) AND (PBLK=active)
THEN DB[11:0] = OB[7:0]
The ADC digital output bus, DB[11:0], has 3-state
capability. When the OE bit in the control register is
high, and the OE Pin (pin 42) is low, the digital output
drivers are enabled and active. When the OE bit is low,
or the OE pin is high, the digital output drivers are
disabled and the bus is in the high impedance state.
Setting Power and Performance with Rext
The power and performance levels of the
XRD98L63 are set by the value of Rext. Rext sets
the current bias level for the entire chip. Rext is
connected between pin 37 (BiasRes) and analog
ground (see Figure 29). This resistor should be
placed as close as possible to the pin and routed
directly to a ground plane in a PCB layout. A
surface mount carbon resistor is recommended.
The OE bit and OE pin only control the digital output
drivers, all other circuits on the chip will remain active.
The black level calibration can still run properly when
the outputs are in the high impedance state.
Chip Reset
Increasing the value of Rext will decrease the
power, linearity and noise performance of the
XRD98L63. Reducing the value of Rext will
improve the linearity and noise performance while
increasing power. The tested default value for
Rext is 18.2KΩ.
The chip includes a Power-On-Reset function (POR),
so when the power supplies are turned on, the chip will
always power up with default values in all registers.
There are two methods to force a chip reset. The first
is to write a “1” to the RESET bit in the reset register.
This will reset the chip, and after a delay of about 10 ns,
the reset bit will automatically clear itself. The second
reset method is to force the RESET pin (pin # 43) low.
This will reset the chip until the RESET pin goes high
again. The RESET pin has an internal pull up.
In order to match system to system performance
and set consistent manufacturable performance
levels between cameras, it is recommended that
the Rext resistor have <1% tolerance.
Rev.1.01
34
XRD98L63
15V
C1=0.1 µF decoupling capacitors at each supply pin
0.01 µF
CCD
0.01 µF
Vdd
Vdd
C1
ASIC/DSP
C1
C1
BiasRes
CapP
CapN
0.1 µF
Vdd C1
AVDD
AGND
OE
RESET
PD
TestOut
LOAD
SDI
SCLK
1
24
Fsync
CLAMP
SPIX
XRD98L63
DB0
DB1
DB2
DB3
DB4
DB5
DB6
48
REFIN
n/c
AVDD
AGND
AGND
37
SBLK
CAL
PBLK
EOS
DVDD
ADCLK
DGND
OGND
OVDD
Timing Generator
C1
Vdd
Vdd
13
DB7
DB8
DB9
DB10
DB11
18.2KΩ
25
n/c
AGND
n/c
AVDD
VCM
n/c
CCDIN
36
C1
12
12
3
3
Digital Video Input
Serial Interface
Controls
(These controls can be
accessed via the serial
interface as well)
Figure 29. Application Schematic
Rev.1.01
35
XRD98L63
80
FS = 30MHz
O
TA = 25 C
70
60
IDD, mA
50
40
.
30
20
IDD @ VDD = 2.7V
10
IDD @ VDD = 3.0V
IDD @ VDD = 3.6V
0
12
14
16
18
20
REXT, KOhms
Figure 30. IDD vs Rext
300
VDD = 2.7V
FS = 30MHz
VDD = 3.0V
VDD = 3.6V
O
TA = 25 C
Power Dissipation, mW
250
200
150
100
50
0
12
14
16
REXT, KOhms
Figure 31. Power Dissipatin vs Rext
Rev.1.01
36
18
20
XRD98L63
70
REXT = 18K
TA = 25OC
60
VDD = 3.6V
50
VDD = 3.0V
I DD, mA
40
VDD = 2.7V
30
20
10
0
12
18
24
30
FREQUENCY, MHz
Figure 32. IDD vs Frequency
180
R EXT = 18K
TA = 25OC
160
VDD = 3.6V
POWER DISSIPATION, mW
140
120
VDD = 3.0V
100
VDD = 2.7V
80
60
40
20
0
12
18
24
FREQUENCY, MHz
Figure 33. Power Dissipation vs Frequency
Rev.1.01
37
30
XRD98L63
50
Rext = 18.2KOhms
Fs = 30MHz
Vdd = 3.6V
40
Vdd = 3.0V
Vdd = 2.7V
Idd (mA)
30
20
10
0
-60
-40
-20
0
20
40
60
80
100
60
80
100
Temperature (C)
Figure 34. IDD vs Temperature
180
Rext = 18.2KOhms
Fs = 30MHz
Vdd = 3.6V
150
120
Power Diss. (mW)
Vdd = 3.0V
Vdd = 2.7V
90
60
30
0
-60
-40
-20
0
20
40
Temperature (C)
Figure 35. Power Dissipation vs Temperature
Rev.1.01
38
XRD98L63
1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
0
1024
2048
3072
4096
Figure 36. System DNL
1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
0
1024
2048
Figure 37. ADC DNL
Rev.1.01
39
3072
4096
XRD98L63
48 LEAD THIN QUAD FLAT PACK
(7 x 7 x 1.4 mm TQFP)
REV. 2. 00
D
D1
36
25
24
37
D1
13
48
1
12
B
A2
e
C
A
α
Seating Plane
A1
L
INCHES
MIN
MAX
0.055
0.063
MILLIMETERS
MIN
MAX
1.4
1.6
A1
0.002
0.006
0.05
0.15
A2
0.053
0.057
1.35
1.45
B
C
D
0.007
0.004
0.346
0.011
0.008
0.362
0.17
0.09
8.8
0.27
0.2
9.2
D1
0.272
0.28
6.9
7.1
e
L
a
0.020 BSC
0.018
0.03
0°
7°
SYMBOL
A
0.50 BSC
0.45
0.75
0°
7°
Note: The control dimension is the millimeter column
Rev.1.01
40
D
XRD98L63
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of
patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending
upon a user’s specific application. While the information in this publication has been carefully checked; no
responsibility, however, is assumed for in accuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the
circumstances.
Copyright 2002 EXAR Corporation
Datasheet June 2002
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev.1.01
41