a Complete 10-Bit 30 MSPS CCD Signal Processor AD9846A PRODUCT DESCRIPTION FEATURES 30 MSPS Correlated Double Sampler (CDS) 4 dB 6 dB 6-Bit Pixel Gain Amplifier ( PxGA®) 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Analog Preblanking Function 10-Bit 30 MSPS A/D Converter Auxiliary Inputs with VGA and Input Clamp 3-Wire Serial Digital Interface 3 V Single Supply Operation Low Power: 100 mW @ 2.7 V 48-Lead LQFP Package The AD9846A is a complete analog signal processor for CCD applications. It features a 30 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9846A’s signal chain consists of an input clamp, correlated double sampler (CDS), Pixel Gain Amplifier (PxGA), digitally controlled variable gain amplifier (VGA), black level clamp, and a 10-bit A/D converter. Additional input modes are provided for processing analog video signals. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input configuration, and power-down modes. APPLICATIONS Digital Still Cameras Digital Video Camcorders Industrial Imaging The AD9846A operates from a single 3 V power supply, typically dissipates 117 mW, and is packaged in a 48-lead LQFP. FUNCTIONAL BLOCK DIAGRAM PBLK AVDD AVSS 4dB6 dB HD VD CLPOB COLOR STEERING DRVDD CLP DRVSS CDS CCDIN 2dB~36dB PxGA 2:1 MUX ADC VGA 10 CLP 6 BANDGAP REFERENCE CLPDM 10 AUX1IN 2:1 MUX OFFSET DAC BUF INTERNAL BIAS AUX2IN DOUT VRT VRB CML 8 CONTROL REGISTERS CLP DVDD DIGITAL INTERFACE AD9846A SL SCK INTERNAL TIMING SDATA SHP SHD DVSS DATACLK PxGA is a registered trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD9846A–SPECIFICATIONS GENERAL SPECIFICATIONS (T MIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.) Parameter Min TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation Power-Down Modes Fast Recovery Mode Standby Total Power-Down Typ Max Unit –20 –65 +85 +150 °C °C 2.7 3.6 V (Specified Under Each Mode of Operation) 85 5 1 MAXIMUM CLOCK RATE mW mW mW 30 A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage Data Output Coding MHz 10 ± 0.5 Bits LSB Bits Guaranteed V ± 1.0 10 2.0 Straight Binary VOLTAGE REFERENCE Reference Top Voltage (VRT) Reference Bottom Voltage (VRB) 2.0 1.0 V V Specifications subject to change without notice. DIGITAL SPECIFICATIONS (DRVDD = 2.7 V, C = 20 pF unless otherwise noted.) L Parameter Symbol Min LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance VIH VIL IIH IIL CIN 2.1 LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA VOH VOL 2.2 Typ Max 0.6 10 10 10 0.5 Unit V V µA µA pF V V Specifications subject to change without notice. –2– REV. 0 AD9846A CCD-MODE SPECIFICATIONS (T MIN Parameter to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 30 MHz, unless otherwise noted.) Min POWER CONSUMPTION MAXIMUM CLOCK RATE CDS Gain Allowable CCD Reset Transient 1 Max Input Range Before Saturation 1 Max CCD Black Pixel Amplitude 1 PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range (Two’s Complement Coding) Min Gain (PxGA Gain Code 32) Max Gain (PxGA Gain Code 31) VARIABLE GAIN AMPLIFIER (VGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain (VGA Gain Code 91) Max Gain (VGA Gain Code 1023) POWER-UP RECOVERY TIME Fast Recovery Mode Reference Standby Mode Total Power-Down Mode Power-Off Condition Max 117 30 1.0 200 1.0 1.6 64 Guaranteed See TPC 1 for Power Curves See Input Waveform in Footnote 1 PxGA Gain at 4 dB See Figure 28 for PxGA Gain Curve –2 10 dB dB 1.6 2.0 V p-p V p-p Steps 1024 Guaranteed See Figure 29 for VGA Gain Curve 2 36 dB dB 256 Steps 0 63.75 LSB LSB Measured at ADC Output –0.5 –1 11 Specifications Include Entire Signal Chain Use Equations on Page 18 to Calculate Gain +0.5 0 12 0.1 0.2 40 +1 12 dB dB % LSB rms dB VGA Gain Fixed at 2 dB (Code 91) VGA Gain Fixed at 2 dB (Code 91) 12 dB Gain Applied AC Grounded Input, 6 dB Gain Applied Measured with Step Change on Supply Normal Clock Signals Applied 0.1 1 3 15 ms ms ms ms 1V MAX INPUT SIGNAL RANGE PxGA gain fixed at 4 dB (Code 63). Specifications subject to change without notice. REV. 0 mW V p-p V p-p Steps 500mV TYP RESET TRANSIENT 2 Note dB mV V p-p mV NOTES 1 Input Signal Characteristics defined as follows: 200mV MAX OPTICAL BLACK PIXEL Unit MHz 0 500 BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Min Clamp Level Max Clamp Level SYSTEM PERFORMANCE Gain Accuracy (VGA Code 91 to 1023) 2 PxGA Gain Accuracy Min Gain (PxGA Register Code 32) Max Gain (PxGA Code 31) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) Typ –3– AD9846A–SPECIFICATIONS AUX1-MODE SPECIFICATIONS Parameter (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.) Min Typ POWER CONSUMPTION 82 MAXIMUM CLOCK RATE 30 INPUT BUFFER Gain Max Input Range 1.0 VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain Max Unit mW MHz 0 dB V p-p 2.0 1023 V p-p Steps 0 36 dB dB Specifications subject to change without notice. AUX2-MODE SPECIFICATIONS Parameter (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.) Min Typ POWER CONSUMPTION MAXIMUM CLOCK RATE 86 30 INPUT BUFFER VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain Max Unit mW MHz (Same as AUX1-MODE) 2.0 ACTIVE CLAMP Clamp Level Resolution Clamp Level (Measured at ADC Output) Min Clamp Level Max Clamp Level 512 V p-p Steps 0 18 dB dB 256 Steps 0 63.75 LSB LSB Specifications subject to change without notice. –4– REV. 0 AD9846A (CL = 20 pF, fSAMP = 30 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7. TIMING SPECIFICATIONS Serial Timing in Figures 21–24.) Parameter Symbol Min Typ SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK Hi/Low Pulsewidth SHP Pulsewidth SHD Pulsewidth CLPDM Pulsewidth CLPOB Pulsewidth1 SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD Rising Edge Internal Clock Delay Inhibited Clock Period tCONV tADC tSHP tSHD tCDM tCOB tS1 tS2 tID tINH 32 13 5 5 4 2 0 13 33 16.7 8.3 8.3 10 20 8.3 16.7 3.0 DATA OUTPUTS Output Delay Output Hold Time Pipeline Delay SERIAL INTERFACE Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read Max Unit ns ns ns ns Pixels Pixels ns ns ns ns 10 tOD tH 7.0 fSCLK tLS tLH tDS tDH tDV 10 10 10 10 10 10 14.5 7.6 9 16 ns ns Cycles MHz ns ns ns ns ns NOTES 1 Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Specifications subject to change without notice. ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS Parameter AVDD1, AVDD2 DVDD1, DVDD2 DRVDD Digital Outputs SHP, SHD, DATACLK CLPOB, CLPDM, PBLK SCK, SL, SDATA VRT, VRB, CMLEVEL BYP1-4, CCDIN Junction Temperature Lead Temperature (10 sec) With Respect To Min Max AVSS DVSS DRVSS DRVSS DVSS DVSS DVSS AVSS AVSS –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 +3.9 +3.9 +3.9 DRVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 300 Model Unit Temperature Range AD9846AJST –20°C to +85°C V V V V V V V V V °C °C Package Option Thin Plastic Quad Flatpack (LQFP) ST-48 THERMAL CHARACTERISTICS Thermal Resistance 48-Lead LQFP Package θJA = 92°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9846A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 Package Description –5– WARNING! ESD SENSITIVE DEVICE AD9846A VRT CML THREE-STATE DVSS DVDD2 VRB NC SDATA SL NC STBY SCK PIN CONFIGURATIONS 48 47 46 45 44 43 42 41 40 39 38 37 NC NC 2 1 36 AUX1IN PIN 1 IDENTIFIER 35 AVSS 34 AUX2IN (LSB) D0 3 D1 4 33 AVDD2 D2 5 D3 6 32 BYP4 AD9846A 31 NC TOP VIEW (Not to Scale) D4 7 D5 8 30 CCDIN 29 BYP2 D6 9 D7 10 28 BYP1 D8 11 (MSB) D9 12 26 AVSS 25 AVSS CLPDM VD HD PBLK CLPOB SHP SHD DVSS DATACLK DVDD1 DRVSS 13 14 15 16 17 18 19 20 21 22 23 24 DRVDD NC = NO CONNECT 27 AVDD1 PIN FUNCTION DESCRIPTIONS Pin Number Name Type Description 1, 2 3–12 13 14 15, 41 16 17 18 19 20 21 22 23 24 25, 26, 35 27 28 29 30 31 32 33 34 36 37 38 39 40 42 43 44 45 46 47 48 NC D0–D9 DRVDD DRVSS DVSS DATACLK DVDD1 HD PBLK CLPOB SHP SHD CLPDM VD AVSS AVDD1 BYP1 BYP2 CCDIN NC BYP4 AVDD2 AUX2IN AUX1IN CML VRT VRB DVDD2 THREE-STATE NC STBY NC SL SDATA SCK DO P P P DI P DI DI DI DI DI DI DI P P AO AO AI NC AO P AI AI AO AO AO P DI NC DI NC DI DI DI Internally not Connected Digital Data Outputs Digital Output Driver Supply Digital Output Driver Ground Digital Ground Digital Data Output Latch Clock Digital Supply Horizontal Drive. Used with VD for Color Steering Control Preblanking Clock Input Black Level Clamp Clock Input CDS Sampling Clock for CCD’s Reference Level CDS Sampling Clock for CCD’s Data Level Input Clamp Clock Input Vertical Drive. Used with HD for Color Steering Control Analog Ground Analog Supply Internal Bias Level Decoupling Internal Bias Level Decoupling Analog Input for CCD Signal Internally Not Connected Internal Bias Level Decoupling Analog Supply Analog Input Analog Input Internal Bias Level Decoupling A/D Converter Top Reference Voltage Decoupling A/D Converter Bottom Reference Voltage Decoupling Digital Supply Digital Output Disable. Active High May be tied high or low. Do not leave floating. Standby Mode, Active High. Same as Serial Interface Internally Not Connected. May be Tied High or Low Serial Digital Interface Load Pulse Serial Digital Interface Data Serial Digital Interface Clock TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power. –6– REV. 0 AD9846A DEFINITIONS OF SPECIFICATIONS DIFFERENTIAL NONLINEARITY (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit resolution indicates that all 1024 codes, respectively, must be present over all operating conditions. PEAK NONLINEARITY Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9846A from a true straight line. The point used as “zero scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a Level 1, 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC’s full-scale range. TOTAL OUTPUT NOISE in LSB, and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC Full Scale/2N codes) when N is the bit resolution of the ADC. For the AD9846A, 1 LSB is 2 mV. POWER SUPPLY REJECTION (PSR) The PSR is measured with a step change applied to the supply pins. This represents a very high frequency disturbance on the AD9846A’s power supply. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage. INTERNAL DELAY FOR SHP/SHD The internal delay (also called aperture delay) is the time delay that occurs from when a sampling edge is applied to the AD9846A until the actual sample of the input signal is held. Both SHP and SHD sample the input signal during the transition from low to high, so the internal delay is measured from each clock’s rising edge to the instant the actual internal sample is taken. The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated EQUIVALENT INPUT CIRCUITS DVDD AVDD1 330 AVSS AVSS DVSS Figure 3. CCDIN (Pin 30) Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB, CLPDM, HD, VD, PBLK, SCK, SL DVDD DRVDD DATA DVDD DVDD DATA IN THREESTATE 330 DATA OUT DOUT RNW DVSS DVSS DVSS DRVSS Figure 4. SDATA (Pin 47) Figure 2. Data Outputs—D0–D9 REV. 0 –7– DVSS AD9846A–Typical Performance Characteristics 140 4 VDD = 3.3V 3 OUTPUT NOISE – LSB POWER DISSIPATION – mW 130 120 VDD = 3.0V 110 100 VDD = 2.7V 2 1 90 0 80 20 SAMPLE RATE – MHz 10 0 30 200 400 600 VGA GAIN CODE – LSB 800 1000 TPC 3. Output Noise vs. VGA Gain TPC 1. Power vs. Sample Rate 0.50 0.25 0 –0.25 –0.50 0 200 400 600 800 1000 TPC 2. Typical DNL Performance –8– REV. 0 AD9846A CCD-MODE AND AUX MODE TIMING CCD SIGNAL N tID N+1 N+2 N+9 N+10 tID SHP tS1 tS2 tCP SHD tINH DATACLK tOD OUTPUT DATA tH N–10 N–9 N–8 N–1 N NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES. Figure 5. CCD-Mode Timing EFFECTIVE PIXELS HORIZONTAL BLANKING OPTICAL BLACK PIXELS DUMMY PIXELS EFFECTIVE PIXELS CCD SIGNAL CLPOB CLPDM PBLK OUTPUT DATA OB PIXEL DATA EFFECTIVE PIXEL DATA DUMMY BLACK EFFECTIVE DATA NOTES: 1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB. 2. PBLK SIGNAL IS OPTIONAL. 3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES. Figure 6. Typical CCD-Mode Line Clamp Timing N+9 N N+1 tID VIDEO SIGNAL N+10 N+8 N+2 tCP DATACLK tOD OUTPUT DATA N–10 tH N–9 N–8 N–1 Figure 7. AUX-Mode Timing REV. 0 –9– N AD9846A PIXEL GAIN AMPLIFIER (PxGA) TIMING FRAME n VD 0101... LINE 0 HD 2323... LINE 1 FRAME n+1 0101... 0101... LINE 2 LINE m–1 LINE m LINE 0 0101... 2323... LINE 1 LINE 2 LINE m–1 LINE m NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3 Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence 5 PIXEL MIN VD HD 3ns MIN 3ns MIN SHP PxGA GAIN GAINX GAIN0 GAIN1 GAIN0 GAINX GAIN2 GAIN3 NOTES: 1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES. 2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns. 3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101. 4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323. Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing EVEN FIELD VD 0101... HD LINE 0 2323... LINE 1 ODD FIELD 0101... 0101... LINE 2 LINE m–1 LINE m LINE 0 0101... 2323... LINE 1 LINE 2 LINE m–1 LINE m NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3 Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence VD 5 PIXEL MIN HD 3ns MIN 3ns MIN SHP PxGA GAIN GAINX GAIN0 GAIN1 GAIN0 GAINX GAIN2 GAIN3 NOTES: 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. 2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101. 3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323. Figure 11. PxGA Mode 2 (Interlace) Detailed Timing –10– REV. 0 AD9846A LINE n VD LINE n+1 012012012... ...01201 012012012... HD NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2 Figure 12. PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence 5 PIXEL MIN VD 5 PIXEL MIN HD 3ns MIN SHP GAINX PxGA GAIN GAIN0 GAIN1 GAIN2 GAIN0 GAINX GAIN0 GAIN1 GAIN0 GAIN1 NOTES: 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. 2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 012012. Figure 13. PxGA Mode 3 (3-Color) Detailed Timing LINE n VD LINE n+1 01230123012... ...01230 012301230123... HD NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3 Figure 14. PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence 5 PIXEL MIN VD 5 PIXEL MIN HD 3ns MIN SHP PxGA GAIN GAINX GAIN0 GAIN1 GAIN2 GAIN0 NOTES: 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. 2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 01230123. Figure 15. PxGA Mode 4 (4-Color) Detailed Timing REV. 0 –11– GAINX AD9846A ODD FIELD VD EVEN FIELD 0101... 0101... LINE 0 HD 2323... 0101... LINE 1 LINE 2 LINE m–1 LINE m LINE 0 2323... 2323... LINE 1 LINE 2 LINE m–1 LINE m NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3 Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence VD 5 PIXEL MIN HD 3ns MIN 3ns MIN SHP GAINX PxGA GAIN GAIN0 GAIN1 GAIN0 GAINX GAIN2 GAIN3 NOTES: 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. 2. EVERY HD RISING EDGE WITH A PREVIOUS VD FALLING EDGE WILL RESET TO 0101. 3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 2323. 4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL REPEAT EITHER 0101... (EVEN) OR 2323 ... (ODD). Figure 17. PxGA Mode 5 (VD Selected) Detailed Timing FRAME n VD 0101... LINE 0 HD 1212... FRAME n+1 0101... LINE 1 LINE 2 0101... LINE m–1 LINE m LINE 0 1212... 0101... LINE 1 LINE 2 LINE m–1 LINE m NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2 Figure 18. PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence 5 PIXEL MIN VD HD 3ns MIN 3ns MIN SHP PxGA GAIN GAINX GAIN0 GAIN1 GAIN0 GAINX GAIN1 GAIN2 NOTES: 1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES. 2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns. 3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101. 4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 1212. Figure 19. PxGA Mode 6 (Mosaic Repeat) Detailed Timing –12– REV. 0 AD9846A VD HD 3ns MIN 3ns MIN SHP PxGA GAIN GAIN0 GAIN0 GAIN1 GAIN2 NOTES: 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. 2. VD = 0 AND HD = 0 SELECTS GAIN0. 3. VD = 0 AND HD = 1 SELECTS GAIN1. 4. VD = 1AND HD = 0 SELECTS GAIN2. 5. VD = 1 AND HD = 1 SELECTS GAIN3. Figure 20. PxGA Mode 7 (User-Specified) Detailed Timing REV. 0 –13– GAIN3 AD9846A SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION Table I. Internal Register Map Register Name Address A0 A1 A2 Operation 0 0 0 Channel Select Power-Down CCD/AUX1/2 Modes VGA Gain 1 0 0 LSB Clamp Level 0 1 0 LSB Control 1 1 0 Color Steering Mode Selection PxGA Gain0 0 0 1 LSB MSB PxGA Gain1 1 0 1 LSB PxGA Gain2 0 1 1 PxGA Gain3 1 1 1 D0 D1 Data Bits D3 D4 D2 D5 Software OB Clamp Reset On/Off D6 D7 D8 D9 D10 0* 1** 0* 0* 0* MSB X MSB X X X 0* 0* ThreeState X X X X X X MSB X X X X X LSB MSB X X X X X LSB MSB X X X X X PxGA On/Off Clock Polarity Select for SHP/SHD/CLP/DATA *Internal use only. Must be set to zero. **Must be set to one. RNW 0 SDATA TEST BIT A0 tDS A1 A2 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 tDH SCK tLS tLH SL NOTES: 1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK. 2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION. 3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW. 4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE. Figure 21. Serial Write Operation RNW 1 SDATA TEST BIT A0 tDS tDH A1 0 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 tDV SCK tLS tLH SL NOTES: 1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION. 2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW. 3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE FIFTH SCK FALLING EDGE, AND IS UPDATED ON SCK FALLING EDGES. Figure 22. Serial Readback Operation –14– REV. 0 AD9846A RNW A0 A1 SDATA 0 0 A2 0 0 0 11 BITS OPERATION 10 BITS ACG GAIN ... ... D0 D10 D0 ... SCK 2 1 3 4 5 8 BITS CLAMP LEVEL D9 ... D0 16 D0 17 26 ... 6 BITS PxGA GAIN0 D9 ... D0 27 34 D5 6 BITS PxGA GAIN1 D0 ... ... ... ... 6 D7 10 BITS CONTROL 35 44 ... D5 6 BITS PxGA GAIN2 D0 ... 50 51 ... D0 D5 56 57 D5 ... ... ... 45 6 BITS PxGA GAIN3 62 63 68 SL ... NOTES: 1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME. 2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER. 3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL. Figure 23. Continuous Serial Write Operation to All Registers RNW A0 A1 A2 0 0 0 1 SDATA 0 D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 PxGA GAIN3 PxGA GAIN2 PxGA GAIN1 PxGA GAIN0 D4 D5 D0 ... D5 ... D0 ... ... SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 D5 23 24 SL 29 ... Figure 24. Continuous Serial Write Operation to All PxGA Gain Registers Table II. Operation Register Contents (Default Value x000) D10 D9 D8 D7 D6 0* 0* 0* 1** 0* Optical Black Clamp D5 Reset D4 Power-Down Modes D3 D2 Channel Selection D1 D0 0 Enable Clamping 1 Disable Clamping 0 Normal 1 Reset All Registers to Default 0 0 1 1 0 0 1 1 0 1 0 1 Normal Power Fast Recovery Standby Total Power-Down 0 1 0 1 CCD Mode AUX1 Mode AUX2 Mode Test Only *Must be set to zero. **Set to one. Table III. VGA Gain Register Contents (Default Value x096) D10 MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 X 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 • • • 1 1 1 1 1 1 1 1 1 1 0 1 REV. 0 –15– Gain (dB) 2.0 • • • 35.965 36.0 AD9846A Table IV. Clamp Level Register Contents (Default Value x080) D10 D9 D8 X X X MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Clamp Level (LSB) 1 1 1 1 1 1 1 0 0 0.25 0.5 • • • 63.5 1 1 1 1 1 1 1 1 63.75 • • • Table V. Control Register Contents (Default Value x000) Data Out D10 D9 X DATACLK D8 D7 D6 0 Enable 0* 0* 1 Three-State CLP/PBLK D5 SHP/SHD D4 PxGA D3** 0 Rising Edge Trigger 0 Active Low 0 Active Low 1 Falling Edge Trigger 1 Active High 1 Active High Color Steering Modes D2 D1 D0 0 Disable 0 1 Enable 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Steering Disabled Mosaic Separate Interlace 3-Color 4-Color VD Selected Mosaic Repeat User Specified *Must be set to zero. **When D3 = 0 (PxGA disabled) the PxGA gain is fixed to 4 dB. Table VI. PxGA Gain Registers for Gain0, Gain1, Gain2, Gain3 (Default Value x000) D10 D9 D8 D7 D6 MSB D5 D4 D3 X X X X X 0 1 1 D2 D1 LSB D0 1 1 1 • • • 0 1 0 1 0 1 0 0 +10.0 • • • 0 1 0 1 0 1 • • • 1 Gain (dB)* +4.3 +4.0 • • • 0 0 0 –2.0 *Control Register Bit D3 must be set High (PxGA Enable) to use the PxGA Gain Registers. –16– REV. 0 AD9846A CIRCUIT DESCRIPTION AND OPERATION gain change on the system black level, usually called the “gain step.” Another advantage of removing this offset at the input stage is to maximize system headroom. Some area CCDs have large black level offset voltages, which, if not corrected at the input stage, can significantly reduce the available headroom in the internal circuitry when higher VGA gain settings are used. The AD9846A signal processing chain is shown in Figure 25. Each processing step is essential in achieving a high-quality image from the raw CCD pixel data. DC Restore To reduce the large dc offset of the CCD output signal, a dcrestore circuit is used with an external 0.1 µF series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V, to be compatible with the 3 V single supply of the AD9846A. Horizontal timing is shown in Figure 6. It is recommended that the CLPDM pulse be used during valid CCD dark pixels. CLPDM may be used during the optical black pixels, either together with CLPOB or separately. The CLPDM pulse should be a minimum of 4 pixels wide. Correlated Double Sampler The CDS circuit samples each CCD pixel twice to extract the video information and reject low-frequency noise. The timing shown in Figure 5 illustrates how the two CDS clocks, SHP and SHD, are used to sample the reference level and data level of the CCD signal respectively. The CCD signal is sampled on the rising edges of SHP and SHD. Placement of these two clock signals is critical in achieving the best performance from the CCD. An internal SHP/SHD delay (tID) of 3 ns is caused by internal propagation delays. PxGA The PxGA provides separate gain adjustment for the individual color pixels. A programmable gain amplifier with four separate values, the PxGA has the capability to “multiplex” its gain value on a pixel-to-pixel basis. This allows lower output color pixels to be gained up to match higher output color pixels. Also, the PxGA may be used to adjust the colors for white balance, reducing the amount of digital processing that is needed. The four different gain values are switched according to the “Color Steering” circuitry. Seven different color steering modes for different types of CCD color filter arrays are programmed in the AD9846A’s Control Register. For example, Mosaic Separate steering mode accommodates the popular “Bayer” arrangement of Red, Green, and Blue filters (see Figure 26). Input Clamp A line-rate input clamping circuit is used to remove the CCD’s optical black offset. This offset exists in the CCD’s shielded black reference pixels. Unlike some AFE architectures, the AD9846A removes this offset in the input stage to minimize the effect of a VD 3 COLOR STEERING HD PxGA MODE SELECTION 2 GAIN0 4:1 MUX DC RESTORE 6 GAIN1 GAIN2 PxGA GAIN REGISTERS INTERNAL VREF GAIN3 2V FULL SCALE 2dB TO 36dB 0.1F CCDIN CDS PxGA 10 10-BIT ADC VGA DOUT –2dB TO +10dB INPUT OFFSET CLAMP 10 CLPDM VGA GAIN REGISTER 8-BIT DAC CLPOB OPTICAL BLACK CLAMP DIGITAL FILTERING 8 CLAMP LEVEL REGISTER Figure 25. CCD-Mode Block Diagram REV. 0 –17– AD9846A for the AD9846A is 6 dB to 40 dB. The minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. When compared to 1 V full-scale systems (such as ADI’s AD9803), the equivalent gain range is 0 dB to 34 dB. MOSAIC SEPARATE COLOR STEERING MODE CCD: PROGRESSIVE BAYER R Gr R Gr LINE0 GAIN0, GAIN1, GAIN0, GAIN1 ... Gb B Gb B LINE1 GAIN2, GAIN3, GAIN2, GAIN3 ... R Gr R Gr LINE2 GAIN0, GAIN1, GAIN0, GAIN1 ... Gb B Gb B The VGA gain curve is divided into two separate regions. When the VGA Gain Register code is between 0 and 511, the curve follows a (1 + x)/(1 – x) shape, which is similar to a “linear-indB” characteristic. From code 512 to code 1023, the curve follows a “linear-in-dB” shape. The exact VGA gain can be calculated for any Gain Register value by using the following two equations: Figure 26. CCD Color Filter Example: Progressive Scan CCD: INTERLACED BAYER EVEN FIELD VD SELECTED COLOR STEERING MODE R Gr R Gr LINE0 GAIN0, GAIN1, GAIN0, GAIN1 ... R Gr R Gr LINE1 GAIN0, GAIN1, GAIN0, GAIN1 ... R Gr R Gr LINE2 GAIN0, GAIN1, GAIN0, GAIN1 ... R Gr R Gr Code Range 0–511 512 –1023 Gain Equation (dB) Gain = 20 log10 ([658 + code]/[658 – code]) – 0.4 Gain = (0.0354)(code) – 0.4 As shown in the CCD Mode Specifications, only the VGA gain range from 2 dB to 36 dB has tested and guaranteed accuracy. This corresponds to a VGA gain code range of 91 to 1023. The Gain Accuracy Specifications also include the PxGA gain of 4 dB, for a total gain range of 6 dB to 40 dB. ODD FIELD 36 B Gb B LINE0 GAIN2, GAIN3, GAIN2, GAIN3 ... Gb B Gb B LINE1 GAIN2, GAIN3, GAIN2, GAIN3 ... Gb B Gb B LINE2 GAIN2, GAIN3, GAIN2, GAIN3 ... Gb B Gb B 30 VGA GAIN – dB Gb Figure 27. CCD Color Filter Example: Interlaced The same Bayer pattern can also be interlaced, and the VD Selected mode should be used with this type of CCD (see Figure 27). The Color Steering performs the proper multiplexing of the R, G, and B gain values (loaded into the PxGA gain registers), and is synchronized by the user with vertical (VD) and horizontal (HD) sync pulses. For more detailed information, see the PxGA Timing section. The PxGA gain for each of the four channels is variable from –2 dB to +10 dB, controlled in 64 steps through the serial interface. The PxGA gain curve is shown in Figure 28. 10 PxGA GAIN – dB 8 6 4 2 0 –2 32 (100000) 40 48 56 0 8 16 24 31 (011111) PxGA GAIN REGISTER CODE Figure 28. PxGA Gain Curve Variable Gain Amplifier The VGA stage provides a gain range of 2 dB to 36 dB, programmable with 10-bit resolution through the serial digital interface. Combined with 4 dB from the PxGA stage, the total gain range 24 18 12 6 0 0 127 255 383 511 639 767 VGA GAIN REGISTER CODE 895 1023 Figure 29. VGA Gain Curve (Gain from PxGA Not Included) Optical Black Clamp The optical black clamp loop is used to remove residual offsets in the signal chain, and to track low-frequency variations in the CCD’s black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with a fixed black level reference, selected by the user in the Clamp Level Register. Any value between 0 LSB and 64 LSB may be programmed, with 8-bit resolution. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a D/A converter. Normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during the post processing, the AD9846A’s optical black clamping may be disabled using Bit D5 in the Operation Register (see Serial Interface Timing and Internal Register Description section). When the loop is disabled, the Clamp Level Register may still be used to provide programmable offset adjustment. Horizontal timing is shown in Figure 6. The CLPOB pulse should be placed during the CCD’s optical black pixels. It is recommended that the CLPOB pulse duration be at least 20 pixels wide to minimize clamp noise. Shorter pulsewidths may be used, but clamp noise may increase, and the ability to track low-frequency variations in the black level will be reduced. –18– REV. 0 AD9846A level. Signal levels above the bias level will be further increased to a higher ADC code, while signal levels below the bias level will be further decreased to a lower ADC code. A/D Converter The AD9846A uses high-performance ADC architecture, optimized for high speed and low power. Differential Nonlinearity (DNL) performance is typically better than 0.5 LSB, as shown in TPC 2. Instead of the 1 V full-scale range used by the earlier AD9801 and AD9803 products from Analog Devices, the AD9846A ADC uses a 2 V input range. Better noise performance results from using a larger ADC full-scale range (see TPC 3). AUX2 Mode For sampling video-type waveforms, such as NTSC and PAL signals, the AUX2 channel provides black level clamping, gain adjustment, and A/D conversion. Figure 31 shows the circuit configuration for using the AUX2 channel input (Pin 34). A external 0.1 µF blocking capacitor is used with the on-chip video clamp circuit, to level-shift the input signal to a desired reference level. The clamp circuit automatically senses the most negative portion of the input signal, and adjusts the voltage across the input capacitor. This forces the black level of the input signal to be equal to the value programmed into the Clamp Level register (see Serial Interface Register Description). The VGA provides gain adjustment from 0 dB to 18 dB. The same VGA Gain register is used, but only the 9 MSBs of the gain register are used (see Table VII.) AUX1 Mode For applications that do not require CDS, the AD9846A can be configured to sample ac-coupled waveforms. Figure 30 shows the circuit configuration for using the AUX1 channel input (Pin 36). A single 0.1 µF ac-coupling capacitor is needed between the input signal driver and the AUX1IN pin. An on-chip dc-bias circuit sets the average value of the input signal to approximately 0.4 V, which is referenced to the midscale code of the ADC. The VGA Gain register provides a gain range of 0 dB to 36 dB in this mode of operation (see VGA Gain Curve, Figure 29). The VGA gains up the signal level with respect to the 0.4 V bias 0.8V 0.4V ??V 5k 0.1F 0dB TO 36dB AUX1IN INPUT SIGNAL VGA MIDSCALE 10 0.4V 0.4V ADC VGA GAIN REGISTER Figure 30. AUX1 Circuit Configuration VGA GAIN REGISTER 9 0dB TO 18dB BUFFER AUX2IN VIDEO SIGNAL ADC VGA 0.1F CLAMP LEVEL VIDEO CLAMP CIRCUIT LPF 8 CLAMP LEVEL REGISTER Figure 31. AUX2 Circuit Configuration Table VII. VGA Gain Register Used for AUX2-Mode D10 X REV. 0 MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 0 1 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 1 1 1 1 X 0 • • • 1 1 1 1 1 1 –19– Gain (dB) 0.0 0.0 • • • 18.0 AD9846A APPLICATIONS INFORMATION The AD9846A is a complete Analog Front End (AFE) product for digital still camera and camcorder applications. As shown in Figure 32, the CCD image (pixel) data is buffered and sent to the AD9846A analog input through a series input capacitor. The AD9846A performs the dc restoration, CDS, gain adjustment, black level correction, and analog-to-digital conversion. The AD9846A’s digital output data is then processed by the image processing ASIC. The internal registers of the AD9846A—used to control gain, offset level, and other functions—are programmed by the ASIC or microprocessor through a 3-wire serial digital interface. A system timing generator provides the clock signals for both the CCD and the AFE. AD9846A CCD VOUT ADCOUT 0.1F CCDIN REGISTER DATA BUFFER DIGITAL OUTPUTS SERIAL INTERFACE DIGITAL IMAGE PROCESSING ASIC CDS/CLAMP TIMING V-DRIVE CCD TIMING TIMING GENERATOR Figure 32. System Applications Diagram –20– REV. 0 AD9846A 3V ANALOG SUPPLY 0.1F 1.0F 3 CML VRT DVDD2 VRB 0.1F DVSS NC THREE-STATE NC STBY SL SDATA 1.0F SCK SERIAL INTERFACE 48 47 46 45 44 43 42 41 40 39 38 37 NC 1 NC 2 D0 36 PIN 1 IDENTIFIER 35 3 34 D1 4 D2 AUX2IN AVDD2 33 BYP4 5 D3 6 D4 31 TOP VIEW (Not to Scale) D5 8 D6 9 D7 0.1F 3V ANALOG SUPPLY 0.1F 32 AD9846A 7 30 29 28 NC CCDIN CCD SIGNAL BYP2 BYP1 0.1F 0.1F AVDD1 AVSS 26 AVSS 10 27 D8 11 (MSB) D9 12 25 12 0.1F 0.1F 3V ANALOG SUPPLY CLPDM VD SHD CLPOB SHP HD PBLK DVSS DATACLK DVDD1 3V DRIVER SUPPLY DRVSS 13 14 15 16 17 18 19 20 21 22 23 24 DRVDD DATA OUTPUTS AUX1IN AVSS NC = NO CONNECT 0.1F 8 CLOCK INPUTS 0.1F 3V ANALOG SUPPLY Figure 33. Recommended Circuit Configuration for CCD-Mode Internal Power-On Reset Circuitry After power-on, the AD9846A will automatically reset all internal registers and perform internal calibration procedures. This takes approximately 1 ms to complete. During this time, normal clock signals and serial write operations may occur. However, serial register writes will be ignored until the internal reset operation is completed. Pin 43 (formerly RSTB on the AD984x non-A products) is no longer used for the reset operation. Toggling Pin 43 in the AD9846A will have no effect. Grounding and Decoupling Recommendations As shown in Figure 33, a single ground plane is recommended for the AD9846A. This ground plane should be as continuous as possible, particularly around Pins 25 through 39. This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. All decoupling capacitors should be located as close as possible to the package pins. REV. 0 A single clean power supply is recommended for the AD9846A, but a separate digital driver supply may be used for DRVDD (Pin 13). DRVDD should always be decoupled to DRVSS (Pin 14), which should be connected to the analog ground plane. Advantages of using a separate digital driver supply include using a lower voltage (2.7 V) to match levels with a 2.7 V ASIC, reducing digital power dissipation, and reducing potential noise coupling. If the digital outputs (Pins 3–12) must drive a load larger than 20 pF, buffering is recommended to reduce digital code transition noise. Alternatively, placing series resistors close to the digital output pins may also help reduce noise. –21– AD9846A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC SQ 0.030 (0.75) 0.018 (0.45) 37 48 36 1 0.276 (7.00) BSC SQ TOP VIEW (PINS DOWN) COPLANARITY 0.003 (0.08) 0 MIN 12 25 13 0.019 (0.5) BSC 0.008 (0.2) 0.004 (0.09) 24 0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35) 7 0 0.006 (0.15) SEATING 0.002 (0.05) PLANE –22– REV. 0 –23– –24– PRINTED IN U.S.A. C02409–2.5–4/01(0)