SN74AS4374B OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP WITH 3-STATE OUTPUTS SDAS109D – APRIL 1989 – REVISED JANUARY 1995 • • DW OR N PACKAGE (TOP VIEW) 3-State Outputs Drive Bus Lines Directly Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs 1Q 2Q 3Q 4Q GND 5Q 6Q 7Q 8Q OE description This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1D 2D 3D 4D VCC 5D 6D 7D 8D CLK The eight flip-flops of the SN74AS4374B are edge-triggered D-type flip-flops. On the second positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. The output-enable (OE) input does not affect internal operations of the flip-flops. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74AS4374B is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D† OUTPUT Q H X X Z L ↑ L L L ↑ H H L L X Q0 † Data presented at the D inputs require two clock cycles to appear at the Q outputs. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AS4374B OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP WITH 3-STATE OUTPUTS SDAS109D – APRIL 1989 – REVISED JANUARY 1995 logic symbol† OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 10 11 20 logic diagram (positive logic) OE EN CLK C1 1D 1 1D 19 2 18 3 17 4 15 6 14 7 13 8 12 9 11 C1 1Q 2Q 10 1D 20 1D C1 1 1Q 1D 3Q 4Q 5Q To Seven Other Channels 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions VCC VIH Supply voltage VIL IOH Low-level input voltage IOL TA Low-level output current 2 High-level input voltage MIN NOM MAX 4.5 5 5.5 2 High-level output current Operating free-air temperature 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V 0.8 V – 15 mA 48 mA 70 °C SN74AS4374B OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP WITH 3-STATE OUTPUTS SDAS109D – APRIL 1989 – REVISED JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 4.5 V, VOH VCC = 4 4.5 5V VOL 5V VCC = 4 4.5 IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, II IIH VCC = 5.5 V, VCC = 5.5 V, IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, MIN II = – 18 mA IOH = – 3 mA IOH = – 15 mA IOL = 32 mA TYP† 2.4 UNIT – 1.5 V 3.2 V 2 IOL = 48 mA VO = 2.7 V 0.25 0.4 0.35 0.5 VO = 0.4 V VI = 7 V VI = 2.7 V VI = 0.5 V VO = 2.25 V OE high MAX – 30 V 20 µA – 20 µA 0.1 mA 20 µA – 0.2 mA – 112 mA ICC VCC = 5.5 V, 100 150 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. timing requirements over recommended operating free-air temperature range (unless otherwise noted) MIN MAX UNIT 125 MHz fclock tw Clock frequency 0 Pulse duration, CLK high or low 4 ns tsu th Setup time, data before CLK↑ 4 ns Hold time, data after CLK↑ 1 ns switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX§ MIN fmax tPLH tPHL tPZH tPZL tPHZ MAX 125 CLK Q OE Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MHz 2 8 2 8 1.5 6 2.5 8 2 OE Q tPLZ 2.5 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. UNIT 6.5 7 ns ns ns 3 SN74AS4374B OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP WITH 3-STATE OUTPUTS SDAS109D – APRIL 1989 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION 7V SWITCH POSITION TABLE Open S1 R1 = 500 Ω From Output Under Test CL = 50 pF (see Note A) Test Point R2 = 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS TEST S1 tPLH tPHL tPZH tPZL tPHZ tPLZ Open Open Open Closed Open Closed 3.5 V High-Level Pulse 1.3 V 1.3 V 0.3 V tw 3.5 V Timing Input 1.3 V 0.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V th tsu VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Data Input 1.3 V 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3.5 V Output Control 1.3 V tPZL 1.3 V tPLZ 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V Out-of-Phase Output 3.5 V Waveform 1 S1 Closed (see Note B) VOL tPLH tPHL VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V 0.3 V 3.5 V Input 1.3 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) VOL 0.3 V VOH 1.3 V 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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