TI SN74ALVC16374DL

SN74ALVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS258A – JANUARY 1993 – REVISED MAY 1995
D
D
D
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Bus Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
ESD Protection Exceeds 2000 V Per
MIL-STD-833C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
description
This 16-bit edge-triggered D-type flip-flop is
designed for 3.3-V VCC operation; it is tested at
2.5-V, 2.7-V, and 3.3-V VCC.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
The SN74ALVC16374 is particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On
the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the
data (D) inputs. OE) can be used to place the eight outputs in either a normal logic state (high- or low-logic levels)
or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without
need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be
retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVC16374 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16374 is characterized for operation from – 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ALVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS258A – JANUARY 1993 – REVISED MAY 1995
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
logic symbol†
1OE
1CLK
2OE
2CLK
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
48
24
25
47
logic diagram (positive logic)
1OE
1EN
C1
1CLK
C1
C2
1D
1D1
2
1
3
44
5
43
6
41
8
40
9
38
11
37
12
36
13
33
48
2EN
46
35
1
2D
2
14
16
32
17
30
19
29
20
27
22
26
23
47
1Q1
1Q1
1Q2
1Q3
1Q4
To Seven Other Channels
1Q5
1Q6
1Q7
2OE
1Q8
2Q1
2CLK
24
25
2Q2
2Q3
C1
2D1
36
1D
2Q4
2Q5
2Q6
2Q7
To Seven Other Channels
2Q8
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
2
2
1D
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
2Q1
SN74ALVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS258A – JANUARY 1993 – REVISED MAY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . 0.85 W
DL package . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
VCC
Supply voltage
MIN
MAX
2.3
3.6
VIH
High level input voltage
High-level
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VIL
Low level input voltage
Low-level
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
IOL
∆t /∆v
Low-level output current
0.7
0.8
VCC
VCC
– 12
VCC = 3 V
VCC = 2.3 V
– 24
VCC = 2.7 V
VCC = 3 V
12
Input transition rise or fall rate
• DALLAS, TEXAS 75265
V
V
2
VCC = 2.3 V
VCC = 2.7 V
TA
Operating free-air temperature
NOTE 4: Unused or floating control pins must be held high or low.
POST OFFICE BOX 655303
1.7
UNIT
– 12
V
V
V
mA
12
mA
24
0
10
ns / V
– 40
85
°C
3
SN74ALVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS258A – JANUARY 1993 – REVISED MAY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH = – 100 µA
IOH = – 6 mA
VOH
VOL
II
II(hold)
(
)
MIN to MAX
VIH = 1.7 V
VIH = 1.7 V
2.3 V
VCC – 0.2
2
2.3 V
1.7
IOH = – 12 mA
VIH = 2 V
VIH = 2 V
2.7 V
2.2
3V
2.4
IOH = – 24 mA
IOL = 100 µA
VIH = 2 V
3V
2
MIN to MAX
0.2
IOL = 6 mA
IOL = 12 mA
VIL = 0.7 mA
VIL = 0.7 mA
2.3 V
0.4
2.3 V
0.7
IOL = 12 mA
IOL = 24 mA
VIL = 0.8 mA
VIL = 0.8 mA
2.7 V
0.4
3V
0.55
3.6 V
2.3 V
45
VI = 1.7 V
VI = 0.8 V
2.3 V
–45
IOZ§
ICC
VO = VCC or GND
VI = VCC or GND,
nICC
VCC = 3 V to 3.6 V,
Other inputs at VCC or GND
Control inputs
Inputs
IO = 0
One input at VCC – 0.6 V,
VI = VCC or GND
3V
75
3V
–75
UNIT
V
±5
VI = VCC or GND
VI = 0.7 V
VI = 2 V
VI = 0 to 3.6 V
Ci
TA = – 40°C to 85°C
MIN
TYP
MAX
VCC†
TEST CONDITIONS
V
µA
µA
3.6 V
± 500
3.6 V
± 10
µA
3.6 V
40
µA
750
µA
3
33V
3.3
pF
6
Co
VO = VCC or GND
3.3 V
† For conditions shown as MIN or MAX use the appropriate values under recommended operating conditions.
§ For I/O ports, the parameter IOZ includes the input leakage current.
7
pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 and 2)
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
0
150
0
150
0
150
UNIT
fclock
tw
Clock frequency
Pulse duration, CLK high or low
3.3
3.3
3.3
ns
tsu
th
Setup time, data before CLK↑
2.1
2.2
1.9
ns
Hold time, data after CLK↑
0.6
0.5
0.5
ns
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MHz
SN74ALVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS258A – JANUARY 1993 – REVISED MAY 1995
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 2.5 V
± 0.2 V
MIN
MAX
150
VCC = 2.7 V
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
fmax
tpd
150
MHz
CLK
Q
1
5.9
4.9
1
4.2
ns
ten
CLK
Q
1
6.7
5.9
1
4.8
ns
tdis
CLK
Q
1.7
5.5
4.7
1.2
4.3
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
d
Outputs enabled
Outputs disabled
TEST CONDITIONS
CL = 50 pF,
pF
POST OFFICE BOX 655303
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
31
30
16
18
UNIT
pF
5
SN74ALVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS258A – JANUARY 1993 – REVISED MAY 1995
"
PARAMETER MEASUREMENT INFORMATION
0.2 V
VCC = 2.5 V
4.6 V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
4.6 V
GND
tw
LOAD CIRCUIT
2.3 V
2.3 V
Timing
Input
1.2 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.3 V
Data
Input
1.2 V
1.2 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.2 V
1.2 V
0V
tPLH
tPHL
VOH
1.2 V
2.3 V
Output
Control
(low-level
enabling)
1.2 V
1.2 V
VOL
tPLZ
2.3 V
Output
Waveform 1
S1 at 4.6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.2 V
0V
tPZL
2.3 V
Output
1.2 V
0V
tsu
Input
Input
1.2 V
1.2 V
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
1.2 V
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
v
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
v
v
SN74ALVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS258A – JANUARY 1993 – REVISED MAY 1995
"
PARAMETER MEASUREMENT INFORMATION
0.3 V
VCC = 2.7 V AND 3.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
LOAD CIRCUIT
tw
2.7 V
2.7 V
Timing
Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
2.7 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
0V
tPZL
2.7 V
Output
1.5 V
1.5 V
tsu
Input
Input
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
1.5 V
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
v
v
v
Figure 2. Load Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74ALVC16374DGGR
OBSOLETE
TSSOP
DGG
48
TBD
Call TI
Call TI
SN74ALVC16374DL
OBSOLETE
SSOP
DL
48
TBD
Call TI
Call TI
SN74ALVC16374DLR
OBSOLETE
SSOP
DL
48
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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