SN74ALS29841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SDAS149A – JUNE 1988 – REVISED JANUARY 1995 • • • • • • 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Provides Extra Bus-Driving Latches Necessary for Wider Address/Data Paths or Buses With Parity Buffered Control Inputs Reduce dc Loading Effects Power-Up High-Impedance State Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs DW OR NT PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND description 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q LE This 10-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The ten latches are transparent D-type latches. The SN74ALS29841 has noninverting data (D) inputs. A buffered output-enable (OE) input can place the ten outputs in either a normal logic state (high or low logic levels) or in a high-impedance state. The outputs also are in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are off. The SN74ALS29841 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALS29841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SDAS149A – JUNE 1988 – REVISED JANUARY 1995 logic symbol† OE LE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1 13 2 EN C1 23 1D 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE LE 1 13 C1 1D 2 1D 23 1Q To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS29841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SDAS149A – JUNE 1988 – REVISED JANUARY 1995 recommended operating conditions VCC VIH Supply voltage VIL IOH Low-level input voltage IOL tw tsu th TA Operating free-air temperature High-level input voltage MIN NOM MAX UNIT 4.75 5 5.25 V 2 V 0.8 V High-level output current – 24 mA Low-level output current 48 mA Pulse duration, LE high 6 ns Setup time, data before LE↓ 2.5 ns Hold time, data after LE↓ 4.5 ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.75 V, VOH VCC = 4 4.75 75 V VOL IOZH VCC = 4.75 V, VCC = 5.25 V, IOZL II VCC = 5.25 V, VCC = 5.25 V, IIH IIL VCC = 5.25 V, VCC = 5.25 V, IOS‡ ICC VCC = 5.25 V, VCC = 5.25 V, II = – 18 mA IOH = – 15 mA IOH = – 24 mA IOL = 48 mA MIN TYP† 2.4 3.3 2 3.1 0.35 VO = 2.7 V VO = 0.4 V UNIT – 1.2 V V 0.5 V 20 µA – 20 µA VI = 5.5 V VI = 2.7 V 0.1 mA 20 µA VI = 0.4 V VO = 0 – 0.2 mA – 250 mA 85 mA – 75 Outputs low 55 † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. POST OFFICE BOX 655303 MAX • DALLAS, TEXAS 75265 3 SN74ALS29841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SDAS149A – JUNE 1988 – REVISED JANUARY 1995 switching characteristics (see Figure 1) FROM (INPUT) TO (OUTPUT) TEST CONDITIONS tPLH tPHL D An Q Any CL = 50 pF tPLH tPHL D An Q Any CL = 300 pF tPLH tPHL LE An Q Any CL = 50 pF tPLH tPHL LE An Q Any CL = 300 pF tPZH tPZL OE An Q Any CL = 50 pF tPZH tPZL OE An Q Any CL = 300 pF tPHZ tPLZ OE An Q Any CL = 50 pF tPHZ tPLZ OE Any Q CL = 5 pF PARAMETER VCC = MIN to MAX†, TA = MIN to MAX† MIN MAX 2 9.5 2 9.5 14 12 12 16 16 14 14 20 23 15 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12 9 9 UNIT ns ns ns ns ns ns ns ns SN74ALS29841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SDAS149A – JUNE 1988 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION Test Point VCC SWITCH POSITION TABLE S1 From Output Under Test RL = 180 Ω All Diodes 1N916 or 1N3064 R1 1 kΩ CL (see Note A) S2 TEST S1 S2 tPLH tPHL tPZH tPZL tPHZ tPLZ Closed Closed Open Closed Closed Closed Closed Closed Closed Open Closed Closed LOAD CIRCUIT 3V 1.5 V Timing Input High-Level Pulse 3V 1.5 V 0 0 Data Input tw th tsu 1.5 V 3V 3V 1.5 V 1.5 V 0 Low-Level Pulse 1.5 V 1.5 V 0 VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control 1.5 V 1.5 V 0 tPZL tPLZ ≈ 4.5 V 3V Input 1.5 V 1.5 V 0 1.5 V 1.5 V VOL tPHZ VOH 1.5 V VOH Waveform 2 (see Note B) 1.5 V 1.5 V 0.5 V ≈ 1.5 V ≈0 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 0.5 V tPZH tPLH tPHL ≈ 1.5 V VOL VOH In-Phase Output 1.5 V tPHL tPLH Out-of-Phase Output Waveform 1 (see Note B) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated