SN54LVT162244A, SN74LVT162244A 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com FEATURES • • • • • • • • • • Members of the Texas Instruments Widebus™ Family Output Ports Have Equivalent 22-Ω Series Resistors, So No External Resistors Are Required Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SCBS718D – JUNE 2000 – REVISED DECEMBER 2006 SN54LVT162244A . . . WD PACKAGE SN74LVT162244A . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE DESCRIPTION/ORDERING INFORMATION The 'LVT162244A devices are 16-bit buffers and line drivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical active-low output-enable (OE) inputs. The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to reduce overshoot and undershoot. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2006, Texas Instruments Incorporated SN54LVT162244A, SN74LVT162244A 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS718D – JUNE 2000 – REVISED DECEMBER 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) ORDERING INFORMATION PACKAGE (1) TA FBGA – GRD FBGA – ZRD (Pb-free) ORDERABLE PART NUMBER Reel of 1000 Tube of 25 SSOP – DL Reel of 1000 –40°C to 85°C TSSOP – DGG Reel of 2000 TVSOP – DGV Reel of 2000 VFBGA – GQL VFBGA – ZQL –55°C to 125°C (1) (2) CFP – WD Reel of 1000 Tube SN74LVT162244AGRDR TOP-SIDE MARKING LZ244A SN74LVT162244AZRDR SN74LVT162244ADL SN74LVT162244ADLG4 LVT162244A SN74LVT162244ADLR 74LVT162244ADLRG4 SN74LVT162244ADGGR LVT162244A 74LVT162244ADGGRE4 SN74LVT162244ADGVR LZ244A 74LVT162244ADGVRE4 SN74LVT162244AGQLR LZ244A SN74LVT162244AZQLR SNJ544LVT162244AWD (2) SNJ54LVT162244AWD Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Product preview GQL OR ZQL PACKAGE (TOP VIEW) TERMINAL ASSIGNMENTS (1) (56-Ball GQL/ZQL Package) 1 2 3 4 5 6 1 2 3 4 5 6 A 1OE NC NC NC NC 2OE B 1Y2 1Y1 GND GND 1A1 1A2 C 1Y4 1Y3 VCC VCC 1A3 1A4 D 2Y2 2Y1 GND GND 2A1 2A2 E 2Y4 2Y3 2A3 2A4 F 3Y1 3Y2 3A2 3A1 G 3Y3 3Y4 GND GND 3A4 3A3 H 4Y1 4Y2 VCC VCC 4A2 4A1 xxx J 4Y3 4Y4 GND GND 4A4 4A3 xxx K 4OE NC NC NC NC 3OE A B C D E F G H J K xxx xxx 2 (1) NC – No internal connection Submit Documentation Feedback SN54LVT162244A, SN74LVT162244A 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS718D – JUNE 2000 – REVISED DECEMBER 2006 TERMINAL ASSIGNMENTS (1) (54-Ball GRD/ZRD Package) GRD OR ZRD PACKAGE (TOP VIEW) 1 2 3 4 5 1 2 3 4 5 6 A 1Y1 NC 1OE 2OE NC 1A1 B 1Y3 1Y2 NC NC 1A2 1A3 6 A C 2Y1 1Y4 VCC VCC 1A4 2A1 B D 2Y3 2Y2 GND GND 2A2 2A3 C E 3Y1 2Y4 GND GND 2A4 3A1 D E F F 3Y3 3Y2 GND GND 3A2 3A3 G 4Y1 3Y4 VCC VCC 3A4 4A1 H 4Y3 4Y2 NC NC 4A2 4A3 J 4Y4 NC 4OE 3OE NC 4A4 G H J (1) NC – No internal connection FUNCTION TABLE (each 4-bit buffer/driver) INPUTS OE A OUTPUT Y L H H L L L H X Z Submit Documentation Feedback 3 SN54LVT162244A, SN74LVT162244A 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS718D – JUNE 2000 – REVISED DECEMBER 2006 LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 Pin numbers shown are for the DGG, DGV, DL, and WD packages. 4 Submit Documentation Feedback 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 SN54LVT162244A, SN74LVT162244A 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS718D – JUNE 2000 – REVISED DECEMBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high state (2) IO Current into any output in the low state IO Current into any output in the high state (3) IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 –50 mA θJA Package thermal impedance (4) (1) (2) (3) (4) mA 30 mA –50 mA DGG package 70 DGV package 58 DL package 63 GQL/ZQL package 42 GRD/ZRD package Tstg V 30 °C/W 36 Storage temperature range –65 °C 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) SN54LVT162244A (2) SN74LVT162244A MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage 5.5 5.5 V IOH High-level output current –12 –12 mA IOL Low-level output current 12 12 mA ∆t/∆v Input transition rise or fall rate 10 10 ns/V 2 0.8 Outputs enabled ∆t/∆VCC Power-up ramp rate 200 TA –55 (1) (2) Operating free-air temperature V 2 V 0.8 µs/V 200 125 –40 V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Product preview Submit Documentation Feedback 5 SN54LVT162244A, SN74LVT162244A 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS718D – JUNE 2000 – REVISED DECEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54LVT162244A (1) TEST CONDITIONS MIN VIK VCC = 2.7 V, II = –18 mA VOH VCC = 3 V, IOH = –12 mA VOL VCC = 3 V, Control inputs II Data inputs TYP (2) SN74LVT162244A MAX MIN TYP (2) MAX –1.2 –1.2 IOL = 12 mA 0.8 0.8 VCC = 0 or 3.6 V, VI = 5.5 V 10 10 VCC = 3.6 V, VI = VCC or GND ±1 ±1 1 1 –5 –5 2 V V VI = VCC VCC = 3.6 V UNIT VI = 0 V µA ±100 µA 5 5 µA –5 –5 µA IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care ±100 (3) ±100 µA IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care ±100 (3) ±100 µA VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high 0.19 0.19 ICC Ioff VCC = 0, VI or VO = 0 to 4.5 V IOZH VCC = 3.6 V, VO = 3 V IOZL VCC = 3.6 V, VO = 0.5 V Outputs low Outputs disabled 5 5 0.19 0.19 0.2 0.2 mA ∆ICC (4) VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 4 4 pF Co VO = 3 V or 0 9 9 pF (1) (2) (3) (4) mA Product preview All typical values are at VCC = 3.3 V, TA = 25°C. On products compliant to MIL-PRF-38535, this parameter is not production tested. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVT162244A (1) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ (1) (2) 6 FROM (INPUT) TO (OUTPUT) A Y OE Y OE Y VCC = 3.3 V ± 0.3 V SN74LVT162244A VCC = 2.7 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V MAX MIN TYP (2 ) 4.6 5.1 1.4 3.4 4 4.8 3.9 4.5 1.2 2.9 3.6 4.1 1.1 5.4 6.7 1.2 3.9 5.1 6.5 1.3 4.9 6.1 1.4 3.8 4.5 5.8 1.6 5.9 6.5 2.2 4.4 5 5.4 1 5.9 5.8 2 4.2 5 5.4 MIN MAX 1.1 1.1 MIN MAX tsk(LH) 0.5 tsk(HL) 0.5 Product preview All typical values are at VCC = 3.3 V, TA = 25°C. Submit Documentation Feedback MIN UNIT MAX ns ns ns ns SN54LVT162244A, SN74LVT162244A 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS718D – JUNE 2000 – REVISED DECEMBER 2006 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V Input 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Input 1.5 V 1.5 V 0V tPHL tPLH VOH Output 1.5 V 1.5 V VOL tPHL Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ 3V 1.5 V tPZH tPLH VOH Output 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74LVT162244ADGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVT162244ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVT162244ADLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT162244ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT162244ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT162244ADL ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT162244ADLG4 ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT162244ADLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT162244AGQLR NRND BGA MI CROSTA R JUNI OR GQL 56 1000 TBD SNPB Level-1-240C-UNLIM SN74LVT162244AGRDR ACTIVE BGA MI CROSTA R JUNI OR GRD 54 1000 TBD SNPB Level-1-240C-UNLIM SN74LVT162244AZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74LVT162244AZRDR ACTIVE BGA MI CROSTA R JUNI OR ZRD 54 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2007 temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 19-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVT162244ADGGR DGG 48 MLA 330 24 8.6 15.8 1.8 12 24 Q1 SN74LVT162244ADGVR DGV 48 MLA 330 24 6.8 10.1 1.6 12 24 Q1 SN74LVT162244ADLR DL 48 MLA 330 32 11.35 16.2 3.1 16 32 Q1 SN74LVT162244AGQLR GQL 56 HIJ 330 16 4.8 7.3 1.45 8 16 Q1 SN74LVT162244AGRDR GRD 54 HIJ 330 16 5.8 8.3 1.55 8 16 Q1 SN74LVT162244AZQLR ZQL 56 HIJ 330 16 4.8 7.3 1.45 8 16 Q1 SN74LVT162244AZRDR ZRD 54 HIJ 330 16 5.8 8.3 1.55 8 16 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74LVT162244ADGGR DGG 48 MLA 333.2 333.2 31.75 SN74LVT162244ADGVR DGV 48 MLA 333.2 333.2 31.75 SN74LVT162244ADLR DL 48 MLA 336.6 342.9 41.3 SN74LVT162244AGQLR GQL 56 HIJ 346.0 346.0 33.0 SN74LVT162244AGRDR GRD 54 HIJ 346.0 346.0 33.0 SN74LVT162244AZQLR ZQL 56 HIJ 346.0 346.0 33.0 SN74LVT162244AZRDR ZRD 54 HIJ 346.0 346.0 33.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 3 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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