TI SN74LVTH16240DLR

SN54LVTH16240,, SN74LVTH16240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS684D – MARCH 1997 – REVISED DECEMBER 2006
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Members of the Texas Instruments Widebus™
Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation Down
to 2.7 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package Using
25-mil Center-to-Center Spacings
SN54LVTH16240 . . . WD PACKAGE
SN74LVTH16240 . . . DGG OR DL PACKAGE
(TOP VIEW)
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
DESCRIPTION/ORDERING INFORMATION
These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
The 'LVTH16240 devices are designed specifically to improve both the performance and density of 3-state
memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
ORDERING INFORMATION
PACKAGE (1)
TA
Reel of 1000
SSOP – DL
–40°C to 85°C
Tube of 25
TSSOP – DGG
(1)
Reel of 2000
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SN74LVTH16240DLR
SN74LVTH16240DLRG4
SN74LVTH16240DL
LVTH16240
SN74LVTH16240DLG4
74LVTH16240DGGRE4
SN74LVTH16240DGGR
LVTH16240
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2006, Texas Instruments Incorporated
SN54LVTH16240,, SN74LVTH16240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS684D – MARCH 1997 – REVISED DECEMBER 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide
inverting outputs and symmetrical active-low output-enable (OE) inputs.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH16240 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH16240 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUTS
Y
OE
A
L
H
L
L
L
H
H
X
Z
LOGIC SYMBOL(1)
1
EN1
1OE
48
EN2
2OE
25
3OE
EN3
24
EN4
4OE
2
47
1
1A1
1
1Y1
46
3
44
5
43
6
41
8
1Y2
1A2
1Y3
1A3
1Y4
1A4
1
2A1
2
2Y1
40
9
38
11
37
12
2A2
2Y2
2Y3
2A3
2Y4
2A4
13
36
1
3A1
3
3Y1
35
14
33
16
32
17
30
19
3Y2
3A2
3A3
3Y3
3Y4
3A4
1
4A1
4
4Y1
29
20
27
22
26
23
4Y2
4A2
4Y3
4A3
4A4
4Y4
(1)
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
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SN54LVTH16240,, SN74LVTH16240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS684D – MARCH 1997 – REVISED DECEMBER 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
1
25
1OE
3OE
47
2
1A1
46
1Y2
3A2
1Y3
3A3
1Y4
3A4
17
3Y4
24
2OE
4OE
41
40
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
20
4Y2
27
12
19
4Y1
29
11
2A3
37
2Y1
9
2A2
38
30
8
2A1
2A4
16
3Y3
32
48
14
3Y2
33
6
1A4
13
3Y1
35
5
1A3
43
3A1
3
1A2
44
36
1Y1
22
4Y3
26
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23
4Y4
3
SN54LVTH16240,, SN74LVTH16240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS684D – MARCH 1997 – REVISED DECEMBER 2006
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
V
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high state (2)
state (2)
SN54LVTH16240
96
SN74LVTH16240
128
SN54LVTH16240
48
SN74LVTH16240
64
UNIT
IO
Current into any output in the low state
IO
Current into any output in the high state (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
DGG package
89
DL package
94
–65
150
mA
mA
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This current flows only when the output is in the high state and VO > VCC.
The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions (1)
SN54LVTH16240
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
5.5
5.5
V
IOH
High-level output current
–24
–32
mA
IOL
Low-level output current
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
∆t/∆VCC
Power-up ramp rate
200
TA
Operating free-air temperature
–55
(1)
4
SN74LVTH16240
MIN
2
Outputs enabled
2
V
µs/V
200
125
–40
V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN54LVTH16240,, SN74LVTH16240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS684D – MARCH 1997 – REVISED DECEMBER 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 2.7 V,
II = –18 mA
VCC = 2.7 V to 3.6 V,
IOH = –100 µA
VCC = 2.7 V,
IOH = –8 mA
IOH = –24 mA
VCC = 3 V
SN54LVTH16240
MIN TYP (1)
SN74LVTH16240
MAX
–1.2
VOL
VCC = 3 V
VCC – 0.2
2.4
2.4
VCC = 0 or 3.6 V,
II
Data inputs
Ioff
VCC = 3.6 V
VCC = 0,
0.2
0.2
IOL = 24 mA
0.5
0.5
IOL = 16 mA
0.4
0.4
IOL = 32 mA
0.5
0.5
IOL = 48 mA
0.55
VCC = 3.6
VI = 5.5 V
10
10
VI = VCC or GND
±1
±1
1
1
VI = VCC
VI = 0
VI = 2 V
Data inputs
V (2),
VCC = 3.6 V,
VO = 3 V
IOZL
VCC = 3.6 V,
VO = 0.5 V
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don't care
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don't care
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
∆ICC
(4)
–5
µA
–5
±100
75
75
–75
–75
µA
µA
500
–750
VI = 0 to 3.6 V
IOZH
V
0.55
VI or VO = 0 to 4.5 V
VCC = 3 V
II(hold)
V
2
IOL = 100 µA
VI = 0.8 V
UNIT
V
2
IOL = 64 mA
Control inputs VCC = 3.6 V,
MAX
–1.2
VCC – 0.2
IOH = –32 mA
VCC = 2.7 V
MIN TYP (1)
Outputs high
Outputs low
Outputs disabled
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
5
5
µA
–5
–5
µA
±100 (3)
±100
µA
±100 (3)
±100
µA
0.19
0.19
5
5
0.19
0.19
0.2
0.2
mA
mA
Ci
VI = 3 V or 0
4
4
pF
Co
VO = 3 V or 0
9
9
pF
(1)
(2)
(3)
(4)
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
On products compliant to MIL-PRF-38535, this parameter is not production tested.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
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5
SN54LVTH16240,, SN74LVTH16240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS684D – MARCH 1997 – REVISED DECEMBER 2006
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVTH16240
PARAMETER
tPLH
tPHL
tPZH
A
Y
OE
Y
OE
Y
VCC = 3.3 V
±0.3 V
SN74LVTH16240
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
±0.3 V
MIN TYP (1)
VCC = 2.7 V
MAX
MIN
UNIT
MIN
MAX
1
3.6
4.1
1
2.2
3.5
MAX
4
1
3.6
4.1
1
2.7
3.5
4
1
4.2
5.1
1
2.6
4
4.9
4.6
4.8
1.2
2.6
4.4
4.6
1.9
4.7
5.2
2
3.4
4.5
5
1.9
4.4
4.5
2
3.2
4.2
4.2
tsk(LH)
0.5
0.5
tsk(HL)
0.5
0.5
tPHZ
tPLZ
6
TO
(OUTPUT)
1.1
tPZL
(1)
FROM
(INPUT)
All typical values are at VCC = 3.3 V, TA = 25°C.
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ns
ns
ns
ns
SN54LVTH16240,, SN74LVTH16240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS684D – MARCH 1997 – REVISED DECEMBER 2006
PARAMETER MEASUREMENT INFORMATION
6V
500 W
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 W
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
2.7 V
1.5 V
Input
th
2.7 V
1.5 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
Input
1.5 V
1.5 V
0V
tPHL
tPLH
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPLZ
tPZL
3V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLH
tPHL
2.7 V
Output
Control
1.5 V
VOH – 0.3 V
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, tr £ 2.5 ns, tf £ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
19-Sep-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74LVTH16240DGGRE4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH16240DGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH16240DL
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH16240DLG4
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH16240DLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH16240DLRG4
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Apr-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
26-Apr-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVTH16240DGGR
DGG
48
MLA
330
24
8.6
15.8
1.8
12
24
Q1
SN74LVTH16240DLR
DL
48
MLA
330
32
11.35
16.2
3.1
16
32
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74LVTH16240DGGR
DGG
48
MLA
333.2
333.2
31.75
SN74LVTH16240DLR
DL
48
MLA
336.6
342.9
41.3
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
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www.ti.com/audio
Data Converters
dataconverter.ti.com
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www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Low Power
Wireless
www.ti.com/lpw
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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