TI TPS23757PWR

TPS23757
www.ti.com ....................................................................................................................................................................................................... SLVS948 – JULY 2009
High Efficiency PoE Interface and DC/DC Controller
FEATURES
The TPS23757 has an output flag indicating if an
external wall adapter is active when used in
conjunction with ORing controls. The detection
signature pin can also be used to force power from
the PoE source off. Classification can be
programmed to any of the defined types with a single
resistor.
1
•
•
•
•
•
•
•
•
•
•
•
Powers up to 13 W (Input) PDs
Legacy and IEEE 802.3at type 1 PDs
Optimized for Isolated DC/DC Converters
Supports High-Efficiency Topologies
Complete PoE Interface
Adapter ORing Support
Programmable Frequency with Synch.
Robust 100 V, 0.5 Ω Hotswap MOSFET
Pin Compatible with TPS23754/6
–40°C to 125°C Junction Temperature Range
Industry Standard TSSOP-20
The dc/dc controller features two complementary gate
drivers with programmable dead time. This simplifies
design of highly-efficient flyback topologies or
active-clamp forward or flyback converters. The
second gate driver may be disabled if desired for
single MOSFET topologies. The controller also
features internal softstart, bootstrap startup source,
current-mode compensation, and a 78% maximum
duty cycle. A programmable and synchronizable
oscillator allows design optimization for efficiency and
eases use of the controller to upgrade existing power
supply designs. Accurate programmable blanking,
with a default period, simplifies the usual currentsense filter design trade-offs.
APPLICATIONS
•
•
•
•
IEEE 802.3at (draft) type 1 Compliant Devices
Video and VoIP Telephones
Access Points
Security Cameras
The TPS23757 has a 9 V converter startup,
permitting operation with 12 V wall adapters.
DESCRIPTION
The TPS23757 is a combined Power over Ethernet
(PoE) powered device (PD) interface and
current-mode dc/dc controller optimized specifically
for isolated converters. The PoE interface supports
the IEEE 802.3at (draft) standard for a type 1 PD,
which is equivalent to the 13W standard of IEEE
802.3-2008.
From Ethernet
Pairs 1,2
The TPS23757 supports a number of input voltage
ORing options including highest voltage, external
adapter preference, and PoE preference.
R DEN
T1
R OB
CIZ
R FBU
C CTL
R CTL
M2
GAT2
Adapter
Present and
Converter
Running
R CS
T2
C VC
BLNK
VAPb_OUT
VB
TLV431
RFB L
VDD
Optional
Interface
COUT2
COUT1
DVC1
VB
GATE
CS
CVB
RBLNK
RTN, COM
ARTN
DT
R DT
RFRS
RAPD2
Adapter
R APb
R APb_OUT
VC
M1
DA
RAPD1
APb
PPD
CLS
VSS
APD
CTL
FRS
VOUT
L OUT
VDD1
DEN
R CLS
0.1 mF
From Ethernet
Pairs 3,4
58V
C IN
C IO
Figure 1. High Efficiency Converter Using TPS23757
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS23757
SLVS948 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.
These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic
voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
PRODUCT INFORMATION (1)
TPS23757PW
(1)
STATUS
DUTY
CYCLE
POE UVLO
ON / HYST.
(V)
CONVERTER UVLO
ON / HYST.
(V)
PoE Current
Limit
(mA)
PACKAGE
MARKING
Preview
0–78%
35/4.5
9 / 3.5
465
TSSOP-20
TPS23757
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
(2)
Voltage with respect to VSS unless otherwise noted.
Input voltage
MIN
MAX
UNIT
ARTN (2), COM (2), DEN, PPD, RTN (3),
VDD, VDD1
–0.3
100
V
CLS (4)
-0.3
6.5
V
[APD, BLNK (4), CTL, DT (4), FRS (4),
VB (4)] to [ARTN, COM]
–0.3
6.5
V
CS to [ARTN,COM]
–0.3
VB
V
[ARTN, COM] to RTN
–2
2
V
VC, APb, to [ARTN, COM]
–0.3
19
V
GATE (4), GAT2 (4) to [ARTN, COM]
–0.3
VC+0.3
V
Sinking current
RTN
Internally limited
Sourcing current
VB
Internally limited
Average Sourcing or sinking current
GATE, GAT2
25
mArms
Human Body Model (HBM)
2
kV
Electrostatic Discharge
Charge Device Model (CDM)
System level (contact/air) at RJ-45 (5)
Operating junction temperature range
(1)
(2)
(3)
(4)
(5)
2
TJ
–40
mA
mA
500
V
8 / 15
kV
Internally limited
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ARTN and COM typically tied to RTN.
IRTN = 0 for VRTN > 80V.
Do not apply voltage to these pins
ESD per EN61000-4-2. A power supply containing the TPS23757 was subjected to the highest test levels in the standard. See the ESD
section.
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RECOMMENDED OPERATING CONDITIONS (1)
Voltage with respect to VSS (unless otherwise noted)
MIN
VI
UNIT
57
V
Input voltage range APb, VC to [ARTN, COM]
0
18
V
Input voltage range APD, CTL to [ARTN, COM]
0
VB
V
Input voltage range CS to [ARTN, COM]
0
2
Continuous RTN current (TJ ≤ 125°C) (2)
IS
Sourcing current, VB
C
VB capacitance
0
V
400
mA
5
mA
350
kΩ
125
°C
2.5
µF
0.08
RBLNK
0
Synchronization pulse width input (when used)
(1)
(2)
MAX
0
I
TJ
NOM
Input voltage range ARTN, COM, PPD, RTN, VDD, VDD1
25
Operating junction temperature range
ns
–40
ARTN and COM tied to RTN.
This is the minimum current-limit value. PDs should be designed for maximum currents below this value to provide for unit power-draw
tolerance. IEEE 802.3at (draft) type 1 and IEEE 802.3-2008 compliant devices should not draw average current greater than 350 mA, or
their class power.
DISSIPATION RATINGS
(1)
(2)
(3)
PACKAGE
ΨJT
°C/W (1)
θJA
°C/W (2)
θJA
°C/W (3)
PWP (TSSOP-20)
0.7 / 0.45
135
74
Thermal resistance junction to case top, low-k / high-k board, natural convection.
JEDEC method with low-k board (1 signal layer), natural convection.
JEDEC method with high-k board (2 signal – 2 plane layers).
ELECTRICAL CHARACTERISTICS
Unless otherwise noted: CS=COM=APD=CTL=RTN=ARTN, GATE and GAT2 float, RFRS= 68.1 kΩ, RBLNK= 249 kΩ, DT = VB,
PPD = VSS, APb open, CVB= CVC= 0.1 µF, RDEN= 24.9 kΩ, RCLS open, 0 V ≤ (VDD, VDD1) ≤ 57 V, 0 V ≤ VC ≤ 18 V, –40°C ≤ TJ ≤
125°C. Typical specifications are at 25°C.
CONTROLLER SECTION ONLY
[VSS = RTN and VDD = VDD1] or [VSS = RTN = VDD], all voltages referred to [ARTN, COM] (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
VC
VCUV
VCUVH
tST
UVLO
VC rising
Hysteresis
(1)
8.7
9
9.3
3.3
3.5
3.7
Operating current
VC = 12 V, CTL = VB, RDT = 68.1 kΩ
0.7
0.92
1.2
Bootstrap startup time,
CVC = 22 µF
VDD1 = 10.2 V, VC(0) = 0 V
50
85
175
VDD1 = 35 V, VC(0) = 0 V
27
45
92
Startup current source - IVC
VDD1 = 10.2 V, VC = 8.6 V
0.44
1.06
1.80
VDD1 = 48 V, VC = 0 V
2.7
4.8
6.8
6.5 V ≤ VC ≤ 18 V, 0 ≤ IVB ≤ 5 mA
4.8
5.10
5.25
V
mA
ms
mA
VB
Voltage
(1)
V
The hysteresis tolerance tracks the rising threshold for a given device.
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PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
227
253
278
kHz
76
78
80
%
2
2.2
2.4
V
FRS
Switching frequency
CTL = VB, measure GATE, RFRS = 68.1 kΩ
DMAX
Duty cycle
CTL= VB, measure GATE
VSYNC
Synchronization
Input threshold
0% duty cycle threshold
VCTL ↓ until GATE stops
1.3
1.5
1.7
V
Softstart period
Interval from switching start to VCSMAX
1.9
3.9
6.2
ms
70
100
145
kΩ
BLNK = RTN
35
55
78
RBLNK = 49.9 kΩ
38
55
70
RDT = 24.9 kΩ, GAT2 ↑ to GATE ↑
40
50
62.5
RDT = 24.9 kΩ, GATE ↓ to GAT2 ↓
40
50
62.5
CTL
VZDC
Input resistance
BLNK
Blanking delay
(In addition to t1)
ns
DT
CTL = VB, CGATE = 1 nF,
CGAT2 = 1 nF, measure GATE, GAT2
tDT1
Dead time
See Figure 2 for tDTx definition
tDT2
tDT1
RDT = 75 kΩ, GAT2 ↑ to GATE ↑
120
150
188
tDT2
RDT = 75 kΩ, GATE ↓ to GAT2 ↓
120
150
188
ns
CS
VCSMAX
Maximum threshold voltage
VCTL = VB, VCS rising until GATE duty cycle drops
0.5
0.55
0.6
V
t1
Turnoff delay
VCS = 0.65 V
24
40
70
ns
VSLOPE
Internal slope compensation
voltage
Peak voltage at maximum duty cycle, referenced to CS
120
155
185
mV
ISL_EX
Peak slope compensation
current
VCTL = VB, ICS at maximum duty cycle
30
42
54
µA
Bias current (sourcing)
DC component of ICS
1
2.5
4.3
µA
Source current
VCTL = VB, VC = 12 V, GATE high, pulsed measurement
0.37
0.6
0.95
A
Sink current
VCTL = VB, VC = 12 V, GATE low, pulsed measurement
0.7
1.0
1.4
A
Source current
VCTL = VB, VC = 12 V, GAT2 high, RDT = 24.9 kΩ, pulsed
measurement
0.37
0.6
0.95
A
Sink current
VCTL = VB, VC = 12 V, GAT2 low, RDT = 24.9 kΩ, pulsed
measurement
0.7
1.0
1.4
A
1.43
1.5
1.57
0.29
0.31
0.33
1.45
1.55
1.65
0.29
0.31
0.33
7.4
8.3
9.2
0.5
0.6
0.7
GATE
GAT2
APD / PPD
VAPDEN
VAPDH
APD threshold voltage
VPPDEN
VPPDH
VPPD2
Hysteresis
(2)
VPPD- VVSS rising, UVLO disable
PPD threshold voltage
VPPD2H
IPPD
VAPD rising
Hysteresis
(2)
VPPD- VVSS rising, Class enable
Hysteresis
(2)
APD leakage current
(source or sink)
VC = 12 V, VAPD = VB
PPD sink current
VPPD-VVSS = 1.5 V
2.5
TJ rising
135
V
V
V
1
µA
5
7.5
µA
145
155
°C
THERMAL SHUTDOWN
Turnoff temperature
Hysteresis (3)
(2)
(3)
4
20
°C
The hysteresis tolerance tracks the rising threshold for a given device.
These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product
warranty.
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ELECTRICAL CHARACTERISTICS – PoE AND CONTROL
[VDD = VDD1] or [VDD1 = RTN], VC = RTN, COM = RTN = ARTN, all voltages referred to VSS unless otherwise noted
PARAMETER
TEST CONDITIONS
DETECTION (DEN)
MIN
TYP MAX
UNIT
(VDD = VDD1 = RTN = VSUPPLY positive)
Measure ISUPPLY
Detection current
Detection bias current
VPD_DIS
VDD = 1.6 V
62
64.3
66.5
VDD = 10 V
399
406
414
5.6
10
4
5
V
0.1
5
µA
VDD = 10 V, float DEN, measure ISUPPLY
Hotswap disable threshold
3
DEN leakage current
VDEN = VDD = 57 V, float VDD1 and RTN, measure IDEN
CLASSIFICATION (CLS)
µA
µA
(VDD = VDD1 = RTN = VSUPPLY positive)
13 V ≤ VDD ≤ 21 V, Measure ISUPPLY
RCLS = 1270 Ω
1.8
2.1
2.4
RCLS = 243 Ω
9.9
10.4
10.9
RCLS = 137 Ω
17.6
18.5
19.4
RCLS = 90.9 Ω
26.5
27.7
29.3
RCLS = 63.4 Ω
38.0
39.7
42
Classification regulator lower
threshold
Regulator turns on, VDD rising
11.2
11.9
12.6
Hysteresis (1)
1.55
1.65
1.75
Classification regulator upper
threshold
Regulator turns off, VDD rising
21
22
23
Hysteresis (1)
0.5
0.75
1.0
Leakage current
VDD = 57 V, VCLS = 0 V, DEN = VSS, measure ICLS
Classification current,
applies to both cycles
ICLS
VCL_ON
VCL_H
VCU_OFF
VCU_H
PASS DEVICE (RTN)
1
mA
V
V
µA
(VDD1 = RTN)
0.25
0.43
0.8
Ω
Current limit
VRTN = 1.5 V, VDD = 48 V, pulsed measurement
400
465
535
mA
Inrush limit
VRTN = 2 V, VDD: 0 V → 48 V, pulsed measurement
100
140
180
mA
Foldback voltage threshold
VDD rising
11
12.3
13.6
V
VDD rising
33.9
35
36.1
4.4
4.55
4.76
On resistance
UVLO
UVLO_R
UVLO_H
UVLO threshold
Hysteresis (1)
APb
tAPb
V
VC = 12 V, float VDD1, VDD= 48 V, ARTN = VSS
ON characteristic
VAPD = 2 V, CTL = ARTN, (VAPb- VARTN) = 0.6 V
Leakage current
VAPb = 18 V, (VAPD-VARTN) = 0 V, (VPPD- VVSS) = 0 V
2
Delay
From start of switching to APb active
mA
10
µA
5
9
15
ms
135
145
155
°C
THERMAL SHUTDOWN
Turnoff temperature
TJ rising
Hysteresis (2)
°C
The hysteresis tolerance tracks the rising threshold for a given device.
These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product
warranty.
GATE
(1)
(2)
20
hi
50%
GAT2
lo
hi
50%
time
lo
tDT1
tDT2
Figure 2. GATE and GAT2 Timing and Phasing
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DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
VDD1
VC
f
Oscillator
FRS
CTL
50kW
CONV.
OFF
enb
4 ms
Softstart
Control
D Q
CK
1
+
CLRB
mA
ARTN 40
(pk)
375kW
GATE
DT
COM
GAT 2
f
Converter
Thermal
Monitor
+
0.55V -
ARTN
sa
pa
softstart
CTL
APb Logic
Switch
Matrix
ARTN
BLNK
ARTN
VDD
Ref
Global Cvtr.
enb
Enable
+
0.75V
CS
VB
Reg
Deadtime
50kW
f
2.5V
uvlo, f pd
11V and
9V
APb
CLS
Class
Logic and
Regulator
pa, sa, den
22V and
21.25V
12.5V
and 1V
35V and
30.5V
uvlo
DEN
V SS
400ms
CONV.
OFF
R Q
S
7.8V
PPD
1.55V and
1.25V
H
L
1
ILIM
+
0
-
EN
pa
Common
Circuits and
PoE Thermal
Monitor
f pd
Hotswap
MOSFET
RTN
VSS
50mW
sa
1.5V and
1.2V
ARTN
den
APD
4V
PWP PACKAGE
(TOP VIEW)
CTL
VB
CS
COM
GATE
VC
GAT2
ARTN
RTN
VSS
6
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
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APb
FRS
BLNK
APD
DT
CLS
PPD
DEN
VDD
VDD1
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PIN FUNCTIONS
NAME
NO.
TYPE
DESCRIPTION
CTL
1
I
The control loop input to the PWM (pulse width modulator), typically driven by output regulation feedback (e.g.
optocoupler). Use VB as a pullup for CTL.
VB
2
O
5.1 V bias rail for dc/dc control circuits and the feedback optocoupler. Typically bypass with a 0.1 µF to ARTN.
CS
3
I/O
DC/DC converter switching MOSFET current sense input. See RCS in Figure 1.
COM
4
GATE
5
O
Gate drive output for the main dc/dc converter switching MOSFET.
VC
6
I/O
DC/DC converter bias voltage. Connect a 0.47 µF (minimum) ceramic capacitor to ARTN at the pin, and a
larger capacitor to power startup.
GAT2
7
O
Gate drive output for a second dc/dc converter switching MOSFET (see Figure 1).
ARTN
8
ARTN is the dc/dc converter analog return. Tie to COM, and RTN for most applications.
RTN
9
RTN is the output of the PoE hotswap MOSFET.
VSS
10
VDD1
11
I
Source of dc/dc converter startup current. Connect to VDD for many applications.
VDD
12
I
Connect to the positive PoE input power rail. VDD powers the PoE interface circuits. Bypass with a 0.1 µF
capacitor and protect with a TVS.
DEN
13
I/O
PPD
14
I
Raising VPPD - VVSS above 1.55 V enables the hotswap MOSFET and activates APb. Connecting PPD to VDD
enables classification when APD is active. Tie PPD to VSS or float when not used.
CLS
15
I
Connect a resistor from CLS to VSS to program classification current per Table 1.
DT
16
I
Connect a resistor from DT to ARTN to set the GATE to GAT2 dead time. Tie DT to VB to disable GAT2
operation.
APD
17
I
Raising VAPD-VARTN above 1.5 V disables the internal hotswap MOSFET, turns class off, and forces APb
active. This forces power to come from a external VDD1-VRTN adapter. Tie APD to ARTN when not used.
BLNK
18
I
Connect to ARTN to utilize the internally set current-sense blanking period, or connect a resistor from BLNK to
ARTN to program a more accurate period.
FRS
19
I
Connect a resistor from FRS to ARTN to program the converter switching frequency. FRS may be used to
synchronize the converter to an external timing source.
APb
20
O
Active low output that indicates PPD (first level) or APD are active.
Gate driver return, connect to ARTN, and RTN for most applications.
Connect to the negative power rail derived from the PoE source.
Connect a 24.9 kΩ resistor from DEN to VDD to provide the PoE detection signature. Pulling this pin to VSS
during powered operation causes the internal hotswap MOSFET to turn off.
PIN DESCRIPTION
See Figure 1 for component reference designators (RCS for example), and the Electrical Characteristics table for
values denoted by reference (VCSMAX for example). Electrical Characteristic values take precedence over any
numerical values used in the following sections.
APD
APD (adapter priority detect) forces power to come from an external adapter connected from VDD1 to RTN by
opening the hotswap switch, disabling the CLS output (see PPD pin description), and enabling the APb output. A
resistor divider is recommended on APD when it is connected to an external adapter. The divider provides ESD
protection, leakage discharge for the adapter ORing diode, and input voltage qualification. Voltage qualification
assures the adapter output voltage is high enough that it can support the PD before the PoE current is cut off.
Select the APD divider resistors per Equation 1 where VADPTR-ON is the desired adapter voltage that enables the
APD function as adapter voltage rises.
RAPD1 = RAPD2 ´
VADPTR_OFF =
(VADPTR_ON
R APD1 + R APD2
R APD2
- VAPDEN
´
(VAPDEN
) VAPDEN
- VAPDH )
(1)
Place the APD pull-down resistor adjacent to the APD pin.
APD should be tied to ARTN when not used.
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BLNK
Blanking provides an interval between GATE going high and the current-control comparators on CS actively
monitoring the input. This delay allows the normal turn-on current transient (spike) to subside before the
comparators are active, preventing undesired short duty cycles and premature current limiting.
Connect BLNK to ARTN to obtain the internally set blanking period. Connect a resistor from BLNK to ARTN for a
more accurate, programmable blanking period. The relationship between the desired blanking period and the
programming resistor is defined by Equation 2.
RBLNK (kW ) = tBLNK (ns )
(2)
Place the resistor adjacent to the BLNK pin when it is used.
CLS
A resistor from CLS (class) to VSS programs the classification current per the IEEE standard. The PD power
ranges and corresponding resistor values are listed in Table 1. The power assigned should correspond to the
maximum average power drawn by the PD during operation.
Table 1. Class Resistor Selection
POWER AT PD
RESISTOR
(Ω)
CLASS
MINIMUM
(W)
MAXIMUM
(W)
0
0.44
12.95
1270
1
0.44
3.84
243
2
3.84
6.49
137
3
6.49
12.95
90.9
4
12.95
25.5
63.4
NOTES
Minimum may be reduced by pulsed loading. Serves as a catch-all default class.
Maximum type 2 hardware class current levels not supported by TPS23757.
CS
The CS (current sense) input for the dc/dc converter should be connected to the high side of the switching
MOSFET’s current sense resistor (RCS). The current-limit threshold, VCSMAX, defines the voltage on CS above
which the GATE ON time will be terminated regardless of the voltage on CTL.
The TPS23757 provides internal slope compensation (155 mV, VSLOPE), an output current for additional slope
compensation, a peak current limiter, and an off-time pull-down to this pin.
Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy
traces such as the gate drive signal.
CTL
CTL (control) is the voltage-control loop input to the PWM (pulse width modulator). Pulling VCTL below VZDC (zero
duty cycle voltage) causes GATE to stop switching. Increasing VCTL above VZDC raises the switching MOSFET
programmed peak current. The maximum (peak) current is requested at approximately VZDC + (2 × VCSMAX). The
ac gain from CTL to the PWM comparator is 0.5. The internal divider from CTL to ARTN is approximately 100
kΩ.
Use VB as a pull up source for CTL.
DEN
DEN (detection and enable) is a multifunction pin for PoE detection and inhibiting operation from PoE power.
Connect a 24.9 kΩ resistor from DEN to VDD to provide the PoE detection signature. DEN goes to a
high-impedance state when VVDD-VVSS is outside of the detection range. Pulling DEN to VSS during powered
operation causes the internal hotswap MOSFET and class regulator to turn OFF, while the reduced detection
resistance prevents the PD from properly re-detecting. See Using DEN to Disable PoE.
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DT
Dead-time programming sets the delay between GATE and GAT2 to prevent overlap of MOSFET ON times as
shown in Figure 2. GAT2 turns the second MOSFET OFF when it transitions high. Both MOSFETs should be
OFF between GAT2 going high to GATE going high, and GATE going low to GAT2 going low. The maximum
GATE ON time is reduced by the programmed dead-time period. The dead time period is specified with 1 nF of
capacitance on GATE and GAT2. Different loading on these pins will change the effective dead time.
A resistor connected from DT to ARTN sets the delay between GATE and GAT2 per Equation 3.
RDT (kW ) =
tDT (ns )
2
(3)
Connect DT to VB to set the dead time to 0 and turn GAT2 OFF.
FRS
Connect a resistor from FRS (frequency and synchronization) to ARTN to program the converter switching
frequency. Select the resistor per the following relationship.
RFRS (kW) =
17250
fSW (kHz)
(4)
The converter may be synchronized to a frequency above its maximum free-running frequency by applying short
ac-coupled pulses into the FRS pin per Figure 26.
The FRS pin is high impedance. Keep the connections short and apart from potential noise sources. Special care
should be taken to avoid crosstalk when synchronizing circuits are used.
GATE
Gate drive output for the dc/dc converter’s main switching MOSFET. GATE’s phase turns the main switch ON
when it transitions high, and OFF when it transitions low. GATE is held low when the converter is disabled.
GAT2
GAT2 is the second gate drive output for the dc/dc converter. GAT2’s phase turns the second switch OFF when
it transitions high, and ON when it transitions low. This drives flyback synchronous rectifiers per Figure 1. See
the DT Pin Description for GATE to GAT2 timing. Connecting DT to VB disables GAT2 in a high-impedance
condition. GAT2 is low when the converter is disabled.
PPD
PPD is a multifunction pin that has two voltage thresholds, PPD1 and PPD2.
PPD1 permits power to come from an external low voltage adapter, e.g., 24 V, connected from VDD to VSS by
over-riding the normal hotswap UVLO. Voltage on PPD above 1.55 V (VPPDEN) enables the hotswap MOSFET,
inhibits class current, and enables APb. A resistor divider per Figure 31 provides ESD protection, leakage
discharge for the adapter ORing diode, reverse adapter protection, and input voltage qualification. Voltage
qualification assures the adapter output voltage is high enough that it can support the PD before it begins to draw
current.
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RPPD1
æ
çV
ADPTR_ON - VPPDEN
= ç
ç
VPPDEN
- IPPD
ç
RPPD2
è
ö
÷
÷
÷
÷
ø
é
æ (VPP DEN - VPPDH )
öù
VADP TR_OFF = (VPPDEN - VPPDH )+ êRP PD1 ´ ç
- IPP D ÷ ú
ç
÷ú
RPPD2
êë
è
øû
(5)
PPD2 enables normal class regulator operation when VPPD is above 8.3 V to permit normal classification when
APD is used in conjunction with diode DVDD (see Figure 30). Tie PPD to VDD when PPD2 operation is desired.
The PPD pin has a 5 µA internal pull-down current.
Locate the PPD pull-down resistor adjacent to the pin when used.
PPD may be tied to VSS or left open when not used.
RTN, ARTN, COM
RTN is internally connected to the drain of the PoE hotswap MOSFET, while ARTN is the quiet analog return for
the dc/dc controller. COM serves as the return path for the gate drivers and should be tied to ARTN on the circuit
board. The ARTN / COM / RTN net should be treated as a local reference plane (ground plane) for the dc/dc
control and converter primary. RTN and (ARTN/COM) may be separated by several volts for special applications.
APb
APb is an active low output that indicates [ (VAPD > 1.5 V) OR (1.55 V ≤ VPPD ≤ 8.3 V) ]. APb is valid after both a
delay of tAPb from the start of converter switching, and [VCTL ≤ (VB – 1 V)]. Once APb is valid, VCTL will not effect
it. APb will become invalid if the converter goes back into softstart, overtemperature, or is held off by the PD
during CIN recharge (inrush). APb is referenced to ARTN and is intended to drive the diode side of an
optocoupler. APb should be left open or tied to ARTN if not used.
VB
VB is an internal 5.1 V regulated dc/dc controller supply rail that is typically bypassed by a 0.1 µF capacitor to
ARTN. VB should be used to bias the feedback optocoupler.
VC
VC is the bias supply for the dc/dc controller. The MOSFET gate drivers run directly from VC. VB is regulated
down from VC, and is the bias voltage for the rest of the converter control. A startup current source from VDD1 to
VC is controlled by a comparator with hysteresis to implement the converter bootstrap startup. VC must be
connected to a bias source, such as a converter auxiliary output, during normal operation.
A minimum 0.47 µF capacitor, located adjacent to the VC pin, should be connected from VC to COM to bypass
the gate driver. A larger total capacitance is required for startup to provide control power between the time the
converter starts switching and the availability of the converter auxiliary output voltage.
VDD
VDD is the positive input power rail that is derived from the PoE source (PSE). VDD should be bypassed to VSS
with a 0.1 µF capacitor as required by the IEEE standard. A transient suppressor diode (TVS), such as SMAJ58A
should be connected from VDD to VSS to protect against overvoltage transients.
VDD1
VDD1 is the dc/dc converter startup supply. Connect to VDD for many applications. VDD1 may be isolated by a
diode from VDD to support PoE priority operation.
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VSS
VSS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-limited
hotswap switch that connects it to RTN. VSS is clamped to a diode drop above RTN by the hotswap switch.
A local VSS reference plane should be used to connect the input bypass capacitor, TVS, and RCLS.
TYPICAL CHARACTERISTICS
DETECTION BIAS CURRENT
vs
VOLTAGE
PoE CURRENT LIMIT
vs
TEMPERATURE
8
485
7
480
25°C
Current Limit − mA
IVDD − Bias Current − µA
6
5
125°C
4
3
475
470
2
−40°C
465
1
0
0
2
4
6
8
460
−40
10
(VVDD − VVSS) − PoE Voltage − V
0
20
40
60
80
100
120
TJ - Junction Temperature - oC
G001
Figure 3.
Figure 4.
CONVERTER START TIME
vs
TEMPERATURE
CONVERTER STARTUP CURRENT
vs
VVDD1
160
6
VVC = 8.6V
VVDD1 = 10.2 V
o
TJ = -40 C
140
5
IVC − Source Current − mA
CVC = 22 mF
120
Start Time − ms
−20
100
80
60
o
TJ = 25 C
4
TJ = 125oC
3
2
1
40
VVDD1 = 35 V
20
−40
0
−20
0
20
40
60
80
100
120
5
10
TJ - Junction Temperature - oC
Figure 5.
15 20
25
30
35
40
45 50
55 60
VVDD1-RTN − V
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
CONTROLLER BIAS CURRENT
vs
TEMPERATURE
CONTROLLER BIAS CURRENT
vs
VOLTAGE
3000
4000
GATE and GAT2 Open
VVC = 12 V
GATE, GAT2 open
o
TJ = 25 C
3500
2500
960 kHz
VC − Bias Current − mA
IVC − Sinking −mA
3000
2000
937 kHz
484 kHz
1500
245 kHz
100 kHz
1000
2500
480 kHz
2000
100 kHz
1500
50 kHz
250 kHz
1000
500
500
50 kHz
0
−40
VCTL = 0 V
VCTL = 0 V
0
−20
0
20
40
60
80
100
6
120
TJ - Junction Temperature - °C
8
10
12
14
16
G005
Figure 7.
Figure 8.
SWITCHING FREQUENCY
vs
TEMPERATURE
SWITCHING FREQUENCY
vs
PROGRAM CONDUCTANCE
600
18
VC − Controller Bias Voltage − V
1200
1200
1100
1000
1000
RFRS = 17.35 kΩ (937 kHz)
300
900
RFRS = 69.8 kΩ (245 kHz)
RFRS = 347 kΩ (50 kHz)
200
800
RFRS = 173 kΩ (100 kHz)
700
100
Switching Frequency − kHz
Switching Frequency − kHz
400
Switching Frequency − kHz
RFRS = 34.6 kΩ (484 kHz)
500
Ideal
800
600
Typical
400
200
0
−40
600
−20
0
20
40
60
80
TJ - Junction Temperature - °C
100
120
0
G007
0
10
20
30
40
50
Programmed Resistance (106 / RFRS) − Ω−1
Figure 9.
12
60
G008
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
MAXIMUM DUTY CYCLE
vs
TEMPERATURE
CURRENT SLOPE COMPENSATION VOLTAGE
vs
TEMPERATURE
79
155
78
RFRS = 347 kW (50 kHz)
154
RFRS = 69.8 kW (245 kHz)
76
153
VSLOPE − mVPP
Maximum Duty Cycle − %
77
75
RFRS = 34.6 kW (484 kHz)
74
RFRS = 26.7 kW (623 kHz)
73
152
151
RFRS = 21.5 kW (766 kHz)
72
150
70
−40
−20
0
20
40
60
80
100
149
−40
120
TJ - Junction Temperature - °C
0
20
40
60
G009
Figure 11.
Figure 12.
CURRENT SLOPE COMPENSATION CURRENT
vs
TEMPERATURE
BLANKING PERIOD
vs
TEMPERATURE
Blanking Period − ns
45
40
G010
105
260
95
255
RBLNK = 100 kΩ
250
85
RBLNK = 249 kΩ
245
75
240
RBLNK = RTN
RBLNK = 49.9 kΩ
55
−20
0
20
40
60
80
100
TJ − Junction Temperature − °C
120
265
45
−40
30
−40
100
115
65
35
80
TJ − Junction Temperature − °C
50
ISLOPE − µAPP
−20
Blanking Period − ns
RFRS = 17.3 kW (937 kHz)
71
235
230
−20
0
20
40
60
80
100
120
TJ - Junction Temperature - °C
120
G012
G011
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
DEAD TIME
vs
DEAD TIME RESISTANCE (RDT )
450
18
400
14
350
10
300
6
250
2
200
−2
150
−6
100
−10
50
−14
200
−18
400
100
0
0
50
100
150
200
250
300
350
900
800
Difference From Computed − ns
RBLNK − kΩ
700
Dead Time - ns
Blanking Period − ns
BLANKING PERIOD
vs
BLANKING RESISTANCE (RBLNK)
Ideal
600
500
400
Typical
300
0
G013
0
50
100 150 200 250 300
Dead Time Resistance - kW
Figure 15.
350
400
Figure 16.
APb DELAY TIME
vs
TEMPERATURE
11
APb Delay Time − ms
10
9
8
7
6
−40 −20
0
20
40
60
80
100 120 140
o
Temperature - C
Figure 17.
DETAILED DESCRIPTION
PoE OVERVIEW
The following text is intended as an aid in understanding the operation of the TPS23757 but not as a substitute
for the actual IEEE 802.3-2008 or IEEE 802.3at standard. The pending IEEE 802.3at standard is an update to
IEEE 802.3-2008 clause 33 (PoE), adding high-power options and enhanced classification. Generally speaking, a
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device compliant to IEEE 802.3-2008 will be referred to as a type 1 device (PD or PSE), and devices with high
power and enhanced classification will be referred to as type 2 devices (PD or PSE). Standards change and
should always be referenced when making design decisions. The TPS23757 supports type 1 PDs as a result of
the limited-current capability and lack of type 2 hardware class detection. Type 1 devices are encompassed
within the new standard, providing the same features and functions as devices in service since 2003.
The IEEE 802.3-2008 (802.3at) standard defines a method of safely powering a PD over a cable by power
sourcing equipment (PSE), and then removing power if a PD is disconnected. The process proceeds through an
idle state and three states of detection, classification, and operation. The PSE leaves the cable unpowered (idle
state) while it periodically looks to see if something has been plugged in; this is referred to as detection. The low
power levels used during detection are unlikely to damage devices not designed for PoE. If a valid PD signature
is present, the PSE my inquire how much power the PD requires; this is referred to as classification. The PSE
may then power the PD if it has adequate capacity.
Type 2 PSEs are required to do type 1 hardware classification plus a (new) data-layer classification, or an
enhanced type 2 hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL)
classification. A type 2 PD must do type 2 hardware classification as well as DLL classification. A type 1 PD may
have passive classification ( class 0, < 5 mA) or active type 1 hardware class (1 through 3) per IEEE 802.3-2008.
DLL communication occurs after power-on and the ethernet data link has been established by the applications
circuits in the PD (not the power interface). It may be used by type 1 PDs and must be implemented by type 2
PDs.
Shutdown
Classify
Detect
6.9
Maximum Input
Voltage
Must Turn On byVoltage Rising
Lower Limit Operating Range
Must Turn Off by Voltage Falling
Classification
Upper Limit
Classification
Lower Limit
Detection
Upper Limit
Detection
Lower Limit
IEEE 802.3-2005
Once started, the PD must present the maintain power signature (MPS) to assure the PSE that it is still present.
The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns
the PSE to the idle state. Figure 18 shows the operational states as a function of PD input voltage. The upper
half is for IEEE 802.3-2008, and the lower half shows specific differences for IEEE 802.3at. The dashed lines in
the lower half indicate these are the same (e.g., detect and class) for both.
Normal Operation
42.5
0
30
37
57 PI Voltage (V)
42
Normal Operation
250ms
Transient
Class-Mark
Transition
20.5
Lower Limit 13W Op.
10.1 14.5
Mark
T2 Reset
Range
IEEE 802.3at
2.7
Figure 18. Operational States for PD
The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input
requirements differ from PSE output requirements to account for voltage drops in the channel and operating
margin. The standard allots the maximum loss to the cable regardless of the actual installation to simplify
implementation. IEEE 802.3-2008 (and IEEE 802.3at type 1) was designed to run over infrastructure including
ISO/IEC 11801 class C (CAT3 per TIA/EIA-568) that may have had AWG 26 conductors and 20 Ω power loops.
IEEE 802.3at (type 2) cabling power loss allotments and voltage drops have been adjusted for 12.5 Ω power
loops per ISO/IEC11801 class D (CAT5 or higher per TIA/EIA-568, typically AWG #24 conductors). Table 2
shows key operational limits broken out for the two revisions of the standard.
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Table 2. Comparison of Operational Limits
POWER LOOP
RESISTANCE
(max)
PSE
OUTPUT POWER
(min)
PSE STATIC
OUTPUT VOLTAGE
(min)
PD INPUT
POWER
(max)
POWER ≤
12.95 W
POWER >
12.95 W
'2008 &
802.3at type 1
20 Ω
15.4 W
44 V
12.95 (13) W
37 V–57 V
N/A
802.3at type 2
12.5 Ω
30 W
50 V
25.5 W
37 V–57 V
42.5 V–57 V
STANDARD
STATIC PD INPUT VOLTAGE
The PSE can apply voltage either between the RX and TX pairs (pins 1 - 2 and 3 - 6 for 10baseT or 100baseT),
or between the two spare pairs (4 - 5 and 7 - 8) in either polarity. Power application to the same pin combinations
in 1000baseT systems is recognized in 802.3at. 1000baseT systems can handle data on all pairs, eliminating the
spare pair terminology. The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode
bridges to accept power from any of the possible PSE configurations. The voltage drops associated with the
input bridges create a difference between the standard limits at the PI and the TPS23757 specifications.
A compliant type 1 PD per IEEE 802.3at has the same requirements as a PD per IEEE 802.3-2008.
Threshold Voltages
The TPS23757 has a number of internal comparators with hysteresis for stable switching between the various
states. Figure 19 relates the parameters in the Electrical Characteristics section to the PoE states. The mode
labeled Idle between classification and operation implies that the DEN, CLS, and RTN pins are all high
impedance.
Functional
State
PD Powered
Idle
Classification
VDD -VSS
Detection
VCL_H
VCL_ON
VCU_H
VCU_OFF
VUVLO_H
V UVLO_R
Note: Variable names refer to Electrical Characteristic
Table parameters
Figure 19. Threshold Voltages
PoE Startup Sequence
The waveforms of Figure 20 demonstrate detection, classification, and startup from a PSE with type 1 hardware
classification. The key waveforms shown are VVDD-VVSS, VRTN-VVSS, and IPI. This figure shows two detection
cycles (a minimum of two levels are required), a class cycle (a type 2 PSE need only do 1 hardware class cycle if
it reads class 0 through 3), and startup. VRTN to VSS falls as the TPS23757 charges CIN with inrush-limited current
following application of full voltage. Subsequently, the converter starts up, drawing current as seen in the IPI
waveform.
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Cvtr. Starts
Inrush
50 mA/div
IPI
Class
10 V/div
Detect
(Four Point)
VVDD - VVSS
VRTN - VVSS
t - Time - 50 ms/div
Figure 20. Startup
Detection
The TPS23757 drives DEN to VSS whenever VVDD-VVSS is in the detection state per Figure 19. When the input
voltage rises above VCL-ON, the DEN pin goes to an open-drain condition to conserve power. While in detection,
RTN is high impedance, and almost all the internal circuits are disabled. An RDEN of 24.9 kΩ (1%), presents the
correct signature. It may be a small, low-power resistor since it only sees a stress of about 5 mW. A valid PD
detection signature is an incremental resistance ( ΔV / ΔI ) between 23.75 kΩ and 26.25 kΩ at the PI.
The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the
parallel combination of RDEN and internal VDD loading. The input diode bridge’s incremental resistance may be
hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is
partially cancelled by the TPS23757's effective resistance during detection.
Detection is the same for type 1 and type 2 PDs.
Hardware Classification
Hardware classification allows a PSE to determine a PD’s power requirements before powering, and helps with
power management once power is applied. The PSE applies a voltage of between 14.5 V and 20.5 V at the PD
PI and the PD responds with a current representing the class per the standard. A type 1 PD presents class 0 - 3
in hardware to indicate it is a low-power device (no change from IEEE 802.3-2008). Type 1 PD hardware class
interoperates properly with type 2 PSEs. A type 1 PD must present the hardware class which covers its
maximum power draw. IEEE 802.3at provides a new option for type 1 PDs to negotiate their power allocation to
a lower level using DLL after startup. DLL communication is implemented by the ethernet communication system
in the PD and is not implemented by the TPS23757.
The maximum power entries in Table 1 determine the class the PD must advertise. The PSE may disconnect a
PD if it draws more than its stated class power, which may be the hardware class or an optional lower
DLL-derived power level. The standard permits the PD to draw limited current peaks that increase the
instantaneous power above the Table 1 limit, however the average power requirement always applies.
The TPS23757 disables classification above VCU_OFF to avoid excessive power dissipation. CLS is turned off
during PD thermal limit or when APD, PPD (level 1), or DEN are active. CLS is enabled when APD and PPD
(level 2) are active. The CLS output is inherently current limited, but should not be shorted to VSS for long periods
of time.
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Inrush and Startup
The TPS23757 provides a 140 mA inrush limit that is compatible with both type 1 and type 2 PSEs. The
TPS23757’s internal softstart permits control of the converter startup preventing the converter from exceeding the
PSE output limitations. APb becomes valid within tAPb after converter switching starts, or if an adapter is plugged
in while the PD is operating from a PSE.
Maintain Power Signature
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating
voltage is applied. A valid MPS consists of a minimum dc current of 10 mA (or a 10 mA pulsed current for at
least 75 ms every 225 ms) and an ac impedance lower than 26.25 kΩ in parallel with 0.05 µF. The ac impedance
is usually accomplished by the minimum operating CIN requirement of 5 µF. When either APD or DEN is used to
force the hotswap switch off, the dc MPS will not be met. A PSE that monitors the dc MPS will remove power
from the PD when this occurs. A PSE that monitors only the ac MPS may remove power from the PD.
Startup and Converter Operation
The internal PoE UVLO (Under Voltage Lock Out) circuit holds the hotswap switch off before the PSE provides
full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and
classification. The converter circuits will discharge CIN, CVC, and CVB while the PD is unpowered. Thus VVDD-VRTN
will be a small voltage just after full voltage is applied to the PD, as seen in Figure 20. The PSE drives the PI
voltage to the operating range once it has decided to power up the PD. When VVDD rises above the UVLO
turn-on threshold (VUVLO-R, ~35 V) with RTN high, the TPS23757 enables the hotswap MOSFET with a ~140 mA
(inrush) current limit as seen in Figure 21. Converter switching is disabled while CIN charges and VRTN falls from
VVDD to nearly VVSS, however the converter startup circuit is allowed to charge CVC (the bootstrap startup
capacitor). Converter switching is allowed if the PD is not in inrush, converter OTSD (over-temperature
shutdown) is not active, and the VC UVLO permits it. Once the inrush current falls about 10% below the inrush
current limit, the PD current limit switches to the operational level (~450 mA). Continuing the startup sequence
shown in Figure 21, VVC continues to rise until the startup threshold (VCUV, ~9 V) is exceeded, turning the startup
source off and enabling switching. The VB regulator is always active, powering the internal converter circuits as
VVC rises. There is a slight delay between the removal of charge current and the start of switching as the softstart
ramp sweeps above the VZDC threshold. VVC falls as it powers both the internal circuits and the switching
MOSFET gates. If the converter control bias output rises to support VVC before it falls to VCUV – VCUVH ( ~5.5 V),
a successful startup occurs. APb in Figure 21 becomes active within tAPb from the start of switching, indicating
that an adapter is plugged in.
10 V/div
VAPb - VRTN
Inrush
100 mA/div
IPI
PI Powered
10 V/div
VVC - VRTN
Switching Starts
2 V/div
50 V/div
VOUT
VVDD - VRTN
t - Time - 10 ms/div
Figure 21. Power Up and Start
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If VVDD- VVSS drops below the lower PoE UVLO (VUVLO-R – VUVLO-H, ~30.5 V), the hotswap MOSFET is turned off,
but the converter will still run. The converter will stop if VVC falls below the converter UVLO (VCUV – VCUVH,
~5.5 V), the hotswap is in inrush current limit, 0% duty cycle is demanded by VCTL (VCTL < VZDC, ~1.5 V), or the
converter is in thermal shutdown.
PD Hotswap Operation
IEEE 802.3at has taken a new approach to PSE output limiting. A type 2 PSE must meet an output current vs.
time template with specified minimum and maximum sourcing boundaries. The peak output current may be as
high as 50 A for 10 µs or 1.75 A for 75 ms. This makes robust protection of the PD device even more important
than it was in IEEE 802.3-2008.
The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit and
deglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with VRTN VVSS rising as a result. If VRTN rises above ~12 V for longer than ~400 µs, the current limit reverts to the inrush
value, and turns the converter off. The 400 µs deglitch feature prevents momentary transients from causing a PD
reset, provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 22 shows an
example of recovery from a 14 V PSE rising voltage step. The hotswap MOSFET goes into current limit,
overshooting to a relatively low current, recovers to ~450 mA full current limit, and charges the input capacitor
while the converter continues to run. The MOSFET did not go into foldback because VRTN – VVSS was below 12
V after the 400 µs deglitch.
IPI
200 mA/div
10 V/div
CIN Completes Charge
While Converter Operates
VRTN - VVSS
11.8 V at 400 ms
14 V Input Step
20 V/div
VVDD - VVSS
t - Time - 500 ms/div
Figure 22. Response to PSE Step Voltage
The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like startup or
operation into a VDD to RTN short cause high power dissipation in the MOSFET. An overtemperature shutdown
(OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The
hotswap MOSFET will be re-enabled with the inrush current limit when exiting from an overtemperature event.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn OFF. This feature
allows a PD with Option three ORing per Figure 23 to achieve adapter priority. Care must be taken with
synchronous converter topologies that can deliver power in both directions.
The hotswap switch will be forced off under the following conditions:
1. VAPD above VAPDEN (~1.5 V)
2. VDEN < VPD-DIS when VVDD– VVSS is in the operational range
3. PD overtemperature
4. (VVDD– VVSS) < PoE UVLO (~30.5 V).
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Converter Controller Features
The TPS23757 dc/dc controller implements a typical current-mode control as shown in the Functional Block
Diagram. Features include oscillator, overcurrent and PWM comparators, current-sense blanker, dead-time
control, softstart, and gate driver. In addition, an internal slope-compensation ramp generator, frequency
synchronization logic, thermal shutdown, and startup current source with control are provided.
The TPS23757 is optimized for isolated converters, and does not provide an internal error amplifier. Instead, the
optocoupler feedback is directly fed to the CTL pin which serves as a current-demand control for the PWM.
There is an offset of VZDC (~1.5 V) and 2:1 resistor divider between the CTL pin and the PWM. A VCTL below
VZDC will stop converter switching, while voltages above (VZDC + (2 × VCSMAX)) will not increase the requested
peak current in the switching MOSFET. Optocoupler biasing design is eased by this limited control range.
Bootstrap Topology
The internal startup current source and control logic implement a bootstrap-type startup as discussed in Startup
and Converter Operation. The startup current source charges CVC from VDD1 when the converter is disabled
(either by the PD control or the VC control) to store enough energy to start the converter. Steady-state operating
power must come from a converter (bias winding) output or other source. Loading on VC and VB must be minimal
while CVC charges, otherwise the converter may never start. The optocoupler will not load VB when the converter
is off for most situations, however care should be taken in ORing topologies where the output is powered when
PoE is off.
The converter will shut off when VC falls below its lower UVLO. This can happen when power is removed from
the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall
including the one that powers VC. The control circuit discharges VC until it hits the lower UVLO and turns off. A
restart will initiate as described in Startup and Converter Operation if the converter turns off and there is sufficient
VDD1 voltage. This type of operation is sometimes referred to as hiccup mode which provides robust output short
protection by providing time-average heating reduction of the output rectifier.
The bootstrap control logic disables most of the converter controller circuits except the VB regulator and internal
reference. Both GATE and GAT2 (assuming GAT2 is enabled) will be low when the converter is disabled. FRS,
BLNK, and DT will be at ARTN while the VC UVLO disables the converter. While the converter runs, FRS, BLNK,
and DT will be about 1.25 V.
The startup current source transitions to a resistance as (VVDD1 – VVC) falls below 7 V, but will start the converter
from adapters within tST. The lower test voltage for tST was chosen based on an assumed adapter tolerance, but
is not meant to imply a hard cutoff exists. Startup takes longer and eventually will not occur as VDD1 decreases
below the test voltage. The bootstrap source provides reliable startup from widely varying input voltages, and
eliminates the continual power loss of external resistors. The startup current source will not charge above the
maximum recommended VVC if the converter is disabled and there is sufficient VDD1 to charge higher.
Current Slope Compensation and Current Limit
Current-mode control requires addition of a compensation ramp to the sensed inductive (transformer or inductor)
current for stability at duty cycles near and over 50%. The TPS23757 has a maximum duty cycle limit of 78%,
permitting the design of wide input-range flyback and active clamp converters with a lower voltage stress on the
output rectifiers. While the maximum duty cycle is 78%, converters may be designed that run at duty cycles well
below this for a narrower, 36 V to 57 V PI range. The TPS23757 provides a fixed internal compensation ramp
that suffices for most applications.
The TPS23757 provides internal, frequency independent, slope compensation (150 mV, VSLOPE) to the PWM
comparator input for current-mode control-loop stability. This voltage is not applied to the current-limit comparator
whose threshold is 0.55 V (VCSMAX). If the provided slope is not sufficient, the effective slope may be increased
by addition of RS per Figure 27. The additional slope voltage is provided by (ISL-EX × RS). There is also a small dc
offset caused by the ~2.5 µA pin current. The peak current limit does not have duty cycle dependency unless RS
is used. This makes it easier to design the current limit to a fixed value. See Current Slope Compensation for
more information.
The internal comparators monitoring CS are isolated from the IC pin by the blanking circuits while GATE is low,
and for a short time (blanking period) just after GATE switches high. A 440 Ω (max) equivalent pull down on CS
is applied while GATE is low.
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Blanking - RBLNK
The TPS23757 provides a choice between internal fixed and programmable blanking periods. The blanking
period is specified as an increase in the minimum GATE on time over the inherent gate driver and comparator
delays. The default period (see the Electrical Characteristics table) is selected by connecting BLNK to RTN, and
the programmable period is set with RBLNK.
The TPS23757 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This
avoids current-sense waveform distortion, which tends to get worse at light output loads. There may be some
situations or designers that prefer an R-C approach. The TPS23757 provides a pull-down on CS during the
GATE off time to improve sensing when an R-C filter must be used. The CS input signal should be protected
from nearby noisy signals like GATE drive and the switching MOSFET drain.
Dead Time
The TPS23757 features two switching MOSFET gate drivers to ease implementation of high-efficiency
topologies. Specifically, these include active (primary) clamp topologies and those with synchronous drivers that
are hard-driven by the control circuit. In all cases, there is a need to assure that both driven MOSFETs are not
on at the same time. The DT pin programs a fixed time period delay between the turn-off of one gate driver until
the turn-on of the next. This feature is an improvement over the repeatability and accuracy of discrete solutions
while eliminating a number of discrete parts on the board. Converter efficiency is tuned with this one repeatable
adjustment. The programmed dead time is the same for both GATE-to-GAT2 and GAT2-to-GATE transitions.
The dead time period is specified with some capacitive loading and is triggered from internal signals that are
several stages back in the driver to eliminate the effects of the gate waveform. The actual dead-time will be
somewhat dependent on the gate loading. The turnoff of GAT2 coincides with the start of the internal clock
period.
Connecting DT to VB disables GAT2, which goes to a high-impedance state.
GATE’s phase turns the main switch on when it transitions high, and OFF when it transitions low. GAT2’s phase
turns the second switch OFF when it transitions high, and on when it transitions low. Both switches should be
OFF when GAT2 is high and GATE is low. The signal phasing is shown in Figure 2. Many topologies that use
secondary-side synchronous rectifiers also use N-Channel MOSFETs driven through a gate-drive transformer.
The proper signal phase for these rectifiers may be achieved by inverting the phasing of the secondary winding
(swapping the leads). Use of the two gate drives is shown in Figure 1.
FRS and Synchronization
The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the
TPS23757 converter to a higher frequency. The internal oscillator sets the maximum duty cycle at 78% and
controls the slope-compensation ramp circuit. Synchronization may be accomplished by applying a short pulse
(TSYNC) of magnitude VSYNC to FRS as shown in Figure 26. The synchronization pulse terminates the potential
on-time period, and the off-time period does not begin until the pulse terminates. Reducing the on-time reduces
the available maximum duty cycle.
APb, Startup and Power Management
APb (adapter present) is an active-low multifunction pin that indicates if
[ (1.5 V < VAPD) + (1.55 V < VPPD≤ 8.3 V)] × (VCTL < 4 V) × (pd current limit ≠ Inrush).
The term with VCTL prevents an optocoupler connected to the secondary-side from loading VC before the
converter is started. The APD and PPD terms indicate that an adapter is plugged into the PD, and voltage is
present on them. APb permits applications which run from high-power adapters ( > 13 W) to detect their
presence and adjust the load appropriately. The usage of APb is demonstrated in Figure 1.
Thermal Shutdown
The dc/dc controller has an OTSD that can be triggered by heat sources including the VB regulator, GATE driver,
bootstrap current source, and bias currents. The controller OTSD turns off VB, the GATE driver, and forces the
VC control into an undervoltage state.
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Adapter ORing
Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power
solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular
installation. While most applications only require that the PD operate when both sources are present, the
TPS23757 supports forced operation from either of the power sources. Figure 23 illustrates three options for
diode ORing external power into a PD. Only one option would be used in any particular design. Option 1 applies
power to the TPS23757 PoE input, option 2 applies power between the TPS23757 PoE section and the dc/dc
converter, and option 3 applies power to the output side of the converter. Each of these options has advantages
and disadvantages. Many of the basic ORing configurations and discussion contained in application note
Advanced Adapter ORing Solutions using the TPS23753 (literature number SLVA306A), apply to the TPS23757.
VSS
VDD1
VDD
DEN
CLS
Low Voltage
Output
Power
Circuit
TPS23754
RCLS
58V
From Spare
Pairs or
Transformers
0.1uF
RDEN
From Ethernet
Transformers
Optional for PoE Priority
RTN
Adapter
Option 1
Adapter
Option 2
Adapter
Option 3
Figure 23. ORing Configurations
The IEEE standards require that the Ethernet cable be isolated from ground and all other system potentials. The
adapter must meet a minimum 1500 Vac dielectric withstand test between the output and all other connections
for ORing options 1 and 2. The adapter only needs this isolation for option 3 if it is not provided by the converter.
Adapter ORing diodes are shown for all the options to protect against a reverse voltage adapter, a short on the
adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in
option 3.
PPD ORing Features
The TPS23757 provides several additional features for the ORing based on the multifunction PPD pin. These
include APb signaling of an option 1 adapter, use of a 24 V adapter (reduced output power) for option 1, and use
of PoE as a power backup in conjunction with option 2. See the Advanced ORing Techniques section.
Using DEN to disable PoE
The DEN pin may be used to turn the PoE hotswap switch OFF by pulling it to VSS while in the operational state,
or to prevent detection when in the idle state. Figure 24 shows a secondary-referenced implementation used to
turn PoE input off using an optocoupler. A low on DEN forces the hotswap MOSFET OFF during normal
operation. Proper selection of RDEN1 and RDEN2 will draw less than the dc MPS current, allowing the PSE to
disconnect the PD. RDEN1 is chosen to ensure the PSE will not detect the PD once it is turned off. Additional
information is available in Advanced Adapter ORing Solutions using the TPS23753, SLVA306A.
22
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TPS23757
VDD
VDD1
R DEN2
DEN
CLS
R CLS
58 V
0.1mF
RDEN1
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VSS
High to
disable
PoE
Secondary
Ground
Figure 24. PPD ORing
ORing Challenges
Preference of one power source presents a number of challenges. Combinations of adapter output voltage
(nominal and tolerance), power insertion point, and which source is preferred determine solution complexity.
Several factors adding to the complexity are the natural high-voltage selection of diode ORing (the simplest
method of combining sources), the current limit implicit in the PSE, and PD inrush and protection circuits
(necessary for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for
many of the combinations. However the TPS23757 offers several built-in features that simplify some
combinations.
Several examples will demonstrate the limitations inherent in ORing solutions. Diode ORing a 48 V adapter with
PoE (option 1) presents the problem that either source might be higher. A blocking switch would be required to
assure which source was active. A second example is combining a 12 V adapter with PoE using option 2. The
converter will draw approximately four times the current at 12 V from the adapter than it does from PoE at 48 V.
Transition from adapter power to PoE may demand more current than can be supplied by the PSE. The
converter must be turned off while CIN capacitance charges, with a subsequent converter restart at the higher
voltage and lower input current. A third example is use of a 12 V adapter with ORing option 1. The PD hotswap
would have to handle four times the current, and have 1/16 the resistance (be 16 times larger) to dissipate equal
power. A fourth example is that MPS is lost when running from the adapter, causing the PSE to remove power
from the PD. If ac power is then lost, the PD will stop operating until the PSE detects and powers the PD.
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APPLICATION INFORMATION
The TPS23757 will support many power supply topologies that require a single PWM gate drive or two
complementary gate drives and will operate with current-mode control. Figure 1 provides an example of a flyback
with a driven output synchronous rectifier. The TPS23757 may be used in topologies that do not require GAT2,
which may be disabled to reduce its idling loss.
Selecting a converter topology along with a design procedure is beyond the scope of this applications section.
Examples to help in programming the TPS23757 are shown below. Additional special topics are included to
explain the ORing capabilities, frequency dithering, and other design considerations.
For more specific converter design examples refer to the following application notes:
• Designing with the TPS23753 Powered Device and Power Supply Controller, SLVA305
• Designing for High Efficiency with the Active Clamp UCC2891 PWM Controller, SLUA303
• Advanced Adapter ORing Solutions using the TPS23753, SLVA306A
• TPS23757EVM: Evaluation Module for TPS23757, SLVU318
Input Bridges and Schottky Diodes
Using Schottky diodes instead of PN junction diodes for the PoE input bridges and DVDD will reduce the loss of
this function by about 30%. There are however some things to consider when using them.
The IEEE standard specifies a maximum backfeed voltage of 2.8 V . A 100 kΩ resistor is placed between the
unpowered pairs and the voltage is measured across the resistor. Schottky diodes often have a higher reverse
leakage current than PN diodes, making this a harder requirement to meet. Use conservative design for diode
operating temperature, select lower-leakage devices where possible, and match leakage and temperatures by
using packaged bridges to help with this.
Schottky diode leakage current and lower dynamic resistance can impact the detection signature. Setting
reasonable expectations for the temperature range over which the detection signature is accurate is the simplest
solution. Increasing RDEN slightly may also help meet the requirement.
Schottky diodes have proven less robust to the stresses of ESD transients, failing as a short or becoming leaky.
Care must be taken to provide adequate protection in line with the exposure levels. This protection may be as
simple as ferrite beads and capacitors.
A general recommendation for the input rectifiers are 1 A or 2 A, 100 V rated discrete or bridge diodes.
Protection, D1
A TVS, D1, across the rectified PoE voltage per Figure 25 must be used. An SMAJ58A, or a part with equal to or
better performance, is recommended for general indoor applications. If an adapter is connected from VDD1 to
RTN, as in ORing option 2 above, voltage transients caused by the input cable inductance ringing with the
internal PD capacitance can occur. Adequate capacitive filtering or a TVS must limit this voltage to be within the
absolute maximum ratings. Outdoor transient levels or special applications require additional protection.
Use of diode DVDD for PoE priority may dictate the use of additional protection around the TPS23757. ESD
events between the PD power inputs (PoE and adapter), or the inputs and converter output, cause large stresses
in the hotswap MOSFET if DVDD becomes reverse biased and transient current around the TPS23757 is blocked.
The use of CVDD and DRTN in Figure 25 provides additional protection should over-stress of the TPS23757 be an
issue. An SMAJ58A would be a good initial selection for DRTN. Individual designs may have to tune the value of
CVDD.
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From Ethernet
Transformers
CVDD
0.01mF
CIN
PPD
DEN
CLS
VDD1
VDD
VSS
RTN
COM
ARTN
RDEN
RCLS
D1 58V
DRTN
58V
From Spare
Pairs or
Transformers
C1 0.1mF
DVDD
Figure 25. Example of Added ESD Protection for PoE Priority
Capacitor, C1
The standard specifies an input bypass capacitor (from VDD to VSS) of 0.05 µF to 0.12 µF. Typically a 0.1 µF, 100
V, 10% ceramic capacitor is used.
Detection Resistor, RDEN
The standard specifies a detection signature resistance, RDEN between 23.75 kΩ and 26.25 kΩ, or 25 kΩ ± 5%.
Choose an RDEN of 24.9 kΩ.
Classification Resistor, RCLS
Connect a resistor from CLS to VSS to program the classification current according to the IEEE 802.3-2008
standard. The class power assigned should correspond to the maximum average power drawn by the PD during
operation. Select RCLS according to Table 1. The TPS23757 should not use class 4 as its input current is limited
to class 3 (and lower) levels. Apart from power above 13W, there is no advantage to type 2 operation.
APD Pin Divider Network, RAPD1, RAPD2
The APD pin can be used to disable the TPS23757 internal hotswap MOSFET giving the adapter source priority
over the PoE source. An example calculation is provided in (TI literature number) SLVA306A.
PPD Pin Divider Network, RPPD1, RPPD2
The PPD pin can be used to override the internal hotswap MOSFET UVLO (UVLO_R and UVLO_H) when using
low voltage adapters connected between VDD and VSS. The PPD pin has an internal 5 µA pulldown current
source. As an example, consider the choice of RPPD1 and RPPD2, for a 24 V adapter.
1. Select the startup voltage, VADPTR-ON approximately 75% of nominal for a 24 V adapter. Assuming that the
adapter output is 24 V ± 10%, this provides 15% margin below the minimum adapter operating voltage.
2. Choose VADPTR-ON = 24 V × 0.75 = 18 V
3. Choose RPPD2 = 3.01 kΩ
4. Calculate RPPD1
RPPD1
æ
çV
ADPTR_ON - VPPDEN
= ç
ç
VPPDEN
- IPPD
ç
RPPD2
è
ö æ
ö
÷ ç
÷
18
V
1.55
V
÷ =ç
÷ = 32.26 k W
÷ ç 1.55 V
- 5 mA ÷÷
÷ ç
ø
ø è 3.01 kW
a.
b. Choose RPPD1 = 32.4 kΩ
5. Check PPD turn on and PPD turn off voltages
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é
æV
öù
VADPTR_ON = VPPDEN + êRPPD1 ´ ç PPDEN - IPPD ÷ ú = 18.07 V
êë
è RPPD2
ø úû
a.
é
æ (VPPDEN - VPPDH )
öù
- IPPD ÷ ú = 14.54 V
VADPTR_OFF = (VPPDEN - VPPDH )+ ê RPPD1 ´ ç
ç
÷ú
RPPD2
êë
è
øû
b.
c. Voltages look acceptable.
6. Check PPD resistor power consumption.
2
PRPPD
(24 V ´ 1.1)
(VDD - VSS )2
=
=
= 19.6 mW
RPPD1 + RPPD2
3.01 kW + 32.4 kW
a.
b. Power is acceptable, but resistor values could be increased to reduce the power loss.
Setting Frequency (RFRS) and Synchronization
The converter switching frequency is set by connecting RFRS from the FRS pin to ARTN. The frequency may be
set as high as 1 MHz with some loss in programming accuracy as well as converter efficiency. Synchronization
at high duty cycles may become more difficult above 500 kHz due to the internal oscillator delays reducing the
available on-time. As an example:
1. Assume a desired switching frequency (fSW) of 250 kHz.
2. Compute RFRS:
17250
17250
RFRS (k W ) =
=
= 69
f
(kHz)
250
SW
a.
b. Select 69.8 kΩ.
VSYNC
TSYNC
RFRS
FRS
47pF
VSYNC
TSYNC
1000pF
RTN
ARTN
COM
47pF
Synchronization
Pulse
RFRS
FRS
RT
Synchronization
Pulse
RTN
ARTN
COM
The TPS23757 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,
or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by
applying a short pulse (TSYNC) of magnitude VSYNC to FRS as shown in Figure 26. RFRS should be chosen so that
the maximum free-running frequency is just below the desired synchronization frequency. The synchronization
pulse terminates the potential on-time period, and the off-time period does not begin until the pulse terminates.
The pulse at the FRS pin should reach between 2.5 V and VB, with a minimum width of 22 ns (above 2.5 V) and
rise/fall times less than 10 ns. The FRS node should be protected from noise because it is high-impedance. An
RT on the order of 100 Ω in the isolated example reduces noise sensitivity and jitter.
1:1
Figure 26. Synchronization
Current Slope Compensation
The TPS23757 provides a fixed internal compensation ramp that suffices for most applications. RS (see
Figure 27) may be used if the internally provided slope compensation is not enough.
Most current-mode control papers and application notes define the slope values in terms of VPP/tS (peak ramp
voltage / switching period), however the electrical characteristics table specifies the slope peak (VSLOPE) based
on the maximum (78%) duty cycle. Assuming that the desired slope, VSLOPE-D (in mV/period), is based on the full
period, compute RS per the following equation where VSLOPE, DMAX, and ISL-EX are from the electrical
characteristics table with voltages in mV, current in µA, and the duty cycle is unitless (e.g., DMAX = 0.78).
26
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é
æ VSLOPE (mV) ö ù
ê VSLOPE_D (mV) - ç
÷ú
DMAX
è
ø ûú
ëê
RS (W) =
´ 1000
ISL_EX (mA)
RTN
COM
ARTN
GATE
CS
RS
CS
RCS
Figure 27. Additional Slope Compensation
CS may be required if the presence of RS causes increased noise, due to adjacent signals like the gate drive, to
appear at the CS pin.
Blanking Period, RBLNK
Selection of the blanking period is often empirical because it is affected by parasitics and thermal effects of every
device between the gate-driver and output capacitors. The minimum blanking period prevents the current limit
and PWM comparators from being falsely triggered by the inherent current spike that occurs when the switching
MOSFET turns on. The maximum blanking period is bounded by the output rectifier's ability to withstand the
currents experienced during a converter output short, and the minimum duty cycle required.
If blanking beyond the internal default is desired choose RBLNK using RBLNK (kΩ) = tBLNK (ns).
1. For a 100 ns blanking interval
a. RBLNK (kΩ) = 100
b. Choose RBLNK = 100 kΩ.
The blanking interval can also be chosen as a percentage of the switching period.
1. Compute RBLNK as follows for 2% blanking interval in a switcher running at 250 kHz.
BIanking_Interval(%)
2
RBLNK (k W ) =
´ 10 4 =
´ 10 4 = 80
f
(kHz)
250
SW
a.
b. Select RBLNK = 80.6 kΩ.
Dead Time Resistor, RDT
The required dead time period depends on the specific topology and parasitics. To obtain the optimum timing
resistor, build the supply and tune the dead time to achieve the best efficiency after considering all corners of
operation (load, input voltage, and temperature). A good initial value is 100 ns. Program the dead time with a
resistor connected from DT to ARTN per Equation 3. Efficiency optimization may be performed by substituting a
potentiometer (POT) for RDT, and adjusting its value to obtain a minimum input current at the desired operating
load.
1. Choose RDT as follows assuming a tDT of 100 ns:
t (ns)
100
RDT (kW) = DT
=
= 50
2
2
a.
b. Choose RDT = 49.9 kΩ
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Estimating Bias Supply Requirements and CVC
The bias supply (VC) power requirements determine the CVC sizing and frequency of hiccup during a fault. The
first step is to determine the power/current requirements of the power supply control, then use this to select CVC.
The control current draw will be assumed constant with voltage to simplify the estimate, resulting in an
approximate value.
First determine the switching MOSFET gate drive power.
1. Let VQG be the gate voltage swing that the MOSFET QG is rated to (often 10 V).
æ
VC
PGATE = VC ´ fSW ´ çç QGATE ´
V
QG
è
ö
æ
VC
÷÷ PGAT2 = VC ´ fSW ´ çç QGATE2 ´
V
QG
ø
è
ö
÷÷
ø
a.
b. Compute gate drive power if VC is 10 V, the switching frequency is 250 kHz, QGATE is 17 nC, and QGAT2
is 8 nC.
10
PGATE = 10 V ´ 250 kHz ´ 17 nC ´
= 42.5 mW
10
10
PGAT2 = 10 V ´ 250 kHz ´ 8 nC ´
= 20 mW
10
c.
PDRIVE = 42.5 mW + 20 mW = 62.5 mW
d. This illustrates why MOSFET QG should be an important consideration in selecting the switching
MOSFETs.
2. Estimate the required bias current at some intermediate voltage during the CVC discharge. For the
TPS23757, 7.5 V provides a reasonable estimate. Add the operating bias current to the gate drive current.
V
P
62.5 mW
7.5 V
IDRIVE = DRIVE x DIS =
x
= 4.7 mA
V
V
10
V
10 V
C
C
a.
b. ITOTAL = IDRIVE + IOPERATING = 4.7 mA + 0.92 mA = 5.6 mA
3. Compute the required CVC based on startup within the typical softstart period of 4 ms.
t
´ ITOTAL
4 ms ´ 5.6 mA
CVC1 + CVC2 = STARTUP
=
= 6.4 mF
V
3.5 V
CUVH
a.
b. For this case, a standard 10 µF electrolytic plus a 0.47 µF should be sufficient. In practice this is
conservative since it was assumed it would take the full 4 ms to start up.
4. Compute the initial time to start the converter when operating from PoE.
a. Using a typical bootstrap current of 4 mA, compute the time to startup.
C
´ VCUV
10.47 mF ´ 9 V
t ST = VC
=
= 23.6 ms
IVC
4 mA
b.
5. Compute the fault duty cycle and hiccup frequency
(CVC1 + CVC2 ) ´ VCUVH
(10 mF + 0.47 mF) ´ 3.5 V
tRECHARGE =
=
= 9.2 ms
I
4 mA
VC
a.
(CVC1 + CVC2 ) ´ VCUVH
(10 mF + 0.47 mF) ´ 3.5 V
tDISCHARGE =
=
= 6.5 ms
I
5.6 mA
TOTAL
b.
a. Note that the optocoupler current is 0 mA because the output is in current limit.
b. Also, it is assumed IAPb is 0 mA.
tDISCHARGE
6.5 ms
Duty Cycle: D =
=
= 41%
tDISCHARGE + tRECHARGE
6.5 ms + 9.2 ms
c.
1
1
Hiccup Frequency: F =
=
= 64 Hz
tDISCHARGE + tRECHARGE
6.5 ms + 9.2 ms
d.
6. The voltage rating of CVC1 and CVC2 should be 16 V minimum.
28
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TPS23757
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Switching Transformer Considerations and RVC
Care in design of the transformer and VC bias circuit is required to obtain hiccup overload protection.
Leading-edge voltage overshoot on the bias winding may cause VC to peak-charge, preventing the expected
tracking with output voltage. Some method of controlling this is usually required. This may be as simple as a
series resistor, or an R-C filter in front of DVC1. Good transformer bias-to-output-winding coupling results in
reduced overshoot and better voltage tracking.
RVC as shown in Figure 28 helps to reduce peak charging from the bias winding. This becomes especially
important when tuning hiccup mode operation during output overload. Typical values for RVC will be between 10
Ω and 100 Ω.
RVC
VC
DVC1
CVC
T1
Bias Winding
ARTN
Figure 28. RVC Usage
APb Pin Interface
The APb pin is an active low, open-drain output indicating an adapter power source is available. An optocoupler
is typically used to interface with the APb pin to signal equipment on the secondary side of the converter of APb
status. Optocoupler current-gain is referred to as CTR (current transfer ratio), which is the ratio of transistor
collector current to LED current. To preserve efficiency, a high-gain optocoupler ( 250% ≤ CTR ≤ 500%, or 300%
≤ CTR ≤ 600% ) along with a high-impedance (e.g., CMOS) receiver are recommended. Design of the APb
optocoupler interface can be accomplished as follows:
VOUT
VC
RAPb
RAPb_OUT
Adapter Present
Indicator
Low = Present
APb From
TPS23757
Figure 29. APb Interface
1. APb ON characteristic: IAPb = 2 mA minimum, VAPb = 1 V
2. Let VC = 12 V, VOUT = 5 V, RAPb-OUT = 10 kΩ, VAPb-OUT (low) = 400 mV max
V
- VAPb (low)
5 - 0.4
IAPb = OUT
=
= 0.46 mA
R
10000
APb
a.
3. The optocoupler CTR will be needed to determine RAPb. A device with a minimum CTR of 300% at 5 mA
LED bias current is selected. CTR will also vary with temperature and LED bias current. The strong variation
of CTR with diode current makes this a problem that requires some iteration using the CTR versus IDIODE
curve on the optocoupler data sheet.
a. Using the (normalized) curves, a current of 0.4 mA to 0.5 mA is required to support the output current at
the minimum CTR at 25°C.
a. Pick an IDIODE. For example one around the desired load current.
b. Use the optocoupler datasheet curve to determine the effective CTR at this operating current. It is
usually necessary to apply the normalized curve value to the minimum specified CTR. It might be
necessary to ratio or offset the curve readings to obtain a value that is relative to the current that the
CTR is specified at.
c. If IDIODE × CTRI_DIODE is substantially different from IRAPb_OUT, choose another IDIODE and repeat.
b. This manufacturer’s curves also indicate a –20% variation of CTR with temperature. The approximate
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29
TPS23757
SLVS948 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com
forward voltage of the optocoupler diode is 1.1 V from the data sheet.
100
100
IAPb @ IMIN ´
= 0.5 mA ´
= 0.625 mA
100 - DCTRTEMP
100 - 20
c. VFLED ≈ 1.1 V
V - VAPb - VFLED
12 - 1 - 1.1
R APb = C
=
= 15.48 kW
IAPb
0.625 mA
d. Select a 15.4 kΩ resistor. Even though the minimum CTR and temperature variation were considered,
the designer might choose a smaller resistor for a little more margin.
Advanced ORing Techniques
See Advanced Adapter ORing Solutions using the TSP23753, TI literature number SLVA306A for ORing
applications that also work with the TPS23757. The material in sections Adapter ORing and Protection, D1 are
important to consider as well. The following applications are supported with the introduction of PPD.
CVDD
10nF
VDD1
VDD
PPD
DEN
CLS
DA
30V
26.7kW
APD
3.01kW
VSS
RAPD2 RAPD1 DAPD
CIN
RTN
COM
ARTN
RDEN
3.3MW
RCLS
RVDD1
1.8KW
RHLD
RAPD2
DRTN
APD
RAPD1
58V
VSS
24V
VDD1
VDD
CIN
DA
Adapter
For 48V
Adapter
DHLD
RCLS
PPD
DEN
CLS
DVDD
RTN
COM
ARTN
RDEN
1.8kW
24V
D1 58V
DVDD
C1 0.1uF
From Spare
Pairs or
Transformers
From Ethernet
Transformers
Option 2 ORing with PoE acting as a hot backup is eased by connecting PPD to VDD per Figure 30. This PPD
connection enables the class regulator even when APD is high. The R-Zener network (1.8 kΩ – 24 V) is the
simplest circuit that will satisfy MPS requirements, keeping the PSE online. This network may be switched out
when APD is not powered with an optocoupler. This works best with a 48-V adapter and the APD-programmed
threshold as high as possible. An example of an adapter priority application with smooth switchover between a
48 V adapter and PoE is shown on the right side of Figure 30. DAPD is used to reduce the effective APD
hysteresis, allowing the PSE to power the load before VVDD1 - VRTN falls too low and causes a hotswap foldback.
Adapter
Figure 30. Option 2 PoE Backup ORing
Option 1 ORing of a low voltage adapter (e.g., 24 V) is possible by connecting a resistor divider to PPD as in
Figure 31. When 1.55 V ≤ VPPD ≤ 8.3 V, the hotswap MOSFET is enabled, APb is activated, and the class
feature is disabled. The hotswap current limit is unaffected, limiting the available power. For example, the
maximum input power from a 24 V adapter would be 9.3 W [(24 V – 0.6 V) × 0.4 A].
30
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TPS23757
VDD
VDD1
DEN
PPD
CLS
RCLS
D1 58V
From Spare
Pairs or
Transformers
C1 0.1uF
RDEN
From Ethernet
Transformers
www.ti.com ....................................................................................................................................................................................................... SLVS948 – JULY 2009
DA
RPPD1
Adapter
RPPD2
APD
RTN
COM
ARTN
VSS
Figure 31. Low-Voltage Option 1 ORing
Softstart
Converters require a softstart on the voltage error amplifier to prevent output overshoot on startup. Figure 32
shows a common implementation of a secondary-side softstart that works with the typical TLV431 error amplifier.
The softstart components consist of DSS, RSS, and CSS. They serve to control the output rate-of-rise by pulling
VCTL down as CSS charges through ROB, the optocoupler, and DSS. This has the added advantage that the
TLV431 output and CIZ are preset to the proper value as the output voltage reaches the regulated value,
preventing voltage overshoot due to the error amplifier recovery. The secondary-side error amplifier will not
become active until there is sufficient voltage on the secondary. The TPS23757 provides a primary-side softstart
which persists long enough (~4 ms) for secondary side voltage-loop softstart to take over. The primary-side
current-loop softstart controls the switching MOSFET peak current by applying a slowly rising ramp voltage to a
second PWM control input. The PWM is controlled by the lower of the softstart ramp or the CTL-derived current
demand. The actual output voltage rise time is usually much shorter than the internal softstart period. Initially the
internal softstart ramp limits the maximum current demand as a function of time. Either the current limit,
secondary-side softstart, or output regulation assume control of the PWM before the internal softstart period is
over. Figure 21 shows a smooth handoff between the primary and secondary-side softstart with minimal output
voltage overshoot.
From Regulated
Output Voltage
ROB
RSS
CIZ
DSS
CSS
RFBU
RFBL
TLV431
Figure 32. Error Amplifier Soft Start
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31
TPS23757
SLVS948 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com
Special Switching MOSFET Considerations
Special care must be used in selecting the converter switching MOSFET. The TPS23757 minimum switching
MOSFET VGATE is ~5.5 V, which is due to the VC lower threshold. This will occur during an output overload, or
towards the end of a (failed) bootstrap startup. The MOSFET must be able to carry the anticipated peak fault
current at this gate voltage.
Thermal Considerations and OTSD
Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations
assume that the TPS23757 is the only heat source contributing to the PCB temperature rise. It is possible for a
normally operating TPS23757 device to experience an OTSD event if it is excessively heated by a nearby
device.
Frequency Dithering for Conducted Emissions Control
The international standard CISPR 22 (and adopted versions) is often used as a requirement for conducted
emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions.
Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit
board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques. A
more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant PoE
Powered Device With Isolated Flyback, TI literature number SLUA469. Additionally, IEEE802.3-2008 sections
33.3 and 33.4 have requirements for noise injected onto the Ethernet cable based on compatibility with data
transmission.
Occasionally, a technique referred to as frequency dithering is utilized to provide additional EMI measurement
reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider
bandwidth, thus lowering peak measurements. The circuit of Figure 33 modulates the switching frequency by
feeding a small ac signal into the FRS pin. These values may be adapted to suit individual needs.
10kW
49.9kW
VB
+
-
6.04kW
TL331IDBV
4.99kW
0.01mF
10kW
301kW
1m F
To
FRS
ARTN
Figure 33. Frequency Dithering
ESD
The TPS23757 has been tested to EN61000-4-2 using a power supply based on Figure 1. The levels used were
8 kV contact discharge and 15 kV air discharge. Surges were applied between the PoE input and the dc output,
between the adapter input and the dc output, between the adapter and the PoE inputs, and to the dc output with
respect to earth. Tests were done both powered and unpowered. No TPS23757 failures were observed and
operation was continuous. See Figure 25 for additional protection for some test configurations.
ESD requirements for a unit that incorporates the TPS23757 have a much broader scope and operational
implications than are used in TI’s testing. Unit-level requirements should not be confused with reference design
testing that only validates the ruggedness of the TPS23757.
Layout
Printed circuit board layout recommendations are provided in the evaluation module (EVM) documentation
available for these devices.
32
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS23757PW
PREVIEW
TSSOP
PW
20
70
TBD
Call TI
Call TI
TPS23757PWR
PREVIEW
TSSOP
PW
20
2000
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Aug-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS23757PWR
Package Package Pins
Type Drawing
TSSOP
PW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Aug-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS23757PWR
TSSOP
PW
20
2000
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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