UCD74106 SLUSAJ5 – MAY 2011 www.ti.com Synchronous-Buck Power Stage Check for Samples: UCD74106 FEATURES 1 • • • • • • • • • DESCRIPTION Fully Integrated Power Switches With Drivers for Single and Multiphase Synchronous Buck Converters Full Compatibility With TI Fusion Digital Power Supply Controllers, (UCD91xx and UCD92xx Families) Compatible With Analog Domain Controllers Wide Input Voltage Range: – 4.5 V to 14 V – Operational Down to 2.2-V Input With an External Bias Supply Up to 6-A Output Current Operational to 2-MHz Switching Frequency Current Limit With Current Limit Flag Onboard Regulated 6-V Driver Supply From VIN Thermal Protection and Monitoring The UCD74106 is a complete power system ready to drive a buck power supply (Figure 1). High-side MOSFETs, low-side MOSFETs, drivers, current sensing circuitry and necessary protection functions are all integrated into one monolithic solution to facilitate minimum size and maximum efficiency. Driver circuits provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous rectifier in a synchronous buck circuit. The MOSFET gates are driven to 6.25 V by an internally regulated VGG supply. The internal VGG regulator can be disabled to permit the user to supply an independent gate drive voltage. This flexibility allows a wide power conversion input voltage range of 2.2 V to 18 V. Internal Under Voltage Lockout (UVLO) logic insures VGG is good before allowing chip operation. A drive logic block allows operation in one of two modes. In synchronous mode, the logic block uses the PWM signal to control both the high-side and low-side gate drive signals. Dead time is optimized to prevent cross conduction. The synchronous rectifier enable (SRE) pin controls whether or not the low-side FET is turned on when the PWM signal is low. APPLICATIONS • • • Digitally-Controlled Synchronous-Buck Power Stage for Single and Multi-Phase Applications High Efficiency Small Size Regulators for Desktop, Server, Telecom and Notebook Applications Synchronous-Buck Power Stages Simplified Application Diagram UCD74106 VIN 13 4 PWM 3 SRE C1 TMON 10 2 FLT 12 FLTRST BST 1 SW 6 PGND 7 R2 C3 11 IMON R1 L1 C3 5 C2 VGG BP3 AGND 9 8 C4 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated UCD74106 SLUSAJ5 – MAY 2011 www.ti.com DESCRIPTION (CONT.) On-board current sense amplifiers monitor the current to safeguard the power stage from sudden high current loads. In the event of an over-current fault, the output power stage is turned off and the Fault Flag (FLT) is asserted to alert the controller. Output current is measured and monitored by a precision integrated current sense element. This method provides an accuracy of ±5%. The amplified signal is available for use by the controller on the IMON pin. The IMON pin has a positive offset so that both positive (sourcing) and negative (sinking) current can be sensed. If the die temperature exceeds 150°C, the temperature sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag. Normal operation resumes when the die temperature falls below the thermal hysteresis band and the Fault Flag is re-set by the controller. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. ORDERING INFORMATION OPERATING TEMPERATURE RANGE, TA PIN COUNT –40°C to 125°C 13-pin ORDERABLE PART NUMBER SUPPLY UCD74106RGMR Reel of 2500 UCD74106RGMT Reel of 250 PACKAGE TOP SIDE MARKING QFN UCD74106 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Supply voltage Boot voltage DC Gate supply voltage MIN MAX -0.3 20 -0.3 SW + 7 -0.3 7 -2 VIN + 1 Analog outputs -0.3 3.6 Digital I/O’s -0.3 5.5 Junction temperature -55 150 Storage temperature -65 150 Switch voltage DC ESD rating, Human Body Model (HBM) 2000 ESD rating, Charged Device Model (CDM) Lead temperature (1) 2 500 Reflow soldering, 10 sec 300 UNIT V V °C V °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult company packaging information for thermal limitations and considerations of packages. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com THERMAL INFORMATION UCD74106 THERMAL METRIC (1) RGM UNITS 13 PINS Junction-to-ambient thermal resistance (2) θJA 70.2 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 11.0 ψJT Junction-to-top characterization parameter (5) 0.9 ψJB Junction-to-board characterization parameter (6) 11.0 θJCbot Junction-to-case (bottom) thermal resistance (7) 0.9 (1) (2) (3) (4) (5) (6) (7) 47.3 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX VIN Power input voltage Internally generated VGG 4.5 12 16 VIN Power input voltage Externally supplied VGG 2.2 12 16 VG Externally supplied gate drive voltage 4.5 6.2 UNIT V G TJ Operating junction temperature range -40 125 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 ◦C 3 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS VIN = 12 V; 1 μF from BP3 to GND, 0.22 μF from BST to SW, 4.7 µF from VGG to PGND, TA = TJ = -40°C to 125°C (unless otherwise noted). PARAMETER TEST CONDITION MIN TYP MAX UNITS Supply Supply current Outputs not switching, VIN = 2.2 V, VGG = 5 V 4 Supply current Outputs not switching, VIN = 12 V, 4 mA Gate Drive Under Voltage Lockout VGG UVLO ON BP3 rising 4.0 VGG UVLO OFF BP3 falling 3.8 VGG UVLO hysteresis V 200 mV VGG Supply Generator VGG VIN = 7 to 14 V VGG drop out VIN = 4.5 to 7 V, IVGG < 20 mA 5.2 6.25 6.8 V 200 mV 3.45 V BP3 Supply Voltage BP3 IDD = 0 to 10 mA 3.15 3.3 Input Signal (PWM, SRE) VIH Positive-going input threshold voltage VIL Negative-going input threshold voltage 2.3 Tristate condition tHLD_R 1.4 3-state hold-off time VPWM = 1.65V IPWM input current VPWM = 5.0V VPWM = 3.3V VPWM = 0V ISRE input current 4 V 1 1.9 200 165 -165 VSRE = 5.0V 1 VSRE = 3.3V 1 VSRE = 0V 1 Submit Documentation Feedback ns 250 μA Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 12 V; 1 μF from BP3 to GND, 0.22 μF from BST to SW, 4.7 µF from VGG to PGND, TA = TJ = -40°C to 125°C (unless otherwise noted). PARAMETER TEST CONDITION MIN TYP MAX UNITS FAULT Flag (FLT) FLT Output high level IOH = 4 mA Output low level IOL = -4 mA 2.7 V 0.6 Current Limit Over current threshold PWM frequency = 1 MHz, VIN = 12 V, VOUT = 1.2 V 6.7 7.5 8.2 4.106 4.322 4.538 A Current Sense Amplifier Gain (1) IMON/ISW, 0.3 ≤ V(IMON) ≤ 1.3 V Zero amp load offset 0 ≤ V(IMON) ≤ 3.1 V, RIMON = 22.6 kΩ μA/A μA 22.1 Thermal Sense Thermal shutdown (1) Thermal shutdown hysteresis 155 (1) °C 30 Temperature sense T (1) Gain Temperature sense T offset TJ = 25 °C, -100 μA ≤ ITMON ≤ 100 µA 10 mV/°C 750 mV POWER Drive Train Propagation delay from PWM to switch node going high (1) 20 High-side MOSFET turn on – dead Time (1) 3 5 15 Low-side MOSFET turn on – dead time (1) 3 7 15 Min PWM pulse width (1) (1) (2) ns 20 (2) As designed and characterized, not fully tested in production. There is no inherent limit on the minimum pulse width. Depending on the board layout, partial enhancement of the high-side FET may be observed for shorter pulse widths. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 5 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com DEVICE INFORMATION RGM Package (Top View) BST 1 FLT 2 SRE 3 PWM 4 VGG 5 13 VIN 12 FLTRST 11 IMON SW 6 7 PGND 10 TMON 9 Bp3 8 AGND BLOCK DIAGRAM PWM UCD74106 TMON Thermal Sense 4 12 FLTRST 12 SRE R2 FLT 3 Drive Logic 2 VIN VIN 13 C1 IMON Currennt Sense Processor VGG Generator 11 R1 BST 1 VIN C3 Driver VGG SW 5 C2 6 L1 VOUT C4 3.3-V Generator Driver PGND BP3 9 AGND 7 8 C4 Figure 1. Typical Block Diagram 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com TERMINAL FUNCTIONS TERMINAL I/O FUNCTION NAME NO. PWM 4 I 20-kΩ input capable of accepting 3.3-V or 5-V logic level signals up to 2 MHz. A Schmitt trigger input comparator desensitizes this pin from external noise. This pin controls the state of the high-side MOSFET and the low-side MOSFET when SRE is high. When PWM is in HiZ state the output power stage is turned off within 200 ns. SRE 3 I Synchronous rectifier enable input. High impedance digital input capable of accepting 3.3-V or 5-V logic level signals used to control the synchronous rectifier switch. An appropriate anti-cross-conduction delay is used during synchronous mode. BST 1 I Charge pump capacitor connection. It provides a floating supply for the high-side driver. Connect a 0.22-µF ceramic capacitor from this pin to SW. VGG 5 I/O Gate drive voltage for the power MOSFETs. For VIN > 4.5 V, the internal VGG generator can be used. For VIN < 4.5 V, this pin should be driven from an external bias supply. In all cases, bypass this pin with a 4.7-µF (min), 10-V (min) ceramic capacitor to PGND. BP3 9 O Output of internal 3.3-V LDO regulator for powering internal logic circuits. Bypass this pin with 1 µF (min) to GND. This LDO is supplied by the VGG pin. O Current sense monitor output. Provides a current source output that is proportional to the current flowing in the low-side MOSFET. The gain on this pin is equal to 4.4 µA/A. The IMON pin should be connected to a 22.6-kΩ resistor to GND to produce a voltage proportional to the power-stage load current. The IMON pin sources 22.1 µA at no load. This provides a pedestal that permits the reporting of negative (sinking) current. O Temperature sense pin. The voltage on this pin is proportional to the die temperature. The gain is 12 mV/°C. At TJ = 25°C, the output voltage has an offset of 0.75 V. When the die temperature reaches the thermal shutdown threshold, this pin is pulled to BP3 and power FETs are switched off. Normal operation resumes when the die temperature falls below the thermal hysteresis band. IMON TMON 11 10 FLT 2 O Fault flag. This signal is a 3.3-V digital output which is latched high when the load current exceeds the current limit trip point. When tripped both high side and low side are latched off. See FLT clear protocol as defined by FLTRST. Additionally, if the die temperature exceeds 150°C, VIN and/or VGG is outside of UVLO limits, the output switching will be halted and FLT flag is set. Normal operation resumes after fault clear sequence is complete. FLTRST 12 I Fault reset mode. PGND 7 - Shared power ground return for the buck power stage SW 6 - Switching node of the buck power stage and square wave input to the buck inductor. Electrically this is the connection of the high-side MOSFET source to the low-side MOSFET drain. VIN 13 - Input voltage to the buck power stage and driver circuit Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 7 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com TYPICAL CHARACTERISTICS Typical Efficiency DRIVER EFFICIENCY vs LOAD CURRENT DRIVER DISSIPATION vs LOAD CURRENT 100 1.8 90 1.6 80 1.4 Driver Dissipation (W) 70 Driver Efficiency (%) 12 VIN ->3.3 VOUT at 1 MHz 12 VIN ->2.5 VOUT at 1 MHz 8 VIN ->1.2 VOUT at 1 MHz 12 VIN ->1.2 VOUT at 1 MHz 12 VIN ->800 mVOUT at 1 MHz 60 50 40 30 12 VIN ->3.3 VOUT at 1 MHz 12 VIN ->2.5 VOUT at 1 MHz 8 VIN ->1.2 VOUT at 1 MHz 12 VIN ->1.2 VOUT at 1 MHz 12 VIN ->800 mVOUT at 1 MHz 20 10 0 0 1 3 2 4 5 1.2 1.0 0.8 0.6 0.4 0.2 0 6 0 1 2 Load Current (A) 3 4 5 6 Load Current (A) Figure 2. Figure 3. PWM and SRE Behavior The PWM and SRE (Synchronous Rectifier Enable) pins control the high-side and low-side drivers, as described in Table 2. Table 2. PWM and SRE Behavior 8 PWM = High PWM = Low PWM = HiZ SRE = High HS = ON, LS = OFF HS = OFF, LS = ON HS = OFF, LS = OFF SRE = Low HS = ON, LS = OFF HS = OFF, LS = ON HS = OFF, LS = OFF Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com Fault Modes Fault Reset Mode The Fault Reset Mode can be programmed with the FLTRST pin, as described in Table 3 Table 3. Mode FLTRST FLT Clear 1 GND PWM = HiZ 2 BP3 PWM = 0, SRE = 0 3 Open PWM = 1 pulse MODE 1 UCD74106 ILOAD SW FLT UCD92k PWM INT UCD74106 Tri Stated UCD PWM EN UCD PWM EN UDG-11067 PWM DIS HiZ UCD74106 INT FLT UCD9X 2 Figure 4. Fault Handshake Protocol, (PWM HiZ) NOTE Handshake Sequence: 1. UCD74106 detects fault condition – FLT flag is set 2. FLT flag generates UCD interrupt 3. UCD releases PWM -HiZ state 4. UCD74106 detects (HiZ) as FLT clear; if fault condition is no longer present then flag is cleared 5. If FLT clears UCD responds to the Start command, Else PWM stays in HiZ state Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 9 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com MODE 2 SRE PWM INT_UCD FLT UCD PWM Enabled PWM DIS UCD74106 Tri Stated PWM EN Figure 5. Fault Handshake Protocol, (PWM SRE) NOTE Handshake Sequence: 1. UCD74106 detects fault condition – FLT is set 2. FLT flag generates interup 3. UCD sets SRE Lo AND stops PWM 4. UCD74106 reads (SRE and PWM)= Lo as FLT clear; if fault condition is no longer present then flag is cleared. 5. If FLT clears UCD responds to the Start command, Else (PWM and SRE) = Lo 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com MODE 3 PWM FLT FLT_FLAG UCD PWM Enabled UCD74106 Tri Stated UDG-11083 Area of Uncertainty Figure 6. Fault Handshake Protocol, (PWM pulses) NOTE No Handshake Re-Set: 1. UCD74106 detects fault condition – FL_FLAG is set 2. No action on UCD side. 3. UCD74106 reads one complete PWM pulse without FLT being present and re-sets FLT_FLAG signal on the falling edge of PWM. 4. Within the area of uncertainty: FLT rising edge to FLT_FLAG rising edge delay is zero (gate delay only). 5. PWM falling edge to FLT_FLAG falling edge delay is zero (gate delay only). Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 11 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com The high-side current limit fault behavior shown in Figure 7. PWM ILIMIT IL HS LS FLT UDG-11069 Figure 7. In general, FLT is always cleared by the first complete PWM pulse (a rising and a falling edge) without a fault present. This is true for all faults including UV and OT. The only exception to this occurs during start up where FLT will self clear once UVLO is disabled, as shown in Figure 8. However, if a subsequent under voltage condition occurs the fault must be cleared by one complete PWM pulse without a fault, as shown in Figure 7. PWM SRE HS LS UVL O FLT UDG-11070 ? t4 Figure 8. 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com IMON Behavior The plot in Figure 9 shows how the voltage on the IMON pin will behave with a 22.6-kΩ resistor. The solid dark line represents the typical behavior and the shaded region represents the tolerance band due too gain. VIMON vs LOAD CURRENT VIMON (V) 1.0 0.5 0 -2 0 2 4 6 Load Current (A) Figure 9. MTTF vs DUTY CYCLE 100000 100 110 10000 120 130 140 MTTF (years) 1000 150 100 10 1 0 1 10 100 Duty Cycle (%) Figure 10. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 13 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com TMON Behavior The voltage on this pin is proportional to the die temperature: TMON = TOFFSET + TGAIN ´ TJ (1) Table 4. Temperature Sense Definitions TMON Voltage from TMON pin to GND TOFFSET Thermal sense T offset TGAIN Thermal sense T gain TJ Device internal junction temperature TMON vs JUNCTION TEMPERATURE 2 1.8 1.6 TMON Voltage (V) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 100 120 Junction Temperature (°C) Figure 11. If the junction temperature exceeds approximately 155°C, the device will enter thermal shutdown. This will assert the FLT pin, both MOSFETs will be turned off and the switch node will become high impedance. When the junction temperature cools by approximately 30°C, the device will exit thermal shutdown and resume switching as directed by the PWM and SRE pins. 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com APPLICATION INFORMATION Operating Frequency Switching frequency is a key place to start the design of any DC/DC converter. This will set performance limits on things such as: maximum efficiency, minimum size, and achievable closed loop bandwidth. A higher switching frequency is, generally, going to yield a smaller design at the expense of a lower efficiency. The size benefit is principally a result of the smaller inductor and capacitor energy storage elements needed to maintain ripple and transient response requirements. The additional losses result from a variety of factors, however, one of the largest contributors is the loss incurred by switching the MOSFETs on and off. The integrated nature of the UCD74106 makes these losses drastically smaller and subsequently enables excellent efficiency from a few hundred kHz up to the low MHz. For a reasonable trade off of size versus efficiency, 750 kHz is a good place to start. VGG If 4.5 V < VIN ≤ 6 V a simple efficiency enhancement can be achieved by connecting VGG directly to VIN. This allows the solution to bypass the drop-out voltage of the internal VGG linear regulator, subsequently improving the enhancement of the MOSFETs. When doing this it is critical to make sure that VGG never exceeds the absolute maximum rating of 7 V. Inductor selection There are three main considerations in the selection of an inductor once the switching frequency has been determined. Any real world design is an iterative trade off of each of these factors. 1. The electrical value which in turn is driven by: (a) RMS current (b) The maximum desired output ripple voltage (c) The desired transient response of the converter 2. Losses (a) Copper (PCu) (b) Core (Pfe) 3. Saturation characteristics of the core Inductance Value The principle equation used to determine the inductance is: di (t) vL (t) = L L dt (2) During the on time of the converter the inductance can be solved to be: V - VOUT D L = IN fS DI (3) Table 5. Definitions VIN VOUT Input voltage Output voltage fS Switching frequency D Duty cycle (VOUT/VIN for a buck converter) ΔI The target peak-to-peak inductor current Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 15 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com In general, it is desirable to make ΔI large to improve transient response and small to reduce output ripple voltage and RMS current. A number of considerations go into this however, ΔI = 0.4 IOUT results in a small ILRMS without an unnecessary penalty on transient response. It also creates a reasonable ripple current that most practical capacitor banks can handle. Here IOUT is defined as the maximum expected steady state current. Plugging these assumptions into the above inductance equation results in: V - VOUT D L = 5 IN 2 ´ IOUT fS (4) For example, plotting this result as a function of VIN and VOUT results in: • • • • • • IOUT = 6.0 A ƒS = 1.0 MHz NCRIT = 5 ΔI/IOUT = 40% ΔI = 2.4 A VOUT (V) Figure 12. VIN and VOUT NOTE The maximum inductance occurs at the maximum VIN and VOUT shown in Figure 12. In general, this inductance value should be used in order to keep the inductor ripple current from becoming too large over the range of supported VIN and VOUT. 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com Inductor Losses and Saturation The current rating of an inductor is based on two things, the current necessary to raise the component temperature by 40°C and the current level necessary to reduce the inductance to 80% of its initial value (saturation current ). The current rating is the lower of these two numbers. Both of these factors are influenced by the choice of core material. Popular materials currently in use are: ferrite, powdered alloy and powdered iron. Ferrite is regarded as the highest performance material and as such is the lowest loss and the highest cost. Solid ferrite all by itself will saturate with a relatively small amount of current. This can be addressed by inserting a gap into the core. This, in effect, makes the inductor behave in a linear manner over a wide DC current range. However, once the inductance begins to roll off, these gapped materials exhibit a “sharp” saturation characteristic. In other words the inductance value reduces rapidly with increases in current above the saturation level. This can be dangerous if not carefully considered, in that the current can rise to dangerous levels. Powdered iron has the advantage of lower cost and a soft saturation characteristic; however, its losses can be very large as switching frequencies increase. This can make it undesirable for a UCD74106 based application where higher switching frequency may be desired. It’s also worth noting that many powdered iron cores exhibit an aging characteristic where the core losses increase over time. This is a wear out mechanism that needs to be considered when using these materials. The powdered alloy cores bring the soft saturation characteristics of powered iron with considerable improvements in loss without the wear-out mechanism observed in powered iron. These benefits come at a cost premium. In general the following relative figure of merits can be made: Table 6. Core Material Choices FERRITE POWDERED ALLOY POWDERED IRON COST High Medium Low LOSS Low Medium High SATURATION Rapid Soft Soft When selecting an inductor with an appropriate core it’s important to have in mind the following: • ILRMS, maximum RMS current • ΔI, maximum peak-to-peak current • IMAX, maximum peak current The RMS current can be determined by the following equation: ILRMS = IOUT 2 + DI2 12 (5) When the 40% ripple constraint is used at maximum load current, this equation simplifies to: ILRMS ≈ IOUT. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 17 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com It is widely recognized that the Steinmetz equation (Pfe) is a good representation of core losses for sinusoidal stimulation. It is important to recognize that this approximation applies to sinusoidal excitation only. This is a reasonable assumption when working with converters whose duty cycles are near 50%, however, when the duty cycle becomes narrow this estimate may no longer be valid and considerably more loss may result. Pfe = k ´ f a ´ B ACb (6) The principle drivers in this equation are the material and its respective geometry (k, α, β), the peak AC flux density (BAC) and the excitation frequency (f). The frequency is simply the switching frequency of the converter while the constant k, can be computed based on the effective core volume (Ve) and a specific material constant (kfe). k = k fe ´ Ve (7) The AC flux density (BAC) is related to the conventional inductance specifications by the following relationship: L DI B AC = Ae ´ N 2 (8) Where L is the inductance, Ae, is the effective cross sectional area that the flux takes through the core and N is the number of turns. Some inductor manufactures use the inductor ΔI as a figure of merit for this loss, since all of the other terms are a constant for a given component. They may provide a plot of core loss versus ΔI for various frequencies where ΔI can be calculated as: V - VOUT D DI = IN L fS (9) IMAX has a direct impact on the saturation level. A good rule of thumb is to add 15% of head room to the maximum steady state peak value to provide some room for transients. DI ö æ IMAX = 1.15 ´ ç IOUT + ÷ 2ø è (10) For example for a 6-A design has the following: Table 7. 6-A Design: Inductor Current Requirements IOUT 6A ILRMS 6A ΔI 2.4 A IMAX 9.6 A Armed with this data one can now approach the inductor datasheet to select a part with a saturation limit above 9 A and current heating limit above 6 A. Furthermore total losses can be estimated based on the datasheet DCR value (ILRMS2 x DCR) and the core loss curves for a given frequency and ΔI. 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com Input Capacitance Due to the non-zero impedance of the power planes of the input voltage rail, it is necessary to add some local capacitance near the UCD74106 to ensure that the voltage at this node is quiet and stable. The primary things to consider are: • The radiated fields generated by the di/dt and dv/dt from this node • RMS currents capability needed in the capacitors • The AC voltage present and respective susceptibility of any device connected to this node ICINRMS = IOUT 2 ´ D ´ (1 - D) + DI2 ´D 12 (11) As a point of reference if ΔI = 0.4 IOUT this places the worst case ICINRMS at approximately 3 A. This corresponds to a duty cycle of approximately 50%. Other duty cycles can result in a significantly lower RMS current. A good input capacitor would be a 22-µF X5R ceramic capacitor. Equally important as selecting the proper capacitor is placing and routing that capacitor. It is crucial that the decoupling be placed as close as possible to both the power pin (VIN) and ground (PGND). It is important to recognize that each power stage should have its own local decoupling. One 22-µF capacitor should be placed across each VIN and PGND pair. The proximity of the capacitance to these pins will reduce the radiated fields mentioned above. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 19 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com Output Capacitance The goal of the output capacitor bank is to keep the output voltage within regulation limits during steady state and transient conditions. The total AC RMS current flowing through the capacitor bank can be calculated as: DI ICOUTRMS = 12 (12) For a single type of output capacitor the output ripple voltage wave form can be approximated by the following equation: 1 t VOUT (t) = IC (t) ´ esr + IC ( t) ´ dt C 0 (13) ò Where: DI ´ fs ì D DI t< ´tï D 2 fs ï IC (t) = í ï DI ´ fS ´ æ t - D ö + DI otherwise ÷ ï 1- D ç fS ø 2 è î (14) After substitution and simplification yields: ì æ DI ´ fS DI ö 1 æ t ´ DI ´ (fS ´ t - D ) DI ´ (1 - 2 ´ D ) ö D ï ´t - ÷ + ´ç esr ´ ç t< ÷ ç ÷ ´ ´ D 2 C 2 D 12 f f ïï è ø S S è ø VOUT (t) = í æ DI ´ fS æ ï D ö DI ö 1 æ DI ´ (fS ´ t - 1)´ (D - fS ´ t ) DI ´ (1 - 2 ´ D ) ö ÷ otherwise ïesr ´ çç 1 - D ´ ç t - f ÷ + 2 ÷÷ + C ´ çç ÷ 2 ´ (1 - D )´ fS 12 ´ fS S ø è ïî è ø è ø (15) The term in this equation multiplied by the esr gives the ripple voltage component due to esr and the term multiplied by 1/C gives the ripple voltage component due to the change in charge on the capacitor plates. In the case were the esr component dominates the peak-to-peak output voltage can be approximated as: VPPesr » DI ´ esr (16) When the charge term dominates the peak-to-peak voltage ripple becomes: DI VPPQ » 8 ´ C ´ fS (17) It’s tempting to simply add these two results together for the case where the voltage ripple is significantly influenced by both the capacitance and the esr. However, this will yield an overly pessimistic result, in that it does not account for the phase difference between these terms. Using the ripple voltage equations and the RMS current equation should give a design that safely meets the steady state output requirements. However, additional capacitance is often needed to meet transient requirements and the specific local decoupling requirements of any device that is being powered off of this voltage. This is not just a function of the capacitor bank but also the dynamics of the control loop. See the UCD9240 Compensation Cookbook for additional details (TI Literature Number SLUA497). 20 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 UCD74106 SLUSAJ5 – MAY 2011 www.ti.com Decoupling It is necessary that VGG and BP3 have their own local capacitance as physically close as possible to these pins. The VGG capacitor should be connected as close as possible to the VGG pin and PGND with a 4.7-µF ceramic capacitor. The BP3 capacitor should be connected as close as possible to BP3 pin and AGND with a 1-µF ceramic capacitor. The UCD74106 also supports the ability to operate from input voltages down to 2.2 V. In these cases an additional supply rail must be connected to VGG and VGG_DIS must be shorted to VGG. Potential external bias supply generators for low VIN operation: TPS63000, TPS61220. Current Sense An appropriate resistor must be connected to the current sense output pins to convert the IMON current to a voltage. In the case of the UCD92xx digital controllers, these parts have a full scale current monitor range of 0 V to 2 V. This range can be maximized to make full use of the current monitoring resolution inside the controller. VMON(min) VMON(max) £ RMON £ IOFFSET + IMIN ´ IGAIN IOFFSET + IMAX ´ IGAIN (18) Table 8. Current Sense Definitions RMON Resistor from IMON pin to GND VMON(min) Minimum voltage for IMON (typically, 0.2 V) VMON(max) Maximum voltage for IMON (typically, 1.8 V) IMIN Minimum load current to sense IMAX Maximum load current to sense IOFFSET IGAIN Current sense amplifier zero amp load offset Current sense amplifier gain The recommended 22.6-kΩ resistor can be used to keep IMON within range for sensing load currents below -2 A to above 6 A. In some applications it may be necessary to filter the IMON signal. The UCD74106 IMON pin is a current source output, so a capacitor to ground in parallel with the current-to-voltage conversion resistor is all that is required. As a rule of thumb, placing the corner frequency of the filter at 20% of the switching frequency should be sufficient. For example, if the switching frequency is 500 kHz or higher, the ripple frequency will be easily rejected with a corner frequency of approximately 100 kHz. With a 100-kHz pole point, the filter time constant is 1.6 µs. A fast current transient should be detected within 4.8 µs. 1 CMON = 2 ´ p ´ RMON ´ 20% ´ fS (19) Layout Recommendations The primary thermal cooling path is from the VIN, GND, and the SW stripes on the bottom of the package. Wide copper traces should connect to these nodes. 1-ounce copper should be the minimum thickness of the top layer; however, 2 ounce is better. Multiple thermal vias should be placed near the GND stripes which connect to a PCB ground plane. There is room to place multiple 10 mil (0.25 mm) diameter vias next to the VIN and GND stripes under the package. For input bypassing, the 22-µF input ceramic caps should be connected as close as possible to the VIN and GND stripes. If possible, the input caps should be placed directly under the UCD74106 using multiple 10-mil vias to bring the VIN and GND connections to the back side of the board. Minimizing trace inductance in the bypass path is extremely important to reduce the amplitude of ringing on the switching node. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UCD74106 21 PACKAGE OPTION ADDENDUM www.ti.com 14-May-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp UCD74106RGMR ACTIVE VQFN RGM 13 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCD74106RGMT ACTIVE VQFN RGM 13 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCD74106RGMR VQFN RGM 13 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCD74106RGMT VQFN RGM 13 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD74106RGMR VQFN RGM 13 3000 346.0 346.0 29.0 UCD74106RGMT VQFN RGM 13 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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