TI TLC372QD

TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
D
D
D
D
D
D
D
D
D
TLC372C, TLC372I, TLC372M, TLC372Q
D, P, OR PW PACKAGE
TLC372M . . . JG PACKAGE
(TOP VIEW)
1OUT
1IN –
1IN +
GND
8
2
7
3
6
4
5
VCC
2OUT
2IN –
2IN +
TLC372M . . . FK PACKAGE
(TOP VIEW)
NC
1IN –
NC
1IN +
NC
description
This device is fabricated using LinCMOS
technology and consists of two independent
voltage comparators, each designed to operate
from a single power supply. Operation from dual
supplies is also possible if the difference between
the two supplies is 2 V to 18 V. Each device
features extremely high input impedance
(typically greater than 1012 Ω), allowing direct
interfacing with high-impedance sources. The
outputs are n-channel open-drain configurations
and can be connected to achieve positive-logic
wired-AND relationships.
1
NC
1OUT
NC
VDD
NC
D
Single or Dual-Supply Operation
Wide Range of Supply Voltages
2 V to 18 V
Very Low Supply Current Drain
150 µA Typ at 5 V
Fast Response Time . . . 200 ns Typ for
TTL-Level Input Step
Built-in ESD Protection
High Input Impedance . . . 1012 Ω Typ
Extremely Low Input Bias Current
5 pA Typ
Ultrastable Low Input Offset Voltage
Input Offset Voltage Change at Worst-Case
Input Conditions Typically 0.23 µV/Month,
Including the First 30 Days
Common-Mode Input Voltage Range
Includes Ground
Output Compatible With TTL, MOS, and
CMOS
Pin-Compatible With LM393
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
NC
2OUT
NC
2IN –
NC
NC
GND
NC
2IN+
NC
D
D
NC – No internal connection
symbol (each comparator)
IN +
OUT
IN –
The TLC372 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 1000-V
ESD rating using human body model testing. However, care should be exercised in handling this device as
exposure to ESD may result in a degradation of the device parametric performance.
The TLC372C is characterized for operation from 0°C to 70°C. The TLC372I is characterized for operation from
– 40°C to 85°C. The TLC372M is characterized for operation over the full military temperature range of – 55°C
to 125°C. The TLC372Q is characterized for operation from – 40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
equivalent schematic (each comparator)
Common to All Channels
VDD
OUT
GND
IN +
IN –
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIO max
AT 25°C
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
TSSOP
(PW)
CHIP
FORM
(Y)
0°C to 70°C
5 mV
TLC372CD
—
—
TLC372CP
TLC372CPW
TLC372Y
– 40°C to 85°C
5 mV
TLC372ID
—
—
TLC372IP
—
—
– 55°C to 125°C
5 mV
TLC372MD
TLC372MFK
TLC372MJG
TLC372MP
—
—
– 40°C to 125°C
5 mV
TLC372QD
—
—
TLC372QP
—
—
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC372CDR).
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
TLC372Y chip information
These chips, when properly assembled, display characteristics similar to the TLC372C. Thermal compression
or ultrasonic bonding can be used on the doped-aluminum bonding pads. Chips can be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(6)
(7)
(5)
1IN +
(3)
(2)
1IN –
2OUT
VCC +
(8)
+
(1)
1OUT
–
+
(7)
–
57
(5)
(6)
2IN +
2IN –
(4)
(8)
(4)
GND
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 3.6 × 3.6 MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
(2)
(1)
(3)
ALL DIMENSIONS ARE IN MILS.
PIN (4) INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
57
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage, VID (see Note 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 18 V
Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: TLC372C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC372I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
TLC372M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
TLC372Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values except differential voltages are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN –.
3. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING
FACTOR
DERATE
ABOVE TA
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
500 mW
5.8 mW/°C
64°C
464 mW
377 mW
145 mW
FK
500 mW
11.0 mW/°C
104°C
500 mW
500 mW
275 mW
JG
500 mW
8.4 mW/°C
90°C
500 mW
500 mW
210 mW
P
500 mW
8.0 mW/°C
87°C
500 mW
500 mW
200 mW
PW
525 mW
4.2 mW/°C
25°C
336 mW
N/A
N/A
recommended operating conditions
TLC372C
MIN
Supply voltage, VDD
Common mode input voltage,
Common-mode
voltage VIC
VDD = 5 V
VDD = 10 V
Operating free-air temperature, TA
4
POST OFFICE BOX 655303
TLC372I
TLC372M
TLC372Q
MAX
MIN
MAX
MIN
3
16
4
16
4
16
0
3.5
0
3.5
0
3.5
8.5
0
8.5
0
8.5
0
8.5
70
– 40
85
– 55
125
– 40
125
MAX
MIN
3
16
0
3.5
0
0
• DALLAS, TEXAS 75265
MAX
UNIT
V
V
°C
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
IIO
Input offset current
IIB
Input bias current
VICR
Common mode in
Common-mode
input
ut
voltage range
TEST CONDITIONS
VIC = VICRmin
min,
See Note 4
TA†
TLC372C
MIN
25°C
TYP
1
Full range
MAX
VOH = 5 V
VOH = 15 V
VOL
Low level output voltage
Low-level
VID = – 1 V
V,
IOL = 4 mA
IOL
Low-level output current
VID = – 1 V,
VOL = 1.5 V
IDD
Supply
y current
(two comparators)
VID = 1 V
V,
No load
5
25°C
0 to
VDD –1
0 to
VDD –1.5
25°C
150
Full range
150
25°C
16
150
Full range
0.1
150
700
6
300
16
150
400
400
700
6
300
nA
nA
3
400
nA
V
1
400
mV
pA
20
0.1
700
6
10
0 to
VDD –1
0 to
VDD –1.5
1
UNIT
pA
5
2
0.1
5
1
1
0.6
MAX
10
5
0 to
VDD –1
0 to
VDD –1.5
TYP
1
1
0.3
Full range
25°C
1
MIN
16
150
400
µA
mV
mA
300
400
µA
† All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC372C, – 40°C to 85°C for TLC372I, and – 55°C to
125°C for TLC372M and – 40°C to 125°C for TLC372Q. IMPORTANT: See Parameter Measurement Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and VDD. They can
be verified by applying the limit value to the input and checking for the appropriate output state.
switching characteristics, VDD = 5 V, TA = 25°C
PARAMETER
Response time
TEST CONDITIONS
RL connected to 5 V through 5.1 kΩ, CL = 15 pF
F ‡,
See Note 5
MIN
TYP
100-mV input step with 5-mV overdrive
650
TTL-level input step
200
‡ CL includes probe and jig capacitance.
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
MAX
UNIT
ns
5
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
VID = 1 V
MAX
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
High level output current
High-level
TLC372M, TLC372Q
TYP
7
5
MAX
IOH
5
1
25°C
Full range
MIN
6.5
25°C
25°C
TLC372I
MAX
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
electrical characteristics at specified free-air temperature, VDD = 5 V, TA = 25°C (unless otherwise
noted)
TLC372Y
TEST CONDITIONS†
PARAMETER
VIC = VICRmin,
MIN
See Note 4
TYP
MAX
1
5
UNIT
VIO
IIO
Input offset voltage
Input offset current
1
pA
IIB
Input bias current
5
pA
VICR
Common-mode input voltage range
IOH
VOL
High-level output current
0 to
VDD –1
VID = 1 V,
VID = – 1 V,
Low-level output voltage
VOH = 5 V
IOL = 4 mA
mV
V
0.1
nA
150
400
mV
IOL
Low-level output current
VID = – 1 V,
VOL = 1.5 V
6
16
mA
IDD
Supply current (two comparators)
VID = 1 V,
No load
150
300
µA
† All characteristics are measured with zero common-mode input voltage unless otherwise noted. IMPORTANT: See Parameter Measurement
Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor
between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state.
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLC372 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater
accuracy.
5V
1V
5.1 kΩ
+
+
–
5.1 kΩ
–
Applied VIO
Limit
VO
Applied VIO
Limit
–4 V
(a) VIO WITH VIC = 0
VO
(b) VIO WITH VIC = 4 V
Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but
opposite in polarity, to the input offset voltage, the output changes states.
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
+
Buffer
C2
1 µF
DUT
–
R8
1.8 kΩ, 1%
–
U1a
1/4 TLC274CN
+
Triangle
Generator
R3
100 kΩ
R7
1 MΩ
R4
47 kΩ
R1
240 kΩ
C1
0.1 µF
R6
5.1 kΩ
R2
10 kΩ
C3
0.68 µF
U1c
1/4 TLC274CN
–
U1b
1/4 TLC274C
R5
1.8 kΩ, 1%
+
VDD
VIO
(X100)
Integrator
C4
0.1 µF
R9
10 kΩ, 1%
R10
100 kΩ, 1%
Figure 2. Circuit for Input Offset Voltage Measurement
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
Response time is defined as the interval between the application of an input step function and the instant when the
output reaches 50% of its maximum value. Response time, low-to-high-level output, is measured from the leading
edge of the input pulse, while response time, high-to-low-level output, is measured from the trailing edge of the input
pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The
offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 3, so that the circuit
is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change
state.
VDD
5.1 kΩ
Pulse
Generator
DUT
50 Ω
CL
(see Note A)
1V
Input Offset Voltage
Compensation Adjustment
1 µF
10 Ω
10 Turn
1 kΩ
–1 V
0.1 µF
TEST CIRCUIT
Overdrive
100 mV
Overdrive
Input
Input
100 mV
90%
Low-to-HighLevel Output
90%
ÁÁÁ
50%
High-to-LowLevel Output
10%
tr
50%
10%
tf
tPHL
tPLH
VOLTAGE WAVEFORMS
NOTE A: CL includes probe and jig capacitance.
Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
PRINCIPLES OF OPERATION
LinCMOS process
The LinCMOS process is a Linear polysilicon-gate complementary-MOS process. Primarily designed for
single-supply applications, LinCMOS products facilitate the design of a wide range of high-performance
analog functions, from operational amplifiers to complex mixed-mode converters.
While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.
This short guide is intended to answer the most frequently asked questions related to the quality and reliability
of LinCMOS products. Further questions should be directed to the nearest TI field sales office.
electrostatic discharge
CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only
for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to
CMOS devices. It can occur when a device is handled without proper consideration for environmental
electrostatic charges, e.g. during board assembly. If a circuit in which one amplifier from a dual operational
amplifier is being used and the unused pins are left open, high voltages tends to develop. If there is no provision
for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail.
To prevent voltage buildup, each pin is protected by internal circuitry.
Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more
transistors break down at voltages higher than the normal operating voltages but lower than the breakdown
voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the
shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are
small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as
tens of picoamps.
To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in
Figure 4. This circuit can withstand several successive 1-kV ESD pulses, while reducing or eliminating leakage
currents that may be drawn through the input pins. A more detailed discussion of the operation of TI’s ESDprotection circuit is presented on the next page.
All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protection
circuitry that undergoes qualification testing to withstand 1000 V discharged from a 100-pF capacitor through
a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor
(charged device model). These tests simulate both operator and machine handling of devices during normal
test and assembly operations.
VDD
R1
Input
To Protected Circuit
R2
Q1
Q2
D1
D2
D3
VSS
Figure 4. LinCMOS ESD-Protection Schematic
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
PRINCIPLES OF OPERATION
input protection circuit operation
Texas Instruments patented protection circuitry allows for both positive-and negative-going ESD transients.
These transients are characterized by extremely fast rise times and usually low energies, and can occur both
when the device has all pins open and when it is installed in a circuit.
positive ESD transients
Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input rises
above the voltage on the VDD pin by a value equal to the VEB of Q1. The base current increases through R2
with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2
to exceed its threshold level (VT ~ 22 V to 26 V) and turn Q2 on. The shunted input current through Q1 to VSS
is now shunted through the n-channel enhancement-type MOSFET Q2 to VSS. If the voltage on the input pin
continues to rise, the breakdown voltage of the zener diode D3 is exceeded, and all remaining energy is
dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 to 27 V, which is well below the gate
oxide voltage of the circuit to be protected.
negative ESD transients
The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1
and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is – 0.3 V to – 1 V (the forward
voltage of D1 and D2).
circuit-design considerations
LinCMOS products are being used in actual circuit environments that have input voltages that exceed the
recommended common-mode input voltage range and activate the input protection circuit. Even under normal
operation, these conditions occur during circuit power up or power down, and in many cases, when the device
is being used for a signal conditioning function. The input voltages can exceed VICR and not damage the device
only if the inputs are current limited. The recommended current limit shown on most product data sheets is
± 5 mA. Figures 5 and 6 show typical characteristics for input voltage versus input current.
Normal operation and correct output state can be expected even when the input voltage exceeds the positive
supply voltage. Again, the input current should be externally limited even though internal positive current limiting
is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input
current. This base current is forced into the VDD pin and into the device IDD or the VDD supply through R2
producing the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the input
voltage is below the VT of Q2.
When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be
severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and
no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is
required (see Figure 7).
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
PRINCIPLES OF OPERATION
circuit-design considerations (continued)
INPUT CURRENT
vs
INPUT VOLTAGE
INPUT CURRENT
vs
INPUT VOLTAGE
8
10
TA = 25°C
TA = 25°C
9
7
8
Input Current – mA
Input Current – mA
6
5
4
3
7
6
5
4
3
2
2
1
1
0
VDD
VDD + 4
VDD + 8
Input Voltage – V
0
VDD – 0.3
VDD + 12
VDD – 0.5
VDD – 0.7
Input Voltage – V
VDD – 0.9
Figure 6
Figure 5
VDD
Positive Voltage Input Current LImit:
RI =
RI
VI
See Note A
+
Vref
TLC372
–
RL
+VI – VDD – 0.3 V
5 mA
Negative Voltage Input Current LImit:
RI =
– VI – VDD – (– 0.3 V)
5 mA
NOTE A: If the correct output state is required when the negative input exceeds VSS, a schottky clamp is required.
Figure 7. Typical Input Current-Limiting Configuration for a LinCMOS Comparator
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