SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003
D Meet or Exceed Standards TIA/EIA-422-B
D
D
D
D
D
D
D
D
D
D
SN65C1167 . . . DB OR NS PACKAGE
SN75C1167 . . . DB, N, OR NS PACKAGE
(TOP VIEW)
and ITU Recommendation V.11
BiCMOS Process Technology
Low Supply-Current Requirements:
9 mA Max
Low Pulse Skew
Receiver Input Impedance . . . 17 kΩ Typ
Receiver Input Sensitivity . . . ±200 mV
Receiver Common-Mode Input Voltage
Range of −7 V to 7 V
Operate From Single 5-V Power Supply
Glitch-Free Power-Up/Power-Down
Protection
Receiver 3-State Outputs Active-Low
Enable for SN65C1167 and SN75C1167 Only
Improved Replacements for the MC34050
and MC34051
1B
1A
1R
RE
2R
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
1D
1Y
1Z
DE
2Z
2Y
2D
SN65C1168 . . . N, NS, OR PW PACKAGE
SN75C1168 . . . DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1B
1A
1R
1DE
2R
2A
2B
GND
description/ordering information
The SN65C1167, SN75C1167, SN65C1168,
and SN75C1168 dual drivers and receivers are
integrated circuits designed for balanced
transmission
lines.
The
devices
meet
TIA/EIA-422-B and ITU recommendation V.11.
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
1D
1Y
1Z
2DE
2Z
2Y
2D
ORDERING INFORMATION
0°C to 70°C
TOP-SIDE
MARKING
PDIP (N)
Tube
SN75C1167N
SN75C1167N
SOP (NS)
Tape and reel
SN75C1167NSR
75C1167
SSOP (DB)
Tape and reel
SN75C1167DBR
CA1167
PDIP (N)
Tube
SN75C1168N
SN75C1168N
SOP (NS)
Tape and reel
SN75C1168NSR
75C1168
SSOP (DB)
Tape and reel
SN75C1168DBR
CA1168
Tube
SN75C1168PW
Tape and reel
SN75C1168PWR
SOP (NS)
Tape and reel
SN65C1167NSR
65C1167
SSOP (DB)
Tape and reel
SN65C1167DBR
CB1167
PDIP (N)
Tube
SN65C1168N
SN65C1168N
SOP (NS)
Tape and reel
SN65C1168NSR
65C1168
Tube
SN65C1168PW
Tape and reel
SN65C1168PWR
TSSOP (PW)
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TSSOP (PW)
CA1168
CB1168
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003
description/ordering information (continued)
The SN65C1167 and SN75C1167 combine dual 3-state differential line drivers and 3-state differential line
receivers, both of which operate from a single 5-V power supply. The driver and receiver have active-high and
active-low enables, respectively, which can be connected together externally to function as direction control.
The SN65C1168 and SN75C1168 drivers have individual active-high enables.
Function Tables
EACH DRIVER
OUTPUTS
INPUT
D
ENABLE
DE
H
H
H
L
L
H
L
H
X
L
Z
Z
Y
Z
SN75C1167, EACH RECEIVER
DIFFERENTIAL INPUTS
A−B
ENABLE
RE
OUTPUT
R
VID ≥ 0.2 V
−0.2 V < VID < 0.2 V
L
H
L
?
VID ≤ −0.2 V
X
L
L
H
Z
Open
L
H
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
logic diagram (positive logic)
SN65C1167/SN75C1167
DE
SN65C1168, SN75C1168
12
4
1DE
15
4
1D
RE
1D
15
3
1R
9
2D
5
2R
2
14
13
2
1
10
11
6
7
1Y
1Z
1A
3
1R
2D
9
2R
5
2Z
2A
2B
POST OFFICE BOX 655303
13
2
1
12
2DE
1B
2Y
14
• DALLAS, TEXAS 75265
10
11
6
7
1Y
1Z
1A
1B
2Y
2Z
2A
2B
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003
schematics of inputs
EQUIVALENT OF DRIVER ENABLE INPUT
EQUIVALENT OF A OR B INPUT
VCC
VCC
17 kΩ
NOM
Input
1.7 kΩ
NOM
Input
288 kΩ
NOM
1.7 kΩ
NOM
VCC (A)
or
GND (B)
GND
GND
schematics of outputs
TYPICAL OF EACH DRIVER OUTPUT
TYPICAL OF EACH RECEIVER OUTPUT
VCC
VCC
Output
Output
GND
GND
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input voltage range, VI (A or B, Receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −11 V to 14 V
Differential input voltage range, VID, Receiver (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −14 V to 14 V
Output voltage range, VO, Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 V to 7 V
Clamp current range, IIK or IOK, Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output current range, IO, Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±150 mA
Supply current, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
GND current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −200 mA
Output current range, IO, Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Operating virtual junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Package thermal impedance, θJA (see Notes 3 and 4): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values except differential input voltage are with respect to the network GND.
2. Differential input voltage is measured at the noninverting terminal with respect to the inverting terminal.
3. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Selecting the maximum of 150°C can affect reliability.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
VCC
Supply voltage
VIC
Common-mode input voltage
(see Note 5)
Receiver
VID
VIH
Differential input voltage
Receiver
High-level input voltage
Except A, B
VIL
Low-level input voltage
Except A, B
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
MIN
NOM
MAX
4.5
5
5.5
V
±7
V
±7
V
2
−20
mA
6
Driver
20
SN75C1167, SN75C1168
0
70
SN65C1167, SN65C1168
−40
85
NOTE 5: Refer to TIA/EIA-422-B for exact conditions.
POST OFFICE BOX 655303
V
−6
Driver
Receiver
4
V
0.8
Receiver
UNIT
• DALLAS, TEXAS 75265
mA
°C
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VIK
VOH
Input clamp voltage
VOL
|VOD1|
Low-level output voltage
|VOD2|
Differential output voltage
∆|VOD|
Change in magnitude of differential
output voltage
TEST CONDITIONS
II = −18 mA
VIH = 2 V,
High-level output voltage
VIH = 2 V,
IO = 0 mA
Differential output voltage
VIL = 0.8 V,
VIL = 0.8 V,
IOH = −20 mA
IOL = 20 mA
MIN
TYP†
2.4
3.4
0.2
2
2
RL = 100 Ω,
VOC
Common-mode output voltage
∆|VOC|
Change in magnitude of common-mode
output voltage
IO(OFF)
Output current with power off (see Note 3)
VCC = 0 V
IOZ
High-impedance-state output current
VO = 2.5 V
VO = 5 V
IIH
IIL
High-level input current
IOS
Short-circuit output current
ICC
Supply current (total package)
UNIT
−1.5
V
V
0.4
V
6
V
3.1
See Figure 1 and Note 5
VO = 6 V
VO = −0.25 V
V
±0.4
V
±3
V
±0.4
V
100
µA
−100
µA
20
−20
VI = VCC or VIH
VI = GND or VIL
Low-level input current
MAX
1
VO = VCC or GND,
See Note 6
V
=
V
or
GND
No load,
I
CC
Enabled
VI = 2.4 or 0.5 V, See Note 7
−30
µA
A
µA
−1
µA
−150
mA
4
6
5
9
mA
Ci
Input capacitance
6
pF
† All typical values are at VCC = 5 V and TA = 25°C.
NOTES: 5. Refer to TIA/EIA-422-B for exact conditions.
6. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
7. This parameter is measured per input, while the other inputs are at VCC or GND.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPHL
tPLH
Propagation delay time, high- to low-level output
tsk(p)
Pulse skew
tr
Rise time
tf
Fall time
tPZH
Output enable time to high level
tPZL
Output enable time to low level
tPHZ
Output disable time from low level
Propagation delay time, low- to high-level output
tPLZ
Output disable time from high level
† All typical values are at VCC = 5 V and TA = 25°C.
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
See Figure 2
R3 = 500 Ω,
S1 is open,
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
See Figure 3
R3 = 500 Ω,
S1 is open,
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
See Figure 4
R3 = 500 Ω,
S1 is closed,
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
See Figure 4
R3 = 500 Ω,
S1 is closed,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP†
MAX
7
12
ns
UNIT
7
12
ns
0.5
4
ns
5
10
ns
5
10
ns
10
19
ns
10
19
ns
7
16
ns
7
16
ns
5
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage,
differential input
VIT−
Negative-going input threshold voltage,
differential input
TYP†
MAX
0.2
−0.2‡
Vhys
VIK
Input hysteresis (VIT+ − VIT−)
VOH
VOL
High-level output voltage
II = −18 mA
VID = 200 mV,
Low-level output voltage
VID = −200 mV,
Input clamp voltage, RE
MIN
IOZ
High-impedance-state output
current
II
Line input current
II
ri
Enable input current, RE
Input resistance
VI = VCC or GND
VIC = −7 V to 7 V,
ICC
Supply current (total package)
No load, Enabled
SN75C1167
SN75C1167
3.8
VO = VCC or GND
Other input at 0 V
mV
−1.5
IOH = −6 mA
IOL = 6 mA
4.2
V
V
0.1
0.3
V
±0.5
±5
µA
VI = 10 V
VI = −10 V
1.5
−2.5
±1
Other input at 0 V
V
V
60
SN75C1167
UNIT
4
VI = VCC or GND
VIH = 2.4 V or 0.5 V,
See Note 5
17
mA
µA
kΩ
4
6
5
9
mA
† All typical values are at VCC = 5 V and TA = 25°C.
‡ The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 5: Refer to TIA/EIA-422-B for exact conditions.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 8)
PARAMETER
TEST CONDITIONS
tPLH
tPHL
Propagation delay time, low- to high-level output
tTLH
tTHL
Transition time, low- to high-level output
tPZH
tPZL
Output enable time to high level
tPHZ
tPLZ
Output disable time from high level
See Figure 5
Propagation delay time, high- to low-level output
VIC = 0 V,
Transition time, high- to low-level output
Output enable time to low level
RL = 1 kW,
Output disable time from low level
† All typical values are at VCC = 5 V and TA = 25°C.
NOTE 8: Measured per input while the other inputs are at VCC or GND
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
See Figure 5
See Figure 6
MIN
TYP†
MAX
9
17
27
ns
9
17
27
ns
4
9
ns
4
9
ns
13
22
ns
13
22
ns
13
22
ns
13
22
ns
UNIT
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003
PARAMETER MEASUREMENT INFORMATION
RL
2
VOD2
RL
2 VOC
Figure 1. Driver Test Circuit, VOD and VOC
3V
Input
(see Note B)
tPLH
Y
Input
VOH
R3
50%
1.3 V
Y
1.5 V
C1
S1
tsk(p)
R2
C3
0V
tPHL
R1
C2
1.3 V
1.3 V
50%
1.3 V
VOL
tsk(p)
VOH
Z
50%
1.3 V
Z
See Note A
tPHL
50%
1.3 V
VOL
tPLH
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. C1, C2, and C3 include probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf ≤ 6 ns.
Figure 2. Driver Test Circuit and Voltage Waveforms
C2
Input
C1
R1
0V
R3
VOD
1.5 V
S1
R2
C3
3V
Input
(see Note B)
Differential
Output
90%
90%
10%
10%
tr
See Note A
tf
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. C1, C2, and C3 include probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf ≤ 6 ns.
Figure 3. Driver Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003
PARAMETER MEASUREMENT INFORMATION
3V
Input DE
1.3 V
R1
R3
C2
0V
or
3V
Pulse
Generator
See Note B
tPLZ
C1
S1
1.5 V
1.5 V
Output
VOL + 0.3 V
0.8 V
VOL
tPHZ
DE
50 Ω
0V
tPZL
R2
C3
1.5 V
tPZH
VOH
See Note A
VOL − 0.3 V
Output
2V
1.5 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. C1, C2, and C3 include probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf ≤ 6 ns.
Figure 4. Driver Test Circuit and Voltage Waveforms
VCC
S1
tTLH
Output
(see Note B)
A Input
B Input
RL
Device
Under
Test
10%
tTHL
90%
50%
50%
tPLH
CL = 50 pF
(see Note A)
VOLTAGE WAVEFORMS
Figure 5. Receiver Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VOL
2.5 V
0V
−2.5 V
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr = tf ≤ 6 ns.
8
VOH
tPHL
B Input
A Input = 0 V
TEST CIRCUIT
90%
10%
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003
PARAMETER MEASUREMENT INFORMATION
3V
RE Input
VCC
1.3 V
1.3 V
0V
S1
0.5 V
tPLZ
VCC
Output
RE Input
VID = −2.5 V
or 2.5 V
50%
VOL
RL
Device
Under
Test
tPZL
tPHZ
tPZH
VOH
CL = 50 pF
(see Note A)
50%
Output
GND
0.5 V
tPZL, tPLZ Measurement: S1 to VCC
tPZH, tPHZ Measurement: S1 to GND
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr = tf ≤ 6 ns.
Figure 6. Receiver Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
MECHANICAL
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
A MAX
0.775
(19,69)
0.775
(19,69)
0.920
(23,37)
1.060
(26,92)
A MIN
0.745
(18,92)
0.745
(18,92)
0.850
(21,59)
0.940
(23,88)
MS-100
VARIATION
AA
BB
AC
DIM
A
16
9
0.260 (6,60)
0.240 (6,10)
1
C
AD
8
0.070 (1,78)
0.045 (1,14)
0.045 (1,14)
0.030 (0,76)
D
D
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.430 (10,92) MAX
0.021 (0,53)
0.015 (0,38)
0.010 (0,25) M
14/18 PIN ONLY
20 pin vendor option
D
4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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