SCLS589 − AUGUST 2004 D Can Be Used as Two 16-Bit Counters or a D D D D D D D N OR PW PACKAGE (TOP VIEW) Single 32-Bit Counter 2-V to 5.5-V VCC Operation Max tpd of 25 ns at 5 V (RCLK to Y) Typical VOLP (Output Ground Bounce) <0.7 V at VCC = 5 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >4.4 V at VCC = 5 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) CLKA CLKB GAL GAU GBL GBU RCLK RCOA CLKBEN GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 CCLR description/ordering information The SN74LV8154 is a dual 16-bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation. This 16-bit counter (A or B) feeds a 16-bit storage register, and each storage register is further divided into an upper byte and lower byte. The GAL, GAU, GBL, GBU inputs are used to select the byte that needs to be output at Y0−Y7. CLKA is the clock for A counter, and CLKB is the clock for B counter. RCLK is the clock for the A and B storage registers. All three clock signals are positive-edge triggered. A 32-bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN. To ensure the high-impedance state during power up or power down, GAL, GAU, GBL, and GBU should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PDIP − N −40°C 85°C −40 C to 85 C ORDERABLE PART NUMBER PACKAGE† TA TSSOP − PW Tube SN74LV8154N Tube SN74LV8154PW Tape and reel SN74LV8154PWR TOP-SIDE MARKING SN74LV8154N LV8154 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS589 − AUGUST 2004 FUNCTION TABLE (each buffer) INPUTS GAL GAU GBL GBU OUTPUT Yn Lower byte in A register L H H H H L H H Upper byte in A register H H L H Lower byte in B register H H H L Upper byte in B register H H H H Z Combinations of GAL, GAU, GBL, GBU, other than those shown above, are prohibited. If more than one input is L at the same time, the output data (Y0−Y7) may be invalid. timing diagram CCKBEN CCLR CCKA CCKB RCLK A Counter 0000 0001 0002 0003 0004 B Counter 0000 0001 0002 0003 0004 00 01 02 0100 0101 0100 0102 0103 FFFD FFFE FFFF 0000 0001 0101 0102 FFFD FFFE FFFF 0000 0001 GAL GAU GBL GBU Output Don’t Care 03 00 RCOA 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 01 FF SCLS589 − AUGUST 2004 block diagram R R R R R R CCKB CCKBEN R R R R R R R R R 16-Bit Counter B R R R R R R R R R R R R R R R 4 to 1 Dec Y0 4 to 1 Dec Y1 4 to 1 Dec Y2 4 to 1 Dec Y3 4 to 1 Dec Y4 4 to 1 Dec Y5 4 to 1 Dec Y6 4 to 1 Dec Y7 R R RCLK CCKA CCLR 16-Bit Counter A GAL GAU GBL RCOA GBU absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCLS589 − AUGUST 2004 recommended operating conditions (see Note 4) VCC VCC Supply voltage 2V VIH 3 V to 3.6 V High-level input voltage 4.5 V to 5.5 V MIN MAX 2 5.5 VCC × 0.7 VCC × 0.7 0.5 4.5 V to 5.5 V VI Input voltage VO Output voltage 5.5 V High or low state 0 3-state 0 VCC 5.5 V −50 µA Yn outputs Yn outputs −6 −12 2V −50 3 V to 3.6 V −6 4.5 V to 5.5 V −12 2V 50 3 V to 3.6 V 6 4.5 V to 5.5 V 12 2V 50 Low-level output current RCOA ∆t/∆v 3 V to 3.6 V 4.5 V to 5.5 V High-level output current RCOA IOL V 0 2V IOH V VCC × 0.3 VCC × 0.3 3 V to 3.6 V Low-level input voltage V 1.5 2V VIL UNIT Input transition rise or fall rate 3 V to 3.6 V 6 4.5 V to 5.5 V 12 3 V to 3.6 V 100 4.5 V to 5.5 V 20 mA µA mA µA mA µA mA ns/V TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS589 − AUGUST 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Yn VOH RCOA Yn VOL RCOA MIN IOH = −50 µA IOH = −6 mA 2V 3V 2.48 IOH = −12 mA IOH = −50 µA 4.5 V 3.8 2V 1.9 IOH = −6 mA IOH = −12 mA 3V 2.48 4.5 V 3.8 TYP MAX V 2V 0.1 3V 0.44 IOL = 12 mA IOL = 50 µA 4.5 V 0.55 2V 0.1 IOL = 6 mA IOL = 12 mA 3V 0.44 4.5 V 0.55 VI = 5.5 V or GND VO = VCC or GND ICC Ioff VI = VCC or GND, IO = 0 VI or VO = 0 to 5.5 V Ci VI = VCC or GND VO = VCC or GND UNIT 1.9 IOL = 50 µA IOL = 6 mA II IOZ Co VCC V ±1 µA 5.5 V ±5 µA 5.5 V 20 µA 0 5 µA 0 to 5.5 V 5V 3 pF 5V 5 pF timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) MIN tw tsu Pulse duration Setup time th Hold time tz† Z-period CLKA, CLKB, RCLK high or low 10 CCLR low 22 CLKBEN low before CLKB↑ 13 CCLR high (inactive) before CLKA↑ or CLKB↑ 13 CLKA↑ or CLKB↑ before RCLK↑ 13 RCLK↑ before GAL or GAU or GBL or GBU low 13 GAL or GAU or GBL or GBU high (inactive) before RCLK↑ 13 CLKBEN low after CLKB↑ 0 CLKA or CLKB after RCLK 0 GAL, GAU, GBL, GBU all high before one of them switches low 200 MAX UNIT ns ns ns ns † tz condition: CL = 50 pF, RL = 1 kΩ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCLS589 − AUGUST 2004 timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) MIN tw Pulse duration tsu Setup time th Hold time tz† Z-period CLKA, CLKB, RCLK high or low 10 CCLR low 20 CLKBEN low before CLKB↑ 10 CCLR high (inactive) before CLKA↑ or CLKB↑ 10 CLKA↑ or CLKB↑ before RCLK↑ 10 RCLK↑ before GAL or GAU or GBL or GBU low 10 GAL or GAU or GBL or GBU high (inactive) before RCLK↑ 10 CLKBEN low after CLKB↑ 0 CLKA or CLKB after RCLK 0 GAL, GAU, GBL, GBU all high before one of them switches low MAX UNIT ns ns ns 200 ns temperature range, † tz condition: CL = 50 pF, RL = 1 kΩ switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fMAX tpd tPLH TA = 25°C MIN TYP MAX MIN CL = 15 pF 40 CL = 50 pF 25 MAX UNIT MHz RCLK Y 22 1 38 CLKA RCOA 26 1 44 ns CCLR RCOA 18 1 32 ns ten GAL, GAU, GBL, GBU Y 27 1 46 ns tdis GAL, GAU, GBL, GBU Y 12 1 21 ns RCLK Y 25 1 42 CLKA RCOA 28 1 46 CCLR RCOA 20 1 35 ns ten GAL, GAU, GBL, GBU Y 30 1 50 ns tdis GAL, GAU, GBL, GBU Y 14 1 24 ns tpd tPLH 6 LOAD CAPACITANCE free-air POST OFFICE BOX 655303 CL = 15 pF CL = 50 pF • DALLAS, TEXAS 75265 ns SCLS589 − AUGUST 2004 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE fMAX free-air MIN temperature TA = 25°C TYP MAX MIN CL = 15 pF 40 CL = 50 pF 25 MAX range, UNIT MHz RCLK Y 14 1 25 CLKA RCOA 16 1 27 CCLR RCOA 12 1 20 ns ten GAL, GAU, GBL, GBU Y 16 1 28 ns tdis GAL, GAU, GBL, GBU Y 8 1 15 ns RCLK Y 16 1 27 CLKA RCOA 17 1 28 CCLR RCOA 13 1 21 ns ten GAL, GAU, GBL, GBU Y 18 1 30 ns tdis GAL, GAU, GBL, GBU Y 9 1 16 ns tpd tPLH tpd tPLH CL = 15 pF CL = 50 pF ns ns noise characteristics, VCC = 5 V, CL = 50 pF PARAMETER TA = 25°C MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.7 V Quiet output, minimum dynamic VOL −0.75 V VOH(V) Quiet output, minimum dynamic VOH 4.4 V operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = No load, CCLK = 10 MHz, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP RCLK = 1 MHz 56 UNIT pF 7 SCLS589 − AUGUST 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL VOH 50% VCC VOL 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH 50% VCC 50% VCC tPLZ tPZL tPHL tPHL Out-of-Phase Output 0V VCC Output Control ≈VCC 50% VCC tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated