SCES520A − DECEMBER 2003 − REVISED JUNE 2004 D Available in the Texas Instruments DBV OR DCK PACKAGE (TOP VIEW) NanoStar and NanoFree Packages D D D D D D D D Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) CLK GND D 1 6 2 5 3 4 OE VCC Q YEP OR YZP PACKAGE (BOTTOM VIEW) D GND CLK 3 4 2 5 1 6 Q VCC OE description/ordering information This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) −40 C to 85°C −40°C 85 C SOT (SOT-23) − DBV SOT (SC-70) − DCK TOP-SIDE MARKING‡ SN74LVC1G374YEPR Reel of 3000 _ _ _D4_ SN74LVC1G374YZPR Reel of 3000 SN74LVC1G374DBVR Reel of 250 SN74LVC1G374DBVT Reel of 3000 SN74LVC1G374DCKR Reel of 250 SN74LVC1G374DCKT CA4_ D4_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2004, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES520A − DECEMBER 2003 − REVISED JUNE 2004 description/ordering information (continued) A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS D OUTPUT Q OE CLK L ↑ L L L ↑ H H L H or L X Q H X X Z logic diagram (positive logic) OE CLK 6 1 C1 D 2 3 D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4 Q SCES520A − DECEMBER 2003 − REVISED JUNE 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCES520A − DECEMBER 2003 − REVISED JUNE 2004 recommended operating conditions (see Note 4) Operating VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI VO Input voltage Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V ∆t/∆v Low-level output current Input transition rise or fall rate 5.5 0.65 × VCC 1.7 V 2 0.7 × VCC 0.35 × VCC 0.7 0.8 V 0.3 × VCC 0 5.5 V 0 VCC −4 V −8 mA −24 −32 4 8 16 VCC = 3 V UNIT V 1.5 −16 VCC = 3 V VCC = 4.5 V VCC = 1.65 V IOL 1.65 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Output voltage High-level output current MAX VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 1.65 V VCC = 2.3 V IOH MIN mA 24 VCC = 4.5 V VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 32 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 10 20 ns/V 5 TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES520A − DECEMBER 2003 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −100 mA IOH = −4 mA VOH MIN 1.65 V to 5.5 V 1.65 V VCC−0.1 1.2 2.3 V 1.9 IOH = −8 mA IOH = −16 mA MAX 2.3 4.5 V IOH = −32 mA IOL = 100 mA IOL = 4 mA 3.8 1.65 V to 5.5 V 0.1 1.65 V 0.45 2.3 V 0.3 IOL = 8 mA IOL = 16 mA 0.4 3V IOL = 24 mA II IOZ VI = 5.5 V or GND VO = 0 to 5.5 V Ioff ICC VI or VO = 5.5 V VI = 5.5 V or GND, ∆ICC Ci One input at VCC − 0.6 V, 0.55 0 to 5.5 V ±1 mA 1.65 V to 5.5 V ±5 mA ±10 mA 10 mA 500 mA 0 IO = 0 Other inputs at VCC or GND V 0.55 4.5 V IOL = 32 mA UNIT V 2.4 3V IOH = −24 mA VOL TYP† VCC 1.65 V to 5.5 V 3 V to 5.5 V VI = VCC or GND Co VO = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. 3.3 V 3 pF 3.3 V 6 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V ± 0.15 V MIN MAX VCC = 2.5 V ± 0.2 V MIN MAX 100 VCC = 3.3 V ± 0.3 V MIN 125 MAX VCC = 5 V ± 0.5 V MIN 150 UNIT MAX fclock tw Clock frequency 175 MHz Pulse duration, CLK high or low 3.3 3 2.8 2.5 ns tsu th Setup time, data before CLK↑ 3.5 2.5 2 1.5 ns Hold time, data after CLK↑ 3.4 1.6 1.5 1.5 ns switching characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V FROM (INPUT) TO (OUTPUT) fmax tpd CLK Q 2.5 15 2 6 1.4 4 1 3 ns ten OE Q 2.2 12 2 4.8 1.3 3.8 1.1 2.5 ns tdis OE Q 2.2 11 2 4.8 1.6 4.5 1.2 3.1 ns PARAMETER MIN MAX 100 POST OFFICE BOX 655303 MIN MAX 125 • DALLAS, TEXAS 75265 MIN MAX 150 MIN UNIT MAX 175 MHz 5 SCES520A − DECEMBER 2003 − REVISED JUNE 2004 switching characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) fmax VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V MAX 100 MIN MAX 125 VCC = 3.3 V ± 0.3 V MIN MAX 150 VCC = 5 V ± 0.5 V MIN UNIT MAX 175 MHz tpd CLK Q 2.7 18.3 1.8 8.2 1.6 6 1 4 ns ten OE Q 2 13 1.5 6.3 0.9 5 0.7 3.5 ns tdis OE Q 2 14 1.1 5.3 1.4 4.5 0.8 3.1 ns operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Cpd 6 Power dissipation capacitance Outputs enabled Outputs disabled f = 10 MHz POST OFFICE BOX 655303 VCC = 1.8 V TYP VCC = 2.5 V TYP VCC = 3.3 V TYP VCC = 5 V TYP 24 24 25 27 8 8 9 11 • DALLAS, TEXAS 75265 UNIT pF SCES520A − DECEMBER 2003 − REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MΩ 1 MΩ 1 MΩ 1 MΩ 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SCES520A − DECEMBER 2003 − REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS114 – FEBRUARY 2002 DCK (R-PDSO-G6) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 6 0,10 M 4 1,40 1,10 1 0,13 NOM 2,40 1,80 3 Gage Plane 2,15 1,85 0,15 0°–8° 0,46 0,26 Seating Plane 1,10 0,80 0,10 0,00 0,10 4093553-3/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-203 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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