HITACHI 2SK3210S

2SK3210(L), 2SK3210(S)
Silicon N Channel MOS FET
High Speed Power Switching
ADE-208-760(Z)
Target Specification, 1st. Edition
Dec. 1, 1998
Features
• Low on-resistance
R DS =35mΩ typ.
• High speed switching
• 4V gate drive device can be driven from 5V source
Outline
LDPAK
4
D
1
1
G
S
4
2
3
2
3
1. Gate
2. Drain
3. Source
4. Drain
2SK3210(L), 2SK3210(S)
Absolute Maximum Ratings (Ta = 25°C)
Item
Symbol
Ratings
Unit
Drain to source voltage
VDSS
150
V
Gate to source voltage
VGSS
±20
V
Drain current
ID
30
A
120
A
30
A
30
A
67
mJ
100
W
Drain peak current
I D(pulse)
Body-drain diode reverse drain current
I DR
Avalanche current
Avalanche energy
I AP
Note1
Note3
EAR
Note3
Note2
Channel dissipation
Pch
Channel temperature
Tch
150
°C
Storage temperature
Tstg
–55 to +150
°C
Note:
2
1. PW ≤ 10µs, duty cycle ≤ 1 %
2. Value at Tc = 25°C
3. Value at Tch = 25°C, Rg ≥ 50Ω
2SK3210(L), 2SK3210(S)
Electrical Characteristics (Ta = 25°C)
Item
Symbol Min
Typ
Max
Unit
Test Conditions
Drain to source breakdown voltage V(BR)DSS
150
—
—
V
I D = 10mA, VGS = 0
Gate to source breakdown voltage V(BR)GSS
±20
—
—
V
I G = ±100µA, VDS = 0
Gate to source leak current
I GSS
—
—
±10
µA
VGS = ±16V, VDS = 0
Zero gate voltege drain current
I DSS
—
—
10
µA
VDS = 150 V, VGS = 0
Gate to source cutoff voltage
VGS(off)
1.0
—
2.5
V
I D = 1mA, VDS = 10V
Static drain to source on state
RDS(on)
—
35
45
mΩ
I D = 15A, VGS = 10VNote4
resistance
RDS(on)
—
42
75
mΩ
I D = 15A, VGS = 4V Note4
Forward transfer admittance
|yfs|
18
30
—
S
I D = 15A, VDS = 10V Note4
Input capacitance
Ciss
—
2600
—
pF
VDS = 10V
Output capacitance
Coss
—
820
—
pF
VGS = 0
Reverse transfer capacitance
Crss
—
350
—
pF
f = 1MHz
Turn-on delay time
t d(on)
—
25
—
ns
I D = 15A, VGS = 10V
Rise time
tr
—
180
—
ns
RL = 2Ω
Turn-off delay time
t d(off)
—
600
—
ns
Fall time
tf
—
280
—
ns
Body–drain diode forward voltage
VDF
—
0.95
—
V
I F = 30A, VGS = 0
Body–drain diode reverse
recovery time
t rr
—
110
—
ns
I F = 30A, VGS = 0
diF/ dt =50A/µs
Note:
4. Pulse test
3
2SK3210(L), 2SK3210(S)
1.2 ± 0.2
0.4 ± 0.1
2.54 ± 0.5
2.54 ± 0.5
L type
2.54 ± 0.5
(1.4)
(1.5)
(1.5)
1.27 ± 0.2
3.0 +0.3
–0.5
2.59 ± 0.2
4.44 ± 0.2
8.6 ± 0.3
10.0 +0.3
–0.5
10.2 ± 0.3
1.27 ± 0.2
0.76 ± 0.1
1.3 ± 0.2
11.3 ± 0.5
4.44 ± 0.2
11.0 ± 0.5
1.2 ± 0.2
0.86 +0.2
–0.1
8.6 ± 0.3
10.0 +0.3
–0.5
(1.5)
10.2 ± 0.3
(1.4)
Package Dimensions (Unit: mm)
1.3 ± 0.2
0.1 +0.2
–0.1
2.59 ± 0.2
0.4 ± 0.1
0.86 +0.2
–0.1
2.54 ± 0.5
S type
Hitachi Code
EIAJ
JEDEC
4
LDPAK
—
—
2SK3210(L), 2SK3210(S)
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
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received the latest product standards or specifications before final design, purchase or use.
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contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
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4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
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products.
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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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