HD74ALVCH162831 1-bit 4-bit Address Register / Driver with 3-state Outputs ADE-205-195 (Z) Preliminary 1st. Edition March 1998 Description This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation. The device is ideal for use in applications in which a single address bus is driving four separate memory locations. The HD74ALVCH162831 can be used as a buffer or a register, depending on the logic level of the select (SEL) input. When SEL is logic high, the device is in the buffer mode. The outputs follow the inputs and are controlled by the two output enable (OE) controls. Each OE controls two groups of nine outputs. When SEL is logic low, the device is in the register mode. The register is an edge triggered D-type flip flop. On the positive transition of the clock (CLK) input, data set up at the A inputs is stored in the internal registers. OE controls operate the same as in buffer mode. When OE is logic low, the outputs are in a normal logic state (high or low logic level). When OE is logic high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to V CC through a pullup registor; the minimum value of the registor is determined by the current sinking capability of the driver. SEL and OE do not affect the internal operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±12 mA (@VCC = 3.0 V) • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors. • All outputs have equivalent 26 Ω series resistors, so no external resistors are required. HD74ALVCH162831 Function Table Inputs Output Y OE SEL CLK A H X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H H H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition 2 HD74ALVCH162831 Pin Arrangement 4Y1 3Y1 GND 2Y1 1Y1 VCC NC A1 GND NC A2 GND NC A3 VCC NC A4 GND CLK OE1 OE2 SEL GND A5 A6 VCC A7 NC GND A8 NC GND A9 NC VCC 4Y9 3Y9 GND 2Y9 1Y9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1Y2 2Y2 GND 3Y2 4Y2 VCC 1Y3 2Y3 GND 3Y3 4Y3 GND 1Y4 2Y4 VCC 3Y4 4Y4 GND 1Y5 2Y5 3Y5 4Y5 GND 1Y6 2Y6 VCC 3Y6 4Y6 GND 1Y7 2Y7 GND 3Y7 4Y7 VCC 1Y8 2Y8 GND 3Y8 4Y8 (Top view) 3 HD74ALVCH162831 Absolute Maximum Ratings Item Symbol Ratings Unit VCC –0.5 to 4.6 V VI –0.5 to 4.6 V VO –0.5 to VCC +0.5 V Input clamp current I IK –50 mA VI < 0 Output clamp current I OK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±50 mA VO = 0 to VCC VCC, GND current / pin I CC or IGND ±100 mA Maximum power dissipation at Ta = 55°C (in still air) *3 PT 1 W Storage temperature Tstg –65 to 150 °C Supply voltage Input voltage *1 Output voltage Notes: *1, 2 Conditions TVSOP Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage VCC 2.3 3.6 V Input voltage VI 0 VCC V Output voltage VO 0 VCC V High level output current I OH — –6 mA — –8 VCC = 2.7 V — –12 VCC = 3.0 V — 6 — 8 VCC = 2.7 V — 12 VCC = 3.0 V Low level output current I OL mA Input transition rise or fall rate ∆t / ∆v 0 10 ns / V Operating temperature Ta –40 85 °C Note: Unused control inputs must be held high or low to prevent them from floating. 4 Conditions VCC = 2.3 V VCC = 2.3 V HD74ALVCH162831 Logic Diagram OE1 20 OE2 21 CLK 5 19 4 CLK 2 A1 8 D 2Y1 3Y1 Q 1 SEL 1Y1 4Y1 22 To eight other channels 5 HD74ALVCH162831 Electrical Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Input voltage VIH Max Unit Test Conditions 2.3 to 2.7 1.7 — V 2.7 to 3.6 2.0 — 2.3 to 2.7 — 0.7 2.7 to 3.6 — 0.8 2.3 to 3.6 VCC–0.2 — 2.3 1.9 — I OH = –4 mA, VIH = 1.7 V 2.3 1.7 — I OH = –6 mA, VIH = 1.7 V 2.7 2.4 — I OH = –6 mA, VIH = 2.0 V 3.0 2.0 — I OH = –8 mA, VIH = 2.0 V 3.0 2.0 — I OH = –12 mA, VIH = 2.0 V 2.3 to 3.6 — 0.2 I OL = 100 µA 2.3 — 0.4 I OL = 4 mA, VIL = 0.7 V 2.3 — 0.55 I OL = 6 mA, VIL = 0.7 V 3.0 — 0.55 I OL = 6 mA, VIL = 0.8 V 2.7 — 0.6 I OL = 8 mA, VIL = 0.8 V 3.0 — 0.8 I OL = 12 mA, VIL = 0.8 V I IN 3.6 — ±5 I IN (hold) 2.3 45 — VIN = 0.7 V 2.3 –45 — VIN = 1.7 V 3.0 75 — VIN = 0.8 V 3.0 –75 — VIN = 2.0 V 3.6 — ±500 VIN = 0 to 3.6 V *1 I OZ 3.6 — ±10 µA VOUT = VCC or GND Quiescent supply current I CC 3.6 — 40 µA VIN = VCC or GND 750 µA VIN = one input at (VCC–0.6) V, other inputs at V CC or GND VIL Output voltage VOH VOL Input current Off state output current ∆I CC Note: 6 Min 3.0 to 3.6 — V µA I OH = –100 µA VIN = VCC or GND 1. This is the bus hold maximum dynamic current required to switch the input from one state to another. HD74ALVCH162831 Switching Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Min Typ Max Unit Maximum clock frequency f max 2.5±0.2 150 — — MHz 2.7 150 — — 3.3±0.3 150 — — t PLH 2.5±0.2 1.1 — 4.7 t PHL 2.7 — — 4.8 3.3±0.3 1.5 — 4.3 2.5±0.2 1.0 — 5.3 2.7 — — 5.3 3.3±0.3 1.4 — 4.7 2.5±0.2 1.1 — 6.0 2.7 — — 6.2 3.3±0.3 1.5 — 4.8 t ZH 2.5±0.2 1.0 — 5.9 t ZL 2.7 — — 5.9 3.3±0.3 1.1 — 5.1 t HZ 2.5±0.2 1.4 — 6.3 t LZ 2.7 — — 5.4 3.3±0.3 1.6 — 5.1 2.5±0.2 2.0 — — 2.7 2.0 — — 3.3±0.3 1.6 — — 2.5±0.2 0.7 — — 2.7 0.5 — — 3.3±0.3 1.1 — — 2.5±0.2 3.3 — — 2.7 3.3 — — 3.3±0.3 3.3 — — 3.3 — 4.5 — 3.3 — 5.0 — 3.3 — 7.5 — Propagation delay time Output enable time Output disable time Setup time Hold time Pulse width Input capacitance Output capacitance t su th tw CIN CO FROM (Input) TO (Output) A Y CLK Y SEL Y ns OE Y ns OE Y ns ns ns ns pF Control inputs Data inputs pF 7 HD74ALVCH162831 Switching Characteristics (Ta = 0 to 65°C) Item Symbol VCC (V) Propagation delay time t PLH , t PHL 3.3±0.15 1.9 8 Min Typ Max Unit FROM (Input) TO (Output) — 4.5 ns CLK Y HD74ALVCH162831 Test Circuit See under table 500 Ω S1 OPEN GND *1 CL 500 Ω Load Circuit for Outputs Symbol t PLH / t PHL t su / t h / t w t ZH/ t HZ t ZL / t LZ CL Note: 1. Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V OPEN OPEN GND GND 2 × VCC 30 pF 6.0 V 50 pF CL includes probe and jig capacitance. 9 HD74ALVCH162831 Waveforms – 1 tf tr 90 % Input VIH 90 % Vref Vref 10 % 10 % GND t PHL t PLH VOH Output Vref Vref VOL Waveforms – 2 tr VIH 90 % Vref Timing Input 10 % tsu GND th VIH Data Input Vref Vref GND tw VIH Input Vref Vref GND 10 HD74ALVCH162831 Waveforms – 3 tf tr Output Control VIH 90 % 90 % Vref Vref 10 % t ZL 10 % GND t LZ ≈VOH1 Vref Waveform - A t ZH Waveform - B Vref1 VOL t HZ VOH Vref2 Vref ≈VOL1 TEST VIH Vref Vref1 Vref2 VOH1 VOL1 Notes: 1. 2. 3. 4. Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V VCC 2.7 V 1/2 VCC 1.5 V VOL +0.15 V VOL +0.3 V VOH–0.15 V VOH–0.3 V VCC 3.0 V GND GND All input pulses are supplied by generators having the following characteristics : PRR ≤ 10 MHz, Zo = 50 Ω, t r ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V) PRR ≤ 10 MHz, Zo = 50 Ω, t r ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V) Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. The output are measured one at a time with one transition per measurement. 11 HD74ALVCH162831 Package Dimensions Unit : mm 17.10 Max 41 6.20 Max 80 1 40 0.07 M 12° Max 0.75 Max Hitachi code EIAJ code JEDEC code 12 8.40 Max 1.20 max 0.08 0.15 Min 0.16 Typ 0.23 Max 0.40 — — — Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. 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