HD74ALVCH162334 16-bit Universal Bus Driver with 3-state Outputs ADE-205-210 (Z) Preliminary 1st. Edition December 1997 Description This HD74ALVCH162334 is a 16-bit universal bus driver is designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (O E) input. The device operates in the transparent mode when the latch enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±12 mA (@VCC = 3.0 V) • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors • All outputs have equivalent 26 Ω series resistors, so no external resistors are required HD74ALVCH162334 Function Table Inputs Output Y OE LE CLK A H X X X Z L L X L L L L X H H L H ↑ L L L H ↑ H H L H L or H X Y0 *1 H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Note: 1. Output level before the indicated steady state input conditions were established. 2 HD74ALVCH162334 Pin Arrangement OE 1 48 CLK Y1 2 47 A1 Y2 3 46 A2 45 GND GND 4 Y3 5 44 A3 Y4 6 VCC 7 43 A4 Y5 8 41 A5 Y6 9 40 A6 42 VCC 39 GND GND 10 Y7 11 38 A7 Y8 12 37 A8 Y9 13 36 A9 Y10 14 35 A10 GND 15 34 GND Y11 16 33 A11 Y12 17 32 A12 VCC 18 31 VCC Y13 19 30 A13 Y14 20 29 A14 GND 21 28 GND Y15 22 27 A15 Y16 23 26 A16 NC 24 25 LE (Top view) 3 HD74ALVCH162334 Absolute Maximum Ratings Item Symbol Ratings Unit VCC –0.5 to 4.6 V VI –0.5 to 4.6 V VO –0.5 to VCC +0.5 V Input clamp current I IK –50 mA VI < 0 Output clamp current I OK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±50 mA VO = 0 to VCC VCC, GND current / pin I CC or IGND ±100 mA Maximum power dissipation at Ta = 55°C (in still air) *3 PT 0.85 W Storage temperature Tstg –65 to 150 °C Supply voltage Input voltage *1 Output voltage Notes: *1, 2 Conditions TSSOP Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage VCC 2.3 3.6 V Input voltage VI 0 VCC V Output voltage VO 0 VCC V High level output current I OH — –6 mA — –8 VCC = 2.7 V — –12 VCC = 3.0 V — 6 — 8 VCC = 2.7 V — 12 VCC = 3.0 V Low level output current I OL mA Input transition rise or fall rate ∆t / ∆v 0 10 ns / V Operating temperature Ta –40 85 °C Note: Unused control inputs must be held high or low to prevent them from floating. 4 Conditions VCC = 2.3 V VCC = 2.3 V HD74ALVCH162334 Logic Diagram OE CLK LE A1 1 48 25 47 1D C1 CLK 2 Y1 To fifteen other channels 5 HD74ALVCH162334 Electrical Characteristics (Ta = –40 to 85°C) Item Symbo VCC (V) l Input voltage VIH Max Unit 2.3 to 2.7 1.7 — V 2.7 to 3.6 2.0 — 2.3 to 2.7 — 0.7 2.7 to 3.6 — 0.8 2.3 to 3.6 VCC–0.2 — 2.3 1.9 — I OH = –4 mA, VIH = 1.7 V 2.3 1.7 — I OH = –6 mA, VIH = 1.7 V 3.0 2.4 — I OH = –6 mA, VIH = 2.0 V 2.7 2.0 — I OH = –8 mA, VIH = 2.0 V 3.0 2.0 — I OH = –12 mA, VIH = 2.0 V 2.3 to 3.6 — 0.2 I OL = 100 µA 2.3 — 0.4 I OL = 4 mA, VIL = 0.7 V 2.3 — 0.55 I OL = 6 mA, VIL = 0.7 V 3.0 — 0.55 I OL = 6 mA, VIL = 0.8 V 2.7 — 0.6 I OL = 8 mA, VIL = 0.8 V 3.0 — 0.8 I OL = 12 mA, VIL = 0.8 V I IN 3.6 — ±5 I IN (hold) 2.3 45 — VIN = 0.7 V 2.3 –45 — VIN = 1.7 V 3.0 75 — VIN = 0.8 V 3.0 –75 — VIN = 2.0 V 3.6 — ±500 VIN = 0 to 3.6 V *1 VIL Output voltage VOH VOL Input current Min V µA Test Conditions I OH = –100 µA VIN = VCC or GND Off state output current I OZ 3.6 — ±10 µA VOUT = VCC or GND Quiescent supply current I CC 3.6 — 40 µA VIN = VCC or GND ∆I CC 3.0 to 3.6 — 750 µA VIN = one input at (VCC–0.6) V, other inputs at V CC or GND Note: 6 1. This is the bus hold maximum dynamic current required to switch the input from one state to another. HD74ALVCH162334 Switching Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Min Typ Max Unit 2.5±0.2 150 — — MHz 2.7 150 — — 3.3±0.3 150 — — t PLH 2.5±0.2 1.0 — 3.9 t PHL 2.7 — — 4.5 3.3±0.3 1.1 — 3.9 2.5±0.2 1.0 — 5.0 2.7 — — 6.0 3.3±0.3 1.3 — 5.0 2.5±0.2 1.0 — 4.9 2.7 — — 5.4 3.3±0.3 1.0 — 4.9 t ZH 2.5±0.2 1.0 — 5.4 t ZL 2.7 — — 6.4 3.3±0.3 1.1 — 5.4 t HZ 2.5±0.2 1.0 — 5.0 t LZ 2.7 — — 5.1 3.3±0.3 1.7 — 5.0 3.3 — 5.5 — 3.3 — 6.0 — 3.3 — 8.0 — Maximum clock frequency f max Propagation delay time Output enable time Output disable time Input capacitance Output capacitance CIN CO FROM (Input) TO (Output) A Y LE Y CLK Y ns OE Y ns OE Y pF Control inputs ns Data inputs pF Outputs 7 HD74ALVCH162334 Switching Characteristics (Ta = –40 to 85°C) (cont) Item Symbol VCC (V) Setup time t su Hold time Pulse width 8 th tw Min Typ Max Unit FROM (Input) 2.5±0.2 1.4 — — ns Data before CLK↑ 2.7 1.7 — — 3.3±0.3 1.5 — — 2.5±0.2 1.2 — — Data before LE↑ 2.7 1.6 — — CLK “H” 3.3±0.3 1.3 — — 2.5±0.2 1.4 — — Data before LE↑ 2.7 1.5 — — CLK “L” 3.3±0.3 1.2 — — 2.5±0.2 0.9 — — 2.7 0.8 — — 3.3±0.3 0.9 — — 2.5±0.2 1.2 — — Data after LE↑ 2.7 1.1 — — CLK “H” or “L” 3.3±0.3 1.1 — — 2.5±0.2 3.3 — — 2.7 3.3 — — 3.3±0.3 3.3 — — 2.5±0.2 3.3 — — 2.7 3.3 — — 3.3±0.3 3.3 — — ns ns Data after CLK↑ LE “L” CLK “H” or “L” HD74ALVCH162334 Test Circuit See under table 500 Ω S1 OPEN GND *1 C L = 50 pF 500 Ω Load Circuit for Outputs Symbol t PLH / t PHL t su / t h / t w t ZH/ t HZ t ZL / t LZ Note: 1. Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V OPEN OPEN GND GND 2 × VCC 6.0 V CL includes probe and jig capacitance. 9 HD74ALVCH162334 Waveforms – 1 tf tr 90 % Input VIH 90 % Vref Vref 10 % 10 % GND t PHL t PLH VOH Output Vref Vref VOL Waveforms – 2 tr VIH 90 % Vref Timing Input 10 % tsu GND th VIH Data Input Vref Vref GND tw VIH Input Vref Vref GND 10 HD74ALVCH162334 Waveforms – 3 tf tr Output Control VIH 90 % 90 % Vref Vref 10 % t ZL 10 % GND t LZ ≈VOH1 Vref Waveform - A t ZH Waveform - B Vref1 VOL t HZ VOH Vref2 Vref ≈VOL1 TEST VIH Vref Vref1 Vref2 VOH1 VOL1 Notes: 1. 2. 3. 4. Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V VCC 2.7 V 1/2 VCC 1.5 V VOL +0.15 V VOL +0.3 V VOH–0.15 V VOH–0.3 V VCC 3.0 V GND GND All input pulses are supplied by generators having the following characteristics : PRR ≤ 10 MHz, Zo = 50 Ω, t r ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V) PRR ≤ 10 MHz, Zo = 50 Ω, t r ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V) Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. The output are measured one at a time with one transition per measurement. 11 HD74ALVCH162334 Package Dimensions Unit : mm +0.3 12.50 –0.1 25 6.10 +0.3 –0.1 48 0.20 +0.1 –0.05 0.50 24 0.15 ± 0.05 1 0.08 M 12 0.05 Min 0.10 1.20 max 0.65 Max 8.10 ± 0.3 10° Max 0.50 ± 0.1 Hitachi code EIAJ code JEDEC code TTP-48DC — — Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. 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Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.