HITACHI HD74ALVCH16835

HD74ALVCH16835
18-bit Universal Bus Driver with 3-state Outputs
ADE-205-126D (Z)
5th. Edition
December 1999
Description
The HD74ALVCH16835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V CC operation. Data
flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode
when the latch enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or
low logic level. If the LE is low, the A bus data is stored in the latch/flip flop on the low to high transition
of CLK. When OE is high, the outputs are in the high impedance state. To ensure the high impedance
state during power up or power down, the output ebable (OE) input should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current sinking capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
• Supports unregulated battery operation down to 2.7 V
• Bus hold on data inputs eliminates the need for external pullup resistors.
• Distrlbuted VCC and GND pin conflguration minimizes high speed switching noise.
HD74ALVCH16835
Function Table
Inputs
OE
LE
CLK
A
Output Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
L
L
H
X
Y0 *1
L
L
L
X
Y0 *2
H:
L:
X:
Z:
↑:
Notes:
2
High level
Low level
Immaterial
High impedance
Low to high transition
1. Output level before the indicated steady-state input conditions were established, provided that
CLK was high before LE went low.
2. Output level before the indicated steady-state input conditions were established.
HD74ALVCH16835
Pin Arrangement
NC 1
56 GND
NC 2
55 NC
Y1 3
54 A1
53 GND
GND 4
Y2 5
52 A2
Y3 6
51 A3
50 VCC
VCC 7
Y4 8
49 A4
Y5 9
48 A5
Y6 10
47 A6
46 GND
GND 11
Y7 12
45 A7
Y8 13
44 A8
Y9 14
43 A9
Y10 15
42 A10
Y11 16
41 A11
Y12 17
40 A12
GND 18
39 GND
Y13 19
38 A13
Y14 20
37 A14
Y15 21
36 A15
VCC 22
35 VCC
Y16 23
34 A16
Y17 24
33 A17
GND 25
32 GND
Y18 26
31 A18
OE 27
30 CLK
LE 28
29 GND
(Top view)
3
HD74ALVCH16835
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
VCC
–0.5 to 4.6
V
VI
–0.5 to 4.6
V
VO
–0.5 to VCC+0.5
V
Input clamp current
I IK
–50
mA
VI < 0
Output clamp current
I OK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±50
mA
VO = 0 to VCC
VCC, GND current / pin
I CC or IGND
±100
mA
Maximum power dissipation
at Ta = 55°C (in still air) *3
PT
1
W
Storage temperature range
Tstg
–65 to 150
°C
Supply voltage range
Input voltage range
*1
Output voltage range
*1, 2
Conditions
TSSOP
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those indicated under “recommended operating condition” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
Notes: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. The input and output positive-voltage ratings may be exceeded up to 4.6 V if the input and output
clamp-current ratings are observed.
3. The maximum power dissipation is calculated using a junction temperature of 150°C and board
trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage
VCC
2.3
3.6
V
Input voltage
VI
0
VCC
V
Output voltage
VO
0
VCC
V
High-level output current
I OH
—
–12
mA
—
–12
VCC = 2.7 V
—
–24
VCC = 3.0 V
—
12
—
12
VCC = 2.7 V
—
24
VCC = 3.0 V
Low-level output current
I OL
mA
Input transition rise or fall rate
∆t/∆v
0
10
ns/V
Operating free-air temperature
Ta
–40
85
°C
Note: Unused or floating control pins must be held high or low.
4
Conditions
VCC = 2.3 V
VCC = 2.3 V
HD74ALVCH16835
Logic Diagram
OE
CLK
LE
A1
27
30
28
54
1D
C1
CLK
3
Y1
To 17 Other Channels
5
HD74ALVCH16835
Electrical Characteristics
Ta = –40 to 85°C
Item
Symbol VCC (V)
Min
Max
Unit Test Conditions
Input voltage
VIH
2.3 to 2.7
1.7
—
V
2.7 to 3.6
2.0
—
2.3 to 2.7
—
0.7
2.7 to 3.6
—
0.8
VIL
Output voltage
VOH
VOL
V
V
I OH = –100 µA
Min to Max VCC–0.2
—
2.3
2.0
—
I OH = –6 mA, VIH = 1.7 V
2.3
1.7
—
I OH = –12 mA, VIH = 1.7 V
2.7
2.2
—
I OH = –12 mA, VIH = 2.0 V
3.0
2.4
—
I OH = –12 mA, VIH = 2.0 V
3.0
2.0
—
I OH = –24 mA, VIH = 2.0 V
0.2
2.3
—
0.4
I OL = 6 mA, VIL = 0.7 V
2.3
—
0.7
I OL = 12 mA, VIL = 0.7 V
2.7
—
0.4
I OL = 12 mA, VIL = 0.8 V
3.0
—
0.55
I OL = 24 mA, VIL = 0.8 V
I IN
3.6
—
±5.0
µA
VIN = VCC or GND
I IN(hold)
2.3
—
—
µA
VIN = 0.7 V
2.3
–45
—
VIN = 1.7 V
3.0
75
—
VIN = 0.8 V
3.0
–75
—
VIN = 2.0 V
I OZ
3.6
—
±10
µA
VOUT = VCC or GND
Quiescent supply current I CC
3.6
—
40
µA
VIN = VCC or GND
3.0 to 3.6
—
750
µA
One input at (V CC–0.6)V,
other inputs at V CC or GND
Input current
Off state output current
∆I CC
6
V
I OL = 100 µA
Min to Max —
HD74ALVCH16835
Switching Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V)
Min
Typ
Max
Unit
Maximum clock
f max
2.5±0.2
150
—
—
MHz
2.7
150
—
—
3.3±0.3
150
—
—
t PLH
2.5±0.2
1.3
—
5.0
t PHL
2.7
—
—
4.2
3.3±0.3
1.0
—
3.6
2.5±0.2
1.8
—
5.8
2.7
—
—
4.9
3.3±0.3
1.3
—
4.2
2.5±0.2
1.9
—
5.5
2.7
—
—
5.2
3.3±0.3
1.4
—
4.5
t ZH
2.5±0.2
1.5
—
5.5
t ZL
2.7
—
—
5.6
3.3±0.3
1.1
—
4.6
t HZ
2.5±0.2
2.1
—
4.5
t LZ
2.7
—
—
4.3
3.3±0.3
1.3
—
3.9
3.3
—
3.5
—
3.3
—
6.0
—
3.3
—
7.0
—
frequency
Propagation delay time
Output enable time
Output disable time
Input capacitance
Output capacitance
CIN
CO
ns
From (Input) To (Output)
A
Y
LE
Y
CLK
Y
ns
OE
Y
ns
OE
Y
pF
Control inputs
Data inputs
pF
A or Y ports
7
HD74ALVCH16835
Switching Characteristics (Ta = –40 to 85°C) (cont)
Item
Symbol VCC (V)
Setup time
t su
Hold time
Pulse width
th
tw
Min
Typ
Max
Unit
From (Input)
2.5±0.2
2.2
—
—
ns
Data before CLK↑
2.7
2.1
—
—
3.3±0.3
1.7
—
—
2.5±0.2
1.9
—
—
Data before LE↓
2.7
1.6
—
—
CLK “H”
3.3±0.3
1.5
—
—
2.5±0.2
1.3
—
—
Data before LE↓
2.7
1.1
—
—
CLK “L”
3.3±0.3
1.0
—
—
2.5±0.2
0.6
—
—
2.7
0.6
—
—
3.3±0.3
0.7
—
—
2.5±0.2
1.4
—
—
Data after LE↓
2.7
1.7
—
—
CLK “H” or “L”
3.3±0.3
1.4
—
—
2.5±0.2
3.3
—
—
2.7
3.3
—
—
3.3±0.3
3.3
—
—
2.5±0.2
3.3
—
—
2.7
3.3
—
—
3.3±0.3
3.3
—
—
ns
Data after CLK↑
ns
LE “H”
CLK “H” or “L”
Switching Characteristics (Ta = 0 to 65°C)
Item
Symbol VCC (V)
Propagation delay time
t PLH , t PHL 3.3±0.15 1.7
8
Min
Typ
Max
Unit
FROM
(Input)
TO
(Output)
—
4.5
ns
CLK
Y
HD74ALVCH16835
Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
500 Ω
CL = 50 pF
Load Circuit for Outputs
Symbol
t PLH / t PHL
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
OPEN
OPEN
t su / t h / t w
t ZH/ t HZ
t ZL / t LZ
Note:
1.
GND
GND
4.6 V
6.0 V
CL includes probe and jig capacitance.
Waveforms – 1
VIH
Input
Vref
Vref
GND
t PHL
t PLH
VOH
Output
Vref
Vref
VOL
Waveforms – 2
9
HD74ALVCH16835
VIH
Vref
Timing Input
tsu
GND
th
VIH
Vref
Data Input
Vref
GND
tw
VIH
Vref
Input
Vref
GND
Waveforms – 3
VIH
Output
Control
Vref
Vref
t ZL
GND
t LZ
≈V OH1
Vref
Waveform - A
VOL + 0.3 V
t ZH
Waveform - B
t HZ
VOH – 0.3 V
Vref
1.
2.
3.
4.
10
VOH
≈V OL1
TEST
VIH
Vref
VOH1
VOL1
Notes:
VOL
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
2.3 V
2.7 V
1.2 V
2.3 V
1.5 V
3.0 V
GND
GND
All input pulses are supplied by generators having the following characteristics: PRR ≤
10MHz, ZO = 50 Ω, t r ≤ 2.5 ns, tf ≤ 2.5 ns.
Waveform–A is for an output with internal conditions such that the output is low except when
disabled by the output control.
Waveform–B is for an output with internal conditions such that the output is high except
when disabled by the output control.
The outputs are measured one at a time with one transition per measurement.
HD74ALVCH16835
Package Dimensions
Unit : mm
+0.3
14.00 –0.1
29
6.10 +0.3
–0.1
56
28
0.15 ± 0.05
0.08 M
0.40 Max
0.10
1.20 max
0.20 +0.1
–0.05
0.50
0.05 Min
1
8.10 ± 0.3
10° Max
0.50 ± 0.1
Hitachi code
EIAJ code
JEDEC code
TTP-56D
—
—
11
HD74ALVCH16835
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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