HD74HC674 16-bit Shift Register Description The HD74HC674 is a 16-bit parallel-in, serial-out shift register. A three-state input/output (data I/O) port provides access for entering serial data or reading the shift-register word in a recirculating loop. The device has four basic modes of operation: 1. 2. 3. 4. Hold (do nothing) Write (serially via input/output) Read (serially) Load (parallel via data inputs) Low-to-high-level changes at the chip select input should be made only when the clock input is low to prevent false clocking. Features • • • • • High Speed Operation: tpd (CLK to SER/Q15) = 17 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs CS R/W Mode CLK SER/Q15 Operation H X X X Z Do nothing L L X Z Shift and write (serial load) L H L Q14n Shift and read L H H P15 Parallel load HD74HC674 Pin Arrangement CS 1 24 VCC CLK 2 23 P15 R/W 3 22 P14 NC 4 21 P13 Mode 5 20 P12 SER/Q15 6 19 P11 P0 7 18 P10 P1 8 17 P9 P2 9 16 P8 P3 10 15 P7 P4 11 14 P6 GND 12 13 P5 (Top view) 2 HD74HC674 Logic Diagram P0 IN PE CK P Q P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 VCC P15 Mode SER/Q15 CS CLK R/W 3 HD74HC674 DC Characteristics Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Input voltage VIH 2.0 1.5 — — 1.5 — V 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — I OH = –6 mA 6.0 5.68 — — 5.63 — I OH = –7.8 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 I OL = 6 mA 6.0 — — 0.26 — 0.33 I OL = 7.8 mA VIL Output voltage VOH VOL Test Conditions V V V Vin = VIH or VIL I OH = –20 µA Vin = VIH or VIL I OL = 20 µA Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply current I CC 6.0 — — 4.0 40 µA Vin = VCC or GND, Iout = 0 µA Off-state output current I OZ 6.0 — — ±0.5 — ±5.0 µA Vin = VIH or VIL, Vout = VCC or GND 4 — HD74HC674 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Maximum clock f max 2.0 — — 5 — 4 MHz 4.5 — — 27 — 21 6.0 — — 32 — 25 Propagation delay t PLH 2.0 — — 200 — 250 time 4.5 — 17 40 — 50 6.0 — — 34 — 43 frequency t PHL Output enable t ZH 2.0 — — 150 — 190 time t ZL 4.5 — 12 30 — 38 6.0 — — 26 — 33 Output disable t HZ 2.0 — — 150 — 190 time t LZ 4.5 — 14 30 — 38 6.0 — — 26 — 33 2.0 80 — — 100 — 4.5 16 6 — 20 — 6.0 14 — — 17 — 2.0 100 — — 125 — 4.5 20 — — 25 — 6.0 17 — — 21 — 2.0 100 — — 125 — 4.5 20 — — 25 — 6.0 17 — — 21 — 2.0 100 — — 125 — 4.5 20 — — 25 — 6.0 17 — — 21 — 2.0 100 — — 125 — 4.5 20 — — 25 — 6.0 17 — — 21 — Pulse width Setup time tw t su t su t su t su ns Test Conditions Clock to SER/Q15 ns ns ns ns SER/Q15 to Clock ns P to Clock ns Mode to Clock ns R/W or CS to Clock 5 HD74HC674 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions Hold time th 2.0 5 — — 5 — ns Clock to SER/Q15 4.5 5 — — 5 — 6.0 5 — — 5 — 2.0 5 — — 5 — ns Clock to P 4.5 5 — — 5 — 6.0 5 — — 5 — 2.0 5 — — 5 — ns Clock to mode 4.5 5 — — 5 — 6.0 5 — — 5 — th th Output rise/fall t TLH 2.0 — — 60 — 75 time t THL 4.5 — 4 12 — 15 6.0 — — 10 — 13 — — 5 10 — 10 Input capacitance 6 Cin ns pF Unit: mm 13 13.4 15.0 Max 24 31.6 32.5 Max 12 1.2 15.24 0.48 ± 0.10 0.51 Min 2.54 ± 0.25 5.70 Max 2.13 Max 2.54 Min 1 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-24 Conforms Conforms 3.1 g Cautions 1. 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