HD74HC195 4-bit Parallel-Access Shift Register Description This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; shift from QA towards QD. Paralle loading is accomplished by applying the four bits of data, and taking the Shift/Load control Input low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the Shift/Load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K or toggle flip-flop as shown in the function table. Features • • • • • High Speed Operation: tpd (Clock to Q) = 13 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HC195 Function Table Inputs Shift/ Serial Parallel Outputs Clear Load Clock J K A B C D QA QB QC QD QD L X X X X X X X L L L L H H L X X a b c d a b c d d H H X X X X X X QA0 QB0 QC0 QD0 QD0 H H L H X X X X QA0 QA0 QBn QCn QCn H H L L X X X X L QAn QBn QCn QCn H H H H X X X X H QAn QBn QCn QCn H H H L X X X X QAn QAn QBn QCn QCn H : L : X : high level (steady state) low level (steady state) don’t care X L : transition from low to high level. a, b, c, d : the level of steady-state input at inputs A, B, C or D respectively. QA0, QB0, QC0, QD0 : the level of QA, QB, QC or QD respectively, before the indicated steady-state input conditions were established. QAn, QBn, QCn, QDn 2 : the level of QA, QB, QC or QD respectively before the most recent the clock. transition of HD74HC195 Pin Arrangement 16 VCC Clear 1 Serial Inputs Parallel Inputs Clear QA 15 QA K QB 14 QB A 4 A QC 13 QC B 5 B QD 12 QD C 6 C QD 11 QD D 7 D CK Shift/Load J 2 J K 3 Outputs 10 Clock 9 Shift/Load GND 8 (Top view) Timing Diagram Clock Clear Serial Inputs Shift/Load Parallel Data Inputs Outputs J K H L H L A B C D QA QB QC QD Serial Shift Clear Serial Shift Load 3 HD74HC195 Logic Diagram K D C B VCC A VCC Shift/ Load D C C Q CL CL D C C Q CL CL D C C Q CL CL D C C Q CL CL Clock Clear QD 4 QD QC QB QA J HD74HC195 DC Characteristics Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Input voltage VIH 2.0 1.5 — — 1.5 — V 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — I OH = –4 mA 6.0 5.68 — — 5.63 — I OH = –5.2 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 I OL = 4 mA 6.0 — — 0.26 — 0.33 I OL = 5.2 mA VIL Output voltage VOH VOL Test Conditions V V V Vin = VIH or VIL I OH = –20 µA Vin = VIH or VIL I OL = 20 µA Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply current I CC 6.0 — — 4.0 40 µA Vin = VCC or GND, Iout = 0 µA — 5 HD74HC195 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Maximum clock f max 2.0 — — 6 — 5 MHZ 4.5 — — 30 — 24 6.0 — — 35 — 28 Propagation delay t PHL 2.0 — — 140 — 175 time 4.5 — 13 28 — 35 6.0 — — 24 — 30 2.0 — — 140 — 175 4.5 — 13 28 — 35 6.0 — — 24 — 30 2.0 — — 150 — 190 4.5 — 15 30 — 38 6.0 — — 26 — 33 2.0 80 — — 100 — 4.5 16 7 — 20 — 6.0 14 — — 17 — 2.0 100 — — 125 — 4.5 20 6 — 25 — 6.0 17 — — 21 — 2.0 100 — — 125 — 4.5 20 13 — 25 — 6.0 17 — — 21 — 2.0 0 — — 0 — 4.5 0 –3 — 0 — 6.0 0 — — 0 — 2.0 75 — — 95 — 4.5 15 8 — 19 — 6.0 13 — — 16 — 2.0 25 — — 31 — 4.5 5 0 — 6 — 6.0 4 — — 5 — frequency t PLH t PHL Pulse width Setup time Hold time Removal time 6 tw t su th t rem ns Test Conditions Clock to Q ns ns Clear to Q ns Clock to Clear ns A, B, C, D, J, K to Clock ns Shift/Load to Clock ns Any input except Shift/Load ns Shift/Load to Clock ns Clear inactive to Clock HD74HC195 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Output rise/fall t TLH 2.0 — — 75 — 95 ns time t THL 4.5 — 5 15 — 19 6.0 — — 13 — 16 — — 5 10 — 10 Input capacitance Cin Test Conditions pF 7 Unit: mm 19.20 20.00 Max 1 7.40 Max 9 6.30 16 8 1.3 0.48 ± 0.10 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max 7.62 + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-16 Conforms Conforms 1.07 g Cautions 1. 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