HD74LVC74 Dual D-type Flip Flops with Preset and Clear ADE-205-066C(Z) Rev.3 September 1995 Description The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. Low voltage and high speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features • • • • • VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@VCC = 3.0 V to 5.5 V) HD74LVC74 Function Table Inputs Outputs PR CLR CK D Q Q L H X X H L H L X X L H *1 H *1 L L X X H H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 H H H X Q0 Q0 H H ↓ X Q0 Q0 H: L: X: ↓: ↑: Q0: Note: High level Low level Immaterial High to Low transition Low to high transition Level to Q before the indicated steady input conditions were established. 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and clear go high simultaneously. Pin Arrangement 1CLR 14 VCC 1 1D 2 CK D 13 2CLR PR CLR 1CK 3 Q Q 1PR 4 1Q 5 1Q 6 11 2CK D CK CLR PR Q Q GND 7 10 2PR 9 2Q 8 2Q (Top view) 2 12 2D HD74LVC74 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC –0.5 to 6.0 V Input diode current I IK –50 mA Input voltage VI –0.5 to 6.0 V Output diode current I OK –50 mA VO = –0.5 V 50 mA VO = VCC +0.5 V Output voltage VO –0.5 to VCC +0.5 V Output current IO ±50 mA VCC, GND current / pin I CC or IGND 100 mA Storage temperature Tstg –65 to +150 °C Conditions VI = –0.5 V Note: The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Symbol Ratings Unit Conditions Supply voltage VCC 1.5 to 5.5 V Data retention 2.0 to 5.5 V At operation VI 0 to 5.5 V PR, CLR, CK, D VO 0 to V CC V Q, Q Operating temperature Ta –40 to 85 °C Output current I OH –12 mA VCC = 2.7 V mA VCC = 3.0 V to 5.5 V mA VCC = 2.7 V mA VCC = 3.0 V to 5.5 V Input / output voltage –24 I OL 12 24 Input rise / fall time *1 t r , tf 10 *2 *2 ns/V Notes: 1. This item guarantees maximum limit when one input switches. Waveform : Refer to test circuit of switching characteristics. 2. duty cycle ≤ 50% 3 HD74LVC74 Electrical Characteristics Ta = –40 to 85°C Item Symbol VCC (V) Min Max Unit Test Conditions Input voltage VIH 2.7 to 3.6 2.0 — V 4.5 to 5.5 VCC×0.7 — V 2.7 to 3.6 — 0.8 V 4.5 to 5.5 — VCC×0.3 V 2.7 to 5.5 VCC –0.2 — V I OH = –100 µA 2.7 2.2 — V I OH = –12 mA 3.0 2.4 — V 3.0 2.0 — V 4.5 3.8 — V 2.7 to 5.5 — 0.2 V I OL = 100 µA 2.7 — 0.4 V I OL = 12 mA 3.0 — 0.55 V I OL = 24 mA 4.5 — 0.55 V 0 to 5.5 — ±5.0 µA VIN = 5.5 V or GND 5.5 — 20 µA VIN = VCC or GND 3.0 to 3.6 — 500 µA VIN = one input at (VCC –0.6)V, other inputs at V CC or GND VIL Output voltage VOH VOL Input current I IN Quiescent supply current I CC ∆I CC 4 I OH = –24 mA HD74LVC74 Switching Characteristics Ta = –40 to 85°C Item Symbol Max Unit From (Input) 150.0 — — MHz 3.3±0.3 150.0 — — MHz 5.0±0.5 150.0 — — MHz t PLH 2.7 — 6.0 9.0 ns t PHL 3.3±0.3 1.5 5.0 8.0 ns 5.0±0.5 — 4.0 6.5 ns t PLH 2.7 — 6.5 9.0 ns t PHL 3.3±0.3 1.5 5.0 8.0 ns 5.0±0.5 — 4.0 6.5 ns 2.7 4.0 — — ns 3.3±0.3 3.0 — — ns 5.0±0.5 3.0 — — ns 2.7 2.0 — — ns 3.3±0.3 2.0 — — ns 5.0±0.5 2.0 — — ns 2.7 4.0 — — ns 3.3±0.3 4.0 — — ns 5.0±0.5 4.0 — — ns 2.7 6.0 — — ns 3.3±0.3 5.0 — — ns 5.0±0.5 4.0 — — ns 2.7 3.0 — — ns 3.3±0.3 2.0 — — ns 5.0±0.5 2.0 — — ns Maximum clock frequency f max Propagation delay time Setup time Hold time Pulse width Recovery time t su th tw t rec VCC (V) Min 2.7 Typ Input capacitance CIN 2.7 — 3.0 — pF Output capacitance CO 2.7 — 15.0 — pF To (Output) CLK Q, Q PR or CLR Q, Q CK PR or CLR 5 HD74LVC74 Test Circuit VCC Pulse Generator Zout = 50 Ω Input Pulse Generator Zout = 50 Ω Notes: 6 1. 2. See Function Table Input PR D Output Q Q CL = 50 pF CK CLR CL includes probe and jig capacitance. Test is put into the each flip flops. 450 Ω 50 Ω Scope Output Q Q CL = 50 pF 450 Ω 50 Ω Scope HD74LVC74 Waveforms tf Input CLR tr 90 % Vref 10 % VIH 90 % Vref 10 % GND tw tf tr VIH 90 % Vref Input PR t rec tf tr 90 % Vref 10 % Input CK 90 % Vref 10 % t s (H) 90 % Vref 10 % Input D tr t w (H) t w (L) Vref Vref 90 % Vref 10 % 10 % tw GND t rec VIH Vref Vref GND t h (H) t s (L) t h (L) VIH 90 % Vref 10 % Vref Vref GND tf t PHL t PLH t PHL t PLH VOH Output Q Vref Vref Vref Vref VOL t PLH t PHL Vref Vref t PLH t PHL VOH Output Q Vref Vref VOL Symbol VIH Vref Notes: 1. 2. 3. VCC = 2.7 V, 3.3±0.3 V VCC = 5.0±0.5 V 2.7 V VCC 1.5 V 50%VCC t r = 2.5 ns, tf = 2.5 ns Clock pulse input waveform : PRR = 10 MHz, duty cycle 50% Data input waveform : PRR = 5 MHz, duty cycle 50% 7 Unit: mm 4.40 5.00 5.30 Max 14 8 1 7 0.65 0.20 ± 0.06 1.0 0.13 M 6.40 ± 0.20 0.10 *Dimension including the plating thickness Base material dimension *0.17 ± 0.05 0.15 ± 0.04 1.10 Max 0.83 Max 0.07 +0.03 –0.04 *0.22+0.08 –0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-14D — — 0.05 g Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. 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