HITACHI HN58C65P-25

HN58C65 Series
8192-word × 8-bit Electrically Erasable and Programmable CMOS
ROM
ADE-203-374A (Z)
Rev. 1.0
Apr. 12, 1995
Description
The Hitachi HN58C65 is a electrically erasable and programmable ROM organized as 8192-word × 8-bit. It
realizes high speed, low power consumption, and a high level of reliability, employing advanced MNOS
memory technology and CMOS process and circuitry technology. It also has a 32-byte page programming
function to make its erase and write operations faster.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Single 5 V Supply
On chip latches: address, data, CE, OE, WE
Automatic byte write: 10 ms max
Automatic page write (32 byte): 10 ms max
Fast access time: 250 ns max
Low power dissipation: 20 mW/MHz typ (Active)
2.0 mW typ (Standby)
Data polling and Ready/Busy
Data protection circuity on power on/power off
Conforms to JEDEC byte-wide standard
Reliable CMOS with MNOS cell technology
105 erase/write cycles (in page mode)
10 year data retention
Ordering Information
Type No.
Access Time
Package
HN58C65P-25
250 ns
600 mil 28 pin plastic DIP (DP-28)
HN58C65FP-25
250 ns
28 pin plastic SOP*1 (FP-28D/DA)
Note:
1. T is added to the end of the type no. for a SOP of 3.0 mm (max) thickness.
HN58C65 Series
Pin Arrangement
HN58C65P/FP Series
RDY/Busy
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
(Top View)
Pin Description
Pin Name
Function
A0 – A12
Address input
I/O1 – I/O7
Data input/output
OE
Output enable
CE
Chip enable
WE
Write enable
VCC
Power (+5 V)
VSS
Ground
NC
No connection
RDY/Busy
Ready/Busy
2
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
HN58C65 Series
Block Diagram
I/O0
VCC
I/O7
High Voltage Generator
VSS
I/O Buffer
and
Input Latch
OE
CE
Control Logic and Timing
WE
A0
Y Decoder
Y Gating
A4
Address
Buffer and
Latch
X Decoder
Memory Array
A5
A12
Data Latch
Mode Selection
Pin Mode
CE
OE
WE
RDY/Busy
I/O
Read
VIL
VIL
VIH
High-Z
Dout
Standby
VIH
X
*1
X
High-Z
High-Z
Write
VIL
VIH
VIL
High-Z to V OL
Din
Deselect
VIL
VIH
VIH
High-Z
High-Z
Write inhibit
X
X
VIH
X
VIL
X
High-Z
—
VIL
VIL
VIH
VOL
Data out (I/O7)
Data polling
Note:
1. X = Don’t care
3
RDY/Busy
HN58C65 Series
Absolute Maximum Ratings
Parameter
*1
Supply voltage
Input voltage
*1
Operating temperature range
Storage temperature range
*3
Symbol
Value
Unit
VCC
–0.6 to +7.0
V
*2
Vin
–0.5 to +7.0
V
Topr
0 to +70
°C
Tstg
–55 to +125
°C
Notes: 1. With respect to V SS
2. –3.0 V for pulse width ≤ 50 ns.
3. Including electrical characteristics and data retention.
Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
4.5
5.0
5.5
V
Input voltage
VIL
–0.3
—
0.8
V
VIH
2.2
—
VCC + 1
V
Topr
0
—
70
°C
Operating temperature
4
HN58C65 Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%)
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Input leakage current
I LI
—
—
2
µA
VCC = 5.5 V
Vin = 5.5 V
Output leakage current
I LO
—
—
2
µA
VCC = 5.5 V
Vout = 5.5/0.4 V
VCC current (Standby)
I CC1
—
—
1
mA
CE = VIH, CE = VCC
VCC current (Active)
I CC2
—
—
8
mA
Iout = 0 mA
Duty = 100%
Cycle = 1 µs at
VCC = 5.5 V
—
—
25
mA
Iout = 0 mA
Duty = 100%
Cycle = 250 ns at
VCC = 5.5 V
Input low voltage
VIL
–0.3 *1
—
0.8
V
Input high voltage
VIH
2.2
—
VCC + 1
V
Output low voltage
VOL
—
—
0.4
V
I OL = 2.1 mA
Output high voltage
VOH
2.4
—
—
V
I OH = –400 µA
Note:
1. –1.0 V for pulse width ≤ 50 ns
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter
Input capacitance
*1
Output capacitance
Note:
*1
Symbol
Min
Typ
Max
Unit
Test Conditions
Cin
—
—
6
pF
Vin = 0 V
Cout
—
—
12
pF
Vout = 0 V
1. This parameter is periodically sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%)
Test Conditions
•
•
•
•
Input pulse levels: 0.4 V to 2.4 V
Input rise and fall time: ≤ 20 ns
Output load: 1TTL gate + 100 pF
Reference levels for measuring timing: 0.8 V and 2 V
5
HN58C65 Series
Read Cycle
Parameter
Symbol
Min
Max
Unit
Test Conditions
Address to output delay
t ACC
—
250
ns
CE = OE = VIL, WE = VIH
CE to output delay
t CE
—
250
ns
OE = VIL, WE = VIH
OE to output delay
t OE
10
100
ns
CE = VIL, WE = VIH
t OH
0
—
ns
CE = OE = VIL, WE = VIH
t DF
0
90
ns
CE = VIL, WE = VIH
Address to output hold
OE, CE high to output float
Note:
*1
1. t DF is defined at which the outputs archieve the open circuit conditions and are no longer driven.
Read Timing Waveform
Address
t ACC
CE
tOH
tCE
OE
tOE
WE
tDF
High
Data Out
Data Out Valid
6
HN58C65 Series
Write Cycle
Parameter
Symbol
Min*1
Typ
Max
Unit
Address setup time
t AS
0
—
—
ns
Address hold time
t AH
150
—
—
ns
CE to write setup time (WE controlled)
t CS
0
—
—
ns
CE hold time (WE controlled)
t CH
0
—
—
ns
WE to write setup time (CE controlled)
t WS
0
—
—
ns
WE hold time (CE controlled)
t WH
0
—
—
ns
OE to write setup time
t OES
0
—
—
ns
OE hold time
t OEH
0
—
—
ns
Data setup time
t DS
100
—
—
ns
Data hold time
t DH
20
—
—
ns
WE pulse width (WE controlled)
t WP
200
—
—
ns
CE pulse width (CE controlled)
t CW
200
—
—
ns
Data latch time
t DL
100
—
—
ns
Byte lode cycle
t BLC
0.30
—
30
µs
Byte lode window
t BL
100
—
—
Test Conditions
µs
*2
Write cycle time
t WC
—
—
10
ms
Time to devce busy
t DB
120
—
—
ns
Write start time
t DW
150
—
—
ns
Notes: 1. Use this device in longer cycle than this value.
2. t WC must be longer than this value unless polling technique is used. This device automatically
completes the internal write operation within this value.
7
HN58C65 Series
Byte Write Timing Waveform (1) (WE Controlled)
t WC
Address
t CS
t AH
t CH
CE
t AS
t BL
t WP
WE
t OES
t OEH
OE
t DS
t DH
Din
t DW
RDY/Busy
t DB
High-Z
8
High-Z
HN58C65 Series
Byte Write Timing Waveform (2) (CE Controlled)
Address
t WS
t AH
t BL
t WC
t CW
CE
t WH
t AS
WE
t OES
t OEH
OE
t DS
t DH
Din
t DW
RDY/Busy
t DB
High-Z
9
High-Z
HN58C65 Series
Page Write Timing Waveform (1) (WE Controlled)
Address
A5 to A12
Address
A0 to A4
t AS
WE
t AH
t BLC
t WP
t BL
t DL
t CS
t WC
t CH
CE
t OEH
t OES
OE
t DS
Din
t DH
RDY/Busy
High-Z
t DW
t DB
High-Z
10
HN58C65 Series
Page Write Timing Waveform (2) (CE Controlled)
Address
A5 to A12
Address
A0 to A4
t AS
CE
t AH
t BLC
t CW
t BL
t DL
t WS
t WC
t WH
WE
t OEH
t OES
OE
t DS
Din
t DH
RDY/Busy
High-Z
t DW
t DB
High-Z
11
HN58C65 Series
Data Polling Timing Waveform
Address
An
An
An
CE
WE
t OES
t BL
OE
t DW
t OE
I/O7
Din X
Dout X
Dout X
t WC
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 32 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 31 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 µs of the preceding rising edge of the WE. When CE or
WE is high for 100 µs after data input, the EEPROM enters write mode automatically and the input data are
written into the EEPROM.
Data Polling
Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a
write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM
is performing a write operation.
RDY/Busy Signal
RDY/Busy signal also allows the status of the EEPROM to be determined. The RDY/Busy signal has high
impedance, except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle,
the RDY/Busy signal changes state to high impedance.
12
HN58C65 Series
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE and data is latched by the rising
edge of WE or CE.
Write/Erase Endurance and Data Retention Time
The endurance is 105 cycles in case of the page programming and 3 × 103 cycles in case of byte programming
(1% cumulative failure rate). The data retention time is more than 10 years when a device is pageprogrammed less than 104 cycles.
Data Protection
1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to progam
mode by mistake. To prevent this phenomenon, this device has a noise cancelation function that cuts
noise if its width is 20 ns or less in program mode. Be careful not to allow noise of a width of more than
20 ns on the control pins.
WE
CE
5V
0V
5V
OE
0V
20 ns max
13
HN58C65 Series
2. Data Protection at VCC On/Off
When V CC is turned on or off, noise on the control pins generated by external circuits (CPU, etc.) may act
as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional
programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable
state.
VCC
CPU
RESET
* Unprogrammable
* Unprogrammable
*The EEPROM should be kept in unprogrammable
state during VCC on/off by using CPU RESET signal.
In addition, when V CC is turned on or off, the input level of on control pins must be held as shown in the
table below.
CE
VCC
X
X
OE
X
VSS
X
WE
X
X
VCC
X: Don’t care.
VCC: Pull-up to VCC level
VSS : Pull-down to V SS level.
14
HN58C65 Series
Package Dimensions
HN58C65P series (DP-28)
Unit: mm
35.60
36.50 Max
15
13.40
14.60 Max
28
14
1.20
2.54 ± 0.25
0.51 Min
1.90 Max
0.48 ± 0.10
15.24
2.54 Min 5.70 Max
1
+ 0.11
0.25 – 0.05
0° – 15°
HN58C65FP Series (FP-28D)
Unit: mm
18.30
18.75 Max
15
2.50 Max
14
1.12 Max
0.17 – 0.07
1
+ 0.08
8.40
28
11.80 ± 0.30
1.70
+ 0.10
0.40 – 0.05
0.20 M
0.15
0.20 ± 0.10
0 – 10 °
1.27
1.00 ± 0.20
15
HN58C65 Series
HN58C65FP Series (FP-28DA)
Unit: mm
18.00
18.75 Max
15
1.27 Max
+ 0.10
0.40 – 0.05
11.80 ± 0.30
1.70
0 – 10 °
0.20 ± 0.10
1.27 ± 0.10
+ 0.08
– 0.07
14
0.17
1
3.00 Max
8.40
28
1.00 ± 0.20
16