HITACHI HN58V257AT-12

HN58V256A Series
HN58V257A Series
256k EEPROM (32-kword × 8-bit)
Ready/Busy and RES function (HN58V257A)
ADE-203-357D (Z)
Rev. 4.0
Oct. 24, 1997
Description
The Hitachi HN58V256A and HN58V257A are electrically erasable and programmable ROMs organized as
32768-word × 8-bit. They have realized high speed, low power consumption and high reliability by
employing advanced MNOS memory technology and CMOS process and circuitry technology. They also
have a 64-byte page programming function to make their write operations faster.
Features
• Single 3 V supply: 2.7 to 5.5 V
• Access time: 120 ns max
• Power dissipation:
 Active: 20 mW/MHz, (typ)
 Standby: 110 µW (max)
• On-chip latches: address, data, CE, OE, WE
• Automatic byte write: 10 ms max
• Automatic page write (64 bytes): 10 ms max
• Ready/Busy (only the HN58V257A series)
• Data polling and Toggle bit
• Data protection circuit on power on/off
• Conforms to JEDEC byte-wide standard
• Reliable CMOS with MNOS cell technology
• 105 erase/write cycles (in page mode)
• 10 years data retention
• Software data protection
• Write protection by RES pin (only the HN58V257A series)
• Industrial versions (Temperature range: – 20 to 85˚C and – 40 to 85˚C) are also available.
HN58V256A Series, HN58V257A Series
Ordering Information
Type No.
Access time
Package
HN58V256AFP-12
120 ns
400 mil 28-pin plastic SOP (FP-28D)
HN58V256AT-12
120 ns
28-pin plastic TSOP (TFP-28DB)
HN58V257AT-12
120 ns
8 × 14 mm2 32-pin plastic TSOP (TFP-32DA)
Pin Arrangement
HN58V256AFP Series
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(Top view)
HN58V256AT Series
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A3
A4
A5
A6
A7
A12
A14
VCC
WE
A13
A8
A9
A11
OE
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A3
A4
A5
A6
A7
A12
A14
RDY/Busy
VCC
RES
WE
A13
A8
A9
A11
OE
(Top view)
HN58V257AT Series
A2
A1
A0
NC
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
NC
CE
A10
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
(Top view)
2
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HN58V256A Series, HN58V257A Series
Pin Description
Pin name
Function
A0 to A14
Address input
I/O0 to I/O7
Data input/output
OE
Output enable
CE
Chip enable
WE
Write enable
VCC
Power supply
VSS
Ground
RDY/Busy*
RES*
1
1
Reset
NC
Note:
Ready busy
No connection
1. This function is supported by only the HN58V257A series.
Block Diagram
Note: 1. This function is supported by only the HN58V257A series.
I/O0
VCC
to
I/O7
RDY/Busy *1
High voltage generator
VSS
RES *1
I/O buffer
and
input latch
OE
CE
Control logic and timing
WE
RES *1
A0
Y decoder
to
Y gating
A5
Address
buffer and
latch
X decoder
Memory array
A6
to
A14
Data latch
3
HN58V256A Series, HN58V257A Series
Operation Table
Operation
CE
OE
WE
RES* 3
1
RDY/Busy* 3
I/O
High-Z
Dout
VIL
VIL
VIH
VH *
Standby
VIH
×*
×
×
High-Z
High-Z
Write
VIL
VIH
VIL
VH
High-Z to V OL
Din
Deselect
VIL
VIH
VIH
VH
High-Z
High-Z
Write inhibit
×
×
VIH
×
—
—
×
VIL
×
×
—
—
Data polling
VIL
VIL
VIH
VH
VOL
Data out (I/O7)
Program reset
×
×
×
VIL
High-Z
High-Z
Read
2
Notes: 1. Refer to the recommended DC operating condition.
2. ×: Don’t care
3. This function is supported by only the HN58V267A series.
Absolute Maximum Ratings
Parameter
Symbol
Value
Supply voltage relative to VSS
VCC
–0.6 to +7.0
Vin
1
–0.5* to +7.0*
Topr
0 to +70
°C
Tstg
–55 to +125
°C
Input voltage relative to V SS
Operating temperature range*
Storage temperature range
2
Notes: 1. Vin min = –3.0 V for pulse width ≤ 50 ns
2. Including electrical characteristics and data retention
3. Should not exceed VCC + 1.0 V.
4
Unit
V
3
V
HN58V256A Series, HN58V257A Series
Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
2.7
3.0
5.5
V
VSS
0
0
0
V
—
0.6
Input voltage
1
VIL
–0.3*
VIH
VH *
Operating temperature
Notes: 1.
2.
3.
4.
4
Topr
V
2
3
1.9*
—
VCC + 0.3* V
VCC – 0.5
—
VCC + 1.0
V
0
—
70
°C
VIL min: –1.0 V for pulse width ≤ 50 ns.
VIH min for VCC = 3.6 to 5.5 V is 2.4 V.
VIH max: VCC + 1.0 V for pulse width ≤ 50 ns.
This function is supported by only the HN58V257A series.
DC Characteristics (Ta = 0 to +70°C, VCC = 2.7 to 5.5 V)
Parameter
Symbol
Min
Typ
Max
1
Unit
Test conditions
µA
VCC = 5.5 V, Vin = 5.5 V
Input leakage current
I LI
—
—
2*
Output leakage current
I LO
—
—
2
µA
VCC = 5.5 V, Vout = 5.5/0.4 V
Standby V CC current
I CC1
—
—
20
µA
CE = VCC
I CC2
—
—
1
mA
CE = VIH
I CC3
—
—
8
mA
Iout = 0 mA, Duty = 100%,
Cycle = 1 µs at VCC = 3.6 V
—
—
12
mA
Iout = 0 mA, Duty = 100%,
Cycle = 1 ns at VCC = 5.5 V
—
—
12
mA
Iout = 0 mA, Duty = 100%,
Cycle = 120 µs at VCC = 3.6 V
—
—
30
mA
Iout = 0 mA, Duty = 100%,
Cycle = 120 ns at VCC = 5.5 V
Operating VCC current
Output low voltage
VOL
—
—
0.4
V
I OL = 2.1 mA
Output high voltage
VOH
VCC × 0.8
—
—
V
I OH = –400 µA
Note:
1. I LI on RES = 100 µA max (only the HN58V257A series)
5
HN58V256A Series, HN58V257A Series
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter
1
Input capacitance*
1
Output capacitance*
Note:
Symbol
Min
Typ
Max
Unit
Test conditions
Cin
—
—
6
pF
Vin = 0 V
Cout
—
—
12
pF
Vout = 0 V
1. This parameter is periodically sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70°C, VCC = 2.7 to 5.5 V)
Test Conditions
• Input pulse levels: 0.4 V to 2.4 V (VCC 3.6V), 0.4V to 3.0 V (VCC > 3.6 V)
0 V to VCC (RES pin*2)
• Input rise and fall time: ≤ 5 ns
• Input timing reference levels: 0.8, 1.8 V
• Output load: 1TTL Gate +100 pF
• Output reference levels: 1.5 V, 1.5 V
Read Cycle
HN58V256A/HN58V257A
-12
Parameter
Symbol
Min
Max
Unit
Test conditions
Address to output delay
t ACC
—
120
ns
CE = OE = VIL, WE = VIH
CE to output delay
t CE
—
120
ns
OE = VIL, WE = VIH
OE to output delay
t OE
10
60
ns
CE = VIL, WE = VIH
t OH
0
—
ns
CE = OE = VIL, WE = VIH
t DF
0
40
ns
CE = VIL, WE = VIH
t DFR
0
350
ns
CE = OE = VIL, WE = VIH
t RR
0
600
ns
CE = OE = VIL, WE = VIH
Address to output hold
OE (CE) high to output float*
RES low to output float*
2
RES to output delay*
6
1, 2
1
HN58V256A Series, HN58V257A Series
Write Cycle
Parameter
Symbol
Min*3
Typ
Max
Unit
Address setup time
t AS
0
—
—
ns
Address hold time
t AH
50
—
—
ns
CE to write setup time (WE controlled)
t CS
0
—
—
ns
CE hold time (WE controlled)
t CH
0
—
—
ns
WE to write setup time (CE controlled)
t WS
0
—
—
ns
WE hold time (CE controlled)
t WH
0
—
—
ns
OE to write setup time
t OES
0
—
—
ns
OE hold time
t OEH
0
—
—
ns
Data setup time
t DS
70
—
—
ns
Data hold time
t DH
0
—
—
ns
WE pulse width (WE controlled)
t WP
200
—
—
ns
CE pulse width (CE controlled)
t CW
200
—
—
ns
Data latch time
t DL
100
—
—
ns
Byte load cycle
t BLC
0.3
—
30
µs
Byte load window
t BL
100
—
—
µs
4
Write cycle time
t WC
—
—
10*
Time to device busy
t DB
120
—
—
ns
—
—
ns
Write start time
Reset protect time*
2, 6
Reset high time*
2
5
Test conditions
ms
t DW
0*
t RP
100
—
—
µs
t RES
1
—
—
µs
Notes: 1. t DF and t DFR are defined as the time at which the outputs achieve the open circuit conditions and are
no longer driven.
2. This function is supported by only the HN58V257A series.
3. Use this device in longer cycle than this value.
4. t WC must be longer than this value unless polling techniques or RDY/Busy (only the HN58V257A
series) are used. This device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after t DW if polling techniques or RDY/Busy (only the
HN58V257A series) are used.
6. This parameter is sampled and not 100% tested.
7. A6 through A14 are page addresses and these addresses are latched at the first falling edge of
WE.
8. A6 through A14 are page addresses and these addresses are latched at the first falling edge of
CE.
9. See AC read characteristics.
7
HN58V256A Series, HN58V257A Series
Read Timing Waveform
Address
tACC
CE
tOH
tCE
OE
tDF
tOE
WE
High
Data Out
Data out valid
tRR
tDFR
RES *2
8
HN58V256A Series, HN58V257A Series
Byte Write Timing Waveform (1) (WE Controlled)
tWC
Address
tCS
tAH
tCH
CE
tAS
tBL
tWP
WE
tOES
tOEH
OE
tDS
tDH
Din
tDW
High-Z
RDY/Busy *2
tDB
High-Z
tRP
tRES
RES *2
VCC
9
HN58V256A Series, HN58V257A Series
Byte Write Timing Waveform (2) (CE Controlled)
Address
tWS
tAH
tBL
tWC
tCW
CE
tAS
tWH
WE
tOES
tOEH
OE
tDS
tDH
Din
tDW
RDY/Busy
*2
tDB
High-Z
tRP
tRES
RES *2
VCC
10
High-Z
HN58V256A Series, HN58V257A Series
Page Write Timing Waveform (1) (WE Controlled)
*7
Address
A0 to A14
tAS
tAH
tBL
tWP
WE
tDL
tCS
tBLC
tWC
tCH
CE
tOEH
tOES
OE
tDH
tDS
Din
RDY/Busy *2
High-Z
tDB
tDW
High-Z
tRP
RES *2
tRES
VCC
11
HN58V256A Series, HN58V257A Series
Page Write Timing Waveform (2) (CE Controlled)
*8
Address
A0 to A14
tAS
CE
tAH
tBL
tCW
tDL
tWS
tBLC
tWC
tWH
WE
tOEH
tOES
OE
tDH
tDS
Din
RDY/Busy *2
High-Z
tRP
RES *2
VCC
12
tRES
tDB
tDW
High-Z
HN58V256A Series, HN58V257A Series
Data Polling Timing Waveform
Address
An
An
An
CE
WE
tOEH
tCE *9
tOES
OE
tDW
tOE*9
I/O7
Din X
Dout X
Dout X
tWC
13
HN58V256A Series, HN58V257A Series
Toggle bit
This device provide another function to determine the internal programming cycle. If the EEPROM is set to
read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read.
When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible
for next read or program.
Toggle bit Waveform
Notes: 1.
2.
3.
4.
I/O6 beginning state is “1”.
I/O6 ending state will vary.
See AC read characteristics.
Any address location can be used, but the address must be fixed.
Next mode
*4
Address
tCE *3
CE
WE
*3
tOE
OE
tOES
tOEH
*1
I/O6
Din
Dout
Dout
tWC
14
*2
*2
Dout
Dout
tDW
HN58V256A Series, HN58V257A Series
Software Data Protection Timing Waveform (1) (in protection mode)
VCC
CE
WE
tBLC
Address
Data
5555
AA
2AAA
55
5555
A0
tWC
Write address
Write data
Software Data Protection Timing Waveform (2) (in non-protection mode)
VCC
tWC
Normal active
mode
CE
WE
Address
Data
5555 2AAA 5555 5555 2AAA 5555
AA
55
80
AA 55
20
15
HN58V256A Series, HN58V257A Series
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When
CE or WE is high for 100 µs after data input, the EEPROM enters write mode automatically and the input
data are written into the EEPROM.
Data Polling
Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode
during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is
performing a write operation.
RDY/Busy Signal (only the HN58V257A series)
RDY/Busy signal also allows the status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to V OL after the first write signal. At the end of a write cycle,
the RDY/Busy signal changes state to high impedance.
RES Signal (only the HN58V257A series)
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping
RES low when VCC is switched. RES should be high during read and programming because it doesn't provide
a latch function.
VCC
Read inhibit
Read inhibit
RES
Program inhibit
16
Program inhibit
HN58V256A Series, HN58V257A Series
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising
edge of WE or CE.
Write/Erase Endurance and Data Retention Time
The endurance is 10 5 cycles in case of the page programming and 104 cycles in case of the byte programming
(1% cumulative failure rate). The data retention time is more than 10 years when a device is pageprogrammed less than 104 cycles.
Data Protection
1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake.
To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns
or less.
Be careful not to allow noise of a width of more than 20 ns on the control pins.
WE
CE
VIH
0V
VIH
OE
0V
20 ns max
17
HN58V256A Series, HN58V257A Series
2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a
trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the
EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state.
Note: The EPROM should be kept in unprogrammable state during V CC on/off by using CPU RESET signal.
VCC
CPU
RESET
* Unprogrammable
* Unprogrammable
(1) Protection by CE, OE, WE
To realize the unprogrammable state, the input level of control pins must be held as shown in the table below.
CE
VCC
×
×
OE
×
VSS
×
WE
×
×
VCC
×: Don’t care.
VCC: Pull-up to VCC level.
VSS : Pull-down to V SS level.
18
HN58V256A Series, HN58V257A Series
(2) Protection by RES (only the HN58V257A series)
The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the EEPROM’s
RES pin. RES should be kept VSS level during VCC on/off.
The EEPROM breaks off programming operation when RES becomes low, programming operation doesn’t
finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms
after the last data input.
VCC
RES
Program inhibit
WE
or CE
1 µs min 100 µs min
Program inhibit
10 ms min
19
HN58V256A Series, HN58V257A Series
3. Software data protection
To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is
enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is
input. To program data in the SDP enable mode, 3 bytes code must be input before write data.
Address
Data
5555
AA
↓
↓
2AAA
55
↓
↓
5555
A0
↓
↓
Write address Write data } Normal data input
The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP
disable cycle, data can not be written.
Address
Data
5555
↓
2AAA
↓
5555
↓
5555
↓
2AAA
↓
5555
AA
↓
55
↓
80
↓
AA
↓
55
↓
20
The software data protection is not enabled at the shipment.
Note: There are some differences between Hitachi’s and other company’s for enable/disable sequence of
software data protection. If there are any questions , please contact with Hitachi sales offices.
20
HN58V256A Series, HN58V257A Series
Package Dimensions
HN58V256AFP Series (FP-28D)
Unit: mm
18.3
18.8 Max
15
14
1.12 Max
0.17 ± 0.05
0.15 ± 0.04
1
2.50 Max
8.4
28
11.8 ± 0.3
1.7
1.27
0.15
0.40 ± 0.08
0.38 ± 0.06
0.20 M
Dimension including the plating thickness
Base material dimension
0.20 ± 0.10
0° – 8°
1.0 ± 0.2
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-28D
Conforms
—
0.7 g
21
HN58V256A Series, HN58V257A Series
Package Dimensions (cont.)
HN58V256AT Series (TFP-28DB)
Unit: mm
8.00
8.20 Max
15
1
14
11.80
28
0.55
0.22 ± 0.08
0.10 M
0.20 ± 0.06
0.45 Max
0.80
13.40 ± 0.30
Dimension including the plating thickness
Base material dimension
22
+0.07
0.13 –0.08
0.10
0.17 ± 0.05
0.15 ± 0.04
1.20 Max
0° – 5°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TFP-28DB
—
—
0.23 g
HN58V256A Series, HN58V257A Series
Package Dimensions (cont.)
HN58V257AT Series (TFP-32DA)
Unit: mm
8.00
8.20 Max
17
1
16
12.40
32
0.50
0.08 M
Dimension including the plating thickness
Base material dimension
0.17 ± 0.05
0.125 ± 0.04
1.20 Max
0.10
0.80
14.00 ± 0.20
0.45 Max
0.13 ± 0.05
0.22 ± 0.08
0.20 ± 0.06
0° – 5°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
0.50 ± 0.10
TFP-32DA
Conforms
Conforms
0.26 g
23
HN58V256A Series, HN58V257A Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other
reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such
use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested
to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
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Semiconductor & IC Div.
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Brisbane, CA. 94005-1835
USA
Tel: 415-589-8300
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München
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United Kingdom
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World Finance Centre,
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Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
24