CD74FCT823A, CD74FCT824A Data sheet acquired from Harris Semiconductor SCHS265 BiCMOS FCT Interface Logic, 9-Bit D-Type Flip-Flops, Three-State D ENDE M M ECO IGNS NOT R NEW DES ology Techn FOR January 1997 MOS Features Use C • Buffered Inputs • Typical Propagation Delay: 7.5ns at VCC = 5V, TA = 25oC, CL = 50pF • Positive Edge Triggered • CD74FCT824A - Inverting • • • • • • Circuit Design Speed of Bipolar FAST™/AS/S 48mA Output Sink Current Output Voltage Swing Limited to 3.7V at VCC = 5V Controlled Output Edge Rates Input/Output Isolation to VCC BiCMOS Technology with Low Quiescent Power Ordering Information • CD74FCT823A - Noninverting PART NUMBER • SCR Latchup Resistant BiCMOS Process and TEMP. RANGE (oC) PKG. NO. PACKAGE CD74FCT823AEN 0 to 70 24 Ld PDIP E24.3 CD74FCT824AEN 0 to 70 24 Ld PDIP E24.3 Pinout CD74FCT823A (PDIP) TOP VIEW CD74FCT824A (PDIP) TOP VIEW OE 1 24 VCC OE 1 24 VCC D0 2 23 Q0 D0 2 23 Q0 D1 3 22 Q1 D1 3 22 Q1 D2 4 21 Q2 D2 4 21 Q2 D3 5 20 Q3 D3 5 20 Q3 D4 6 19 Q4 D4 6 19 Q4 D5 7 18 Q5 D5 7 18 Q5 D6 8 17 Q6 D6 8 17 Q6 D7 9 16 Q7 D7 9 16 Q7 D8 10 15 Q8 D8 10 15 Q8 MR 11 14 CE MR 11 14 CE GND 12 13 CP GND 12 13 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a trademark of Fairchild Semiconductor. Copyright © Harris Corporation 1997 8-1 File Number 2389.2 CD74FCT823A, CD74FCT824A Functional Diagram D0 D1 D2 D3 D4 D5 D6 D7 D8 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 14 CE OE 11 13 1 823A 824A Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 CP MR GND = PIN 12 VCC = PIN 24 TRUTH TABLE (Note 1) INPUTS Q OUTPUTS OE MR CE D CP CD74FCT823A CD74FCT824A H H X X L L L H ↑ ↑ Z Z Z Z High Z FUNCTION H L L L X X X X X X Z L Z L Reset H L H H H H X X X X Z NC Z NC Hold H H L L H H H H L L L L L H L H ↑ ↑ ↑ ↑ Z Z L H Z Z H L Load NOTE: 1. H= HIGH Voltage Level L = LOW Voltage Level NC = No Change ↑ = LOW to HIGH Transition X = Don’t Care Z = HIGH Impedance IEC Logic Symbol CD74FCT823A 1 11 14 13 2 CD74FCT824A 1 11 14 13 EN R G1 >1C2 EN R G1 >1C2 23 2 3 22 3 22 4 21 4 21 5 20 5 20 6 19 6 19 7 18 7 18 8 17 8 17 9 16 9 16 10 15 10 15 2D 8-2 2D 23 CD74FCT823A, CD74FCT824A Absolute Maximum Ratings Thermal Information DC Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Diode Current, IIK (For VI < -0.5V) . . . . . . . . . . . . . . . . . . -20mA DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . . 70mA DC Output Source Current per Output Pin, IO . . . . . . . . . . . . -30mA DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234mA DC Ground Current (IGND). . . . . . . . . . . . . . . . . . . . . . . . . . . 453mA Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Operating Temperature Range, TA . . . . . . . . . . . . . . . . .0oC to 70oC Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V DC Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC DC Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ VCC Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Commercial Temperature Range 0oC to 70oC, VCC Max = 5.25V, VCC Min = 4.75V AMBIENT TEMPERATURE (TA) 25oC TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN 0oC TO 70oC MAX MIN MAX UNITS High Level Input Voltage VIH 4.75 to 5.25 2 - 2 - V Low Level Input Voltage VIL 4.75 to 5.25 - 0.8 - 0.8 V High Level Output Voltage VOH VIH or VIL -15 Min 2.4 - 2.4 - V Low Level Output Voltage VOL VIH or VIL 48 Min - 0.55 - 0.55 V High Level Input Current IIH VCC Max - 0.1 - 1 µA Low Level Input Current IIL GND Max - -0.1 - -1 µA IOZH VCC Max - 0.5 - 10 µA IOZL GND Max - -0.5 - -10 µA Input Clamp Voltage VIK VCC or GND Min - -1.2 - -1.2 V Short Circuit Output Current (Note 3) IOS VO = 0 VCC or GND Max -75 - -75 - mA Quiescent Supply Current, MSI ICC VCC or GND Max - 8 - 80 µA ∆ICC 3.4V (Note 4) Max - 1.6 - 1.6 mA Three-State Leakage Current Additional Quiescent Supply Current per Input Pin TTL Inputs High, 1 Unit Load -18 0 NOTES: 3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms. 4. Inputs that are not measured are at VCC or GND. 5. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICC limit specified in Electrical Specifications table, e.g., 1.6mA Max. at 70oC. 8-3 CD74FCT823A, CD74FCT824A Switching Specifications Over Operating Range FCT Series tr, tf = 2.5ns, CL = 50pF, RL (Figure 1) PARAMETER SYMBOL Propagation Delays VCC (V) 25oC 0oC TO 70oC TYP MIN MAX UNITS (Note 6) Clock to Q CD74FCT823A tPLH, tPHL 5 7.5 1.5 10 ns Clock to Q CD74FCT824A tPLH, tPHL 5 7.5 1.5 10 ns tPHL 5 10.5 1.5 14 ns MR to Q Output Enable to Q CD74FCT823A tPZL, tPZH 5 9 1.5 12 ns Output Disable to Q CD74FCT823A tPLZ, tPHZ 5 6 1.5 8 ns Output Enable to Q CD74FCT824A tPZL, tPZH 5 9 1.5 12 ns Output Disable to Q CD74FCT824A tPLZ, tPHZ 5 6 1.5 8 ns CPD (Note 7) - - - - pF Minimum (Valley) VOHV During Switching of Other Outputs (Output Under Test Not Switching) VOHV 5 0.5 - - V Maximum (Peak) VOLP During Switching of Other Outputs (Output Under Test Not Switching) VOLP 5 1 - - V Input Capacitance CI - - - 10 pF Three-State Output Capacitance CO - - - 15 pF Power Dissipation Capacitance NOTES: 6. 5V: Minimum is at 5.25V for 0oC to 70oC, Maximum is at 4.75V for 0oC to 70oC, Typical is at 5V. 7. CPD, measured per flip-flop, is used to determine the dynamic power consumption. PD (per package) = VCC ICC + Σ(VCC2 fI CPD + VO2 fOCL + VCC ∆ICC D) where: VCC = supply voltage ∆ICC = flow through current x unit load CL = output load capacitance D = duty cycle of input high fO = output frequency fI = input frequency Prerequisite for Switching 25oC PARAMETER 0oC TO 70oC SYMBOL VCC (V) TYP MIN MAX UNITS Maximum Clock Frequency fMAX 5 (Note 8) - 70 - MHz Master Reset Recovery Time tREC 5 - 7 - ns Setup Time, Data to Clock, CE to Clock tSU 5 - 4 - ns Hold Time - Data, CE tH 5 - 2 - ns Pulse Width - Clock, MR tW 5 - 7 - ns NOTE: 8. 5V: Minimum is at 4.75V for 0oC to 70oC, Typical is at 5V. 8-4 CD74FCT823A, CD74FCT824A Test Circuits and Waveforms VCC tr, tf = 2.5ns (NOTE 9) VI 3V 0 PULSE ZO GEN SWITCH POSITION 7V 500Ω RL V0 DUT CL 50pF RT RT = ZO 500Ω RL 9. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZOUT ≤ 50Ω; tf, tr ≤ 2.5ns. FIGURE 1. TEST CIRCUIT tPLZ, tPZL, Open Drain Closed tPHZ, tPZH, tPLH, tPHL Open 3V 1.5V 0V DATA INPUT tH 3V 1.5V 0V TIMING INPUT tREM ASYNCHRONOUS CONTROL SWITCH DEFINITIONS: CL = Load capacitance, includes jig and probe capacitance. RT = Termination resistance, should be equal to ZOUT of the Pulse Generator. VIN = 0V to 3V. Input: tr = tf = 2.5ns (10% to 90%), unless otherwise specified NOTE: tSH TEST 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. 3V 1.5V 0V tH tSH HIGH-LOW-HIGH PULSE FIGURE 2. SETUP, HOLD, AND RELEASE TIMING ENABLE 1.5V FIGURE 3. PULSE WIDTH DISABLE 3V 3V SAME PHASE INPUT TRANSITION 1.5V CONTROL INPUT 0V 3.5V OUTPUT NORMALLY LOW SWITCH CLOSED SWITCH OPEN tPHL 3.5V VOH 1.5V 1.5V VOL OUTPUT 0.3V tPZH OUTPUT NORMALLY HIGH tPLH tPLZ tPZL 1.5V tPHZ 0.3V VOL tPLH tPHL VOH 3V OPPOSITE PHASE INPUT TRANSITION 1.5V 0V 0V 0V 1.5V 0V FIGURE 4. ENABLE AND DISABLE TIMING FIGURE 5. PROPAGATION DELAY 8-5 Test Circuits and Waveforms (Continued) VOH OTHER OUTPUTS VOL VOH OUTPUT UNDER TEST VOHV VOLP VOL NOTES: 10. VOLP is measured with respect to a ground reference near the output under test. VOHV is measured with respect to VOH. 11. Input pulses have the following characteristics: PRR ≤ 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns. 12. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and probes require 700MHz bandwidth. FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS 8-6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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