TI CD74AC174E

[ /Title
(CD74
AC174
,
CD74
ACT17
4
)
/Subject
(Hex D
FlipFlop
with
Reset)
/Autho
r ()
/Keywords
(Harris
Semiconductor,
Advan
ced
CMOS
, Harris
Semiconductor,
Advan
ced
TTL)
/Creator ()
/DOCI
NFO
CD74AC174,
CD54/74ACT174
Data sheet acquired from Harris Semiconductor
SCHS241A
Hex D Flip-Flop with Reset
September 1998 - Revised May 2000
Features
Description
• Buffered Inputs
The CD74AC174 and ’ACT174 are hex D flip-flops with reset
that utilize Advanced CMOS Logic technology. Information at
the D input is transferred to the Q output on the positivegoing edge of the clock pulse. All six flip-flops are controlled
by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of
the clock.
• Typical Propagation Delay
- 6.4ns at VCC = 5V, TA = 25oC, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
Ordering Information
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
PART
NUMBER
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
TEMP.
RANGE (oC)
PACKAGE
CD74AC174E
-55 to 125
16 Ld PDIP
CD74AC174M
-55 to 125
16 Ld SOIC
CD54ACT174F3A
-55 to 125
16 Ld CERDIP
CD74ACT174E
-55 to 125
16 Ld PDIP
CD74ACT174M
-55 to 125
16 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information.
Pinout
CD54ACT174
(CERDIP)
CD74AC174, CD74ACT174
(PDIP, SOIC)
TOP VIEW
MR 1
16 VCC
Q0 2
15 Q5
D0 3
14 D5
D1 4
13 D4
Q1 5
12 Q4
D2 6
11 D3
Q2 7
10 Q3
GND 8
9 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © 2000, Texas Instruments Incorporated
1
CD74AC174, CD54/74ACT174
Functional Diagram
9
CP
CP
D
R
3
D0
2
Q0
4
5
Q1
D1
7
6
Q2
D2
11
10
Q3
D3
13
12
D4
Q4
14
15
D5
Q5
1
MR
GND = 8
VCC = 16
TRUTH TABLE (EACH FLIP-FLOP)
INPUTS
OUTPUTS
RESET
(MR)
CLOCK
CP
DATA
Dn
Qn
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q0
H = High Level (Steady State)
L = Low Level (Steady State)
X = Irrelevant
↑ = Transition from Low to High level
Q0 = Level before the Indicated Steady-State Input conditions
were established.
2
CD74AC174, CD54/74ACT174
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Thermal Resistance (Typical, Note 5)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature (Plastic Package) . . . . . . . . . 1505oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VIH
-
-
1.5
1.2
-
1.2
-
1.2
-
V
AC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VIL
VOH
-
VIH or VIL
3
2.1
-
2.1
-
2.1
-
V
5.5
3.85
-
3.85
-
3.85
-
V
1.5
-
0.3
-
0.3
-
0.3
V
3
-
0.9
-
0.9
-
0.9
V
5.5
-
1.65
-
1.65
-
1.65
V
-0.05
1.5
1.4
-
1.4
-
1.4
-
V
-0.05
3
2.9
-
2.9
-
2.9
-
V
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-4
3
2.58
-
2.48
-
2.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
-
3
CD74AC174, CD54/74ACT174
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Low Level Output Voltage
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VOL
VIH or VIL
0.05
1.5
-
0.1
-
0.1
-
0.1
V
0.05
3
-
0.1
-
0.1
-
0.1
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
12
3
-
0.36
-
0.44
-
0.5
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
High Level Input Voltage
VIH
-
-
4.5 to
5.5
2
-
2
-
2
-
V
Low Level Input Voltage
VIL
-
-
4.5 to
5.5
-
0.8
-
0.8
-
0.8
V
High Level Output Voltage
VOH
VIH or VIL
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
Input Leakage Current
Quiescent Supply Current
MSI
ACT TYPES
Low Level Output Voltage
Input Leakage Current
Quiescent Supply Current
MSI
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
VOL
VIH or VIL
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
2.4
-
2.8
-
3
mA
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.
ACT Input Load Table
INPUT
UNIT LOAD
Dn, MR
0.5
CP
0.83
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
4
CD74AC174, CD54/74ACT174
Prerequisite For Switching Function
PARAMETER
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
UNITS
tSU
1.5
2
-
2
-
ns
3.3
(Note 9)
2
-
2
-
ns
5
(Note 10)
2
-
2
-
ns
1.5
33
-
38
-
ns
3.3
3.7
-
4.2
-
ns
5
2.6
-
3
-
ns
1.5
1.5
-
1.5
-
ns
3.3
1.5
-
1.5
-
ns
5
1.5
-
1.5
-
ns
1.5
44
-
50
-
ns
3.3
4.9
-
5.6
-
ns
5
3.5
-
4
-
ns
1.5
57
-
65
-
ns
3.3
6.4
-
7.3
-
ns
5
4.6
-
5.2
-
ns
1.5
9
-
8
-
MHz
3.3
77
-
68
-
MHz
5
108
-
95
-
MHz
AC TYPES
Data to CP Set-Up Time
Hold Time
tH
Removal Time, MR to CP
tREM
MR Pulse Width
tW
CP Pulse Width
tW
CP Frequency
fMAX
ACT TYPES
Data to CP Set-Up Time
tSU
5
(Note 10)
2
-
2
-
ns
Hold Time
tH
5
2.2
-
2.5
-
ns
tREM
5
1.5
-
1.5
-
ns
MR Pulse Width
tW
5
3.5
-
4
-
ns
Clock Pulse Width
tW
5
5.4
-
6.2
-
ns
fMAX
5
91
-
80
-
MHz
Removal Time, MR to CP
CP Frequency
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
-40oC TO 85oC
PARAMETER
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPLH, tPHL
1.5
-
-
154
-
-
169
ns
3.3
(Note 9)
4.9
-
17.2
4.7
-
18.9
ns
5
(Note 10)
3.5
-
12.3
3.4
-
13.5
ns
AC TYPES
Propagation Delay, CP to Qn
5
CD74AC174, CD54/74ACT174
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
(Continued)
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPLH, tPHL
1.5
-
-
165
-
-
181
ns
3.3
5.2
-
18.5
5.1
-
20.3
ns
5
3.7
-
13.2
3.6
-
14.5
ns
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
37
-
-
37
-
pF
Propagation Delay, CP to Qn
tPLH, tPHL
5
(Note 10)
3.6
-
12.6
3.5
-
14
ns
Propagation Delay, MR to Qn
tPLH, tPHL
5
4
-
14.1
3.9
-
15.5
ns
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
37
-
-
37
-
pF
PARAMETER
Propagation Delay, MR to Qn
Input Capacitance
Power Dissipation Capacitance
ACT TYPES
Input Capacitance
Power Dissipation Capacitance
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. CPD is used to determine the dynamic power consumption per flip-flop.
PD = CPD VCC2 fi + Σ (CL + VCC2 fo) + VCC ∆ICC where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC =
supply voltage.
INPUT LEVEL
INPUT LEVEL
CP
VS
GND
VS
VS
tW
tPLH
tPHL
INPUT LEVEL
VS
VS
D
VS
VS
GND
VS
tH(L)
tSU(L)
CP
VS
tH(H)
tSU(H)
VS
VS
GND
FIGURE 1. PROPAGATION DELAYS
FIGURE 3.
OUTPUT
INPUT LEVEL
MR
RL (NOTE)
500Ω
VS
VS
GND
CP
(Q)
DUT
tREM
tW
INPUT
OUTPUT
LOAD
VS
CL
50pF
tPHL
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
Q
VS
AC
ACT
VCC
3V
Input Switching Voltage, VS
0.5 VCC
1.5V
Output Switching Voltage, VS
0.5 VCC
0.5 VCC
Input Level
FIGURE 2. RESET OR SET PREREQUISITE AND
PROPAGATION DELAYS
FIGURE 4. PROPAGATION DELAY TIMES
6
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Copyright  2000, Texas Instruments Incorporated