SCLS414N − APRIL 1998 − REVISED APRIL 2005
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
QA
SER
OE
RCLK
SRCLK
SRCLR
QH′
QC
QD
QE
QF
QG
QH
15
2
3
14
4
13
5
12
6
11
7
10
8
9
QD
QE
NC
QF
QG
QA
SER
OE
RCLK
SRCLK
SRCLR
NC
VCC
QA
16
QC
QB
1
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
SER
OE
NC
RCLK
SRCLK
SRCLR
1
SN54LV595A . . . FK PACKAGE
(TOP VIEW)
QH
QB
QC
QD
QE
QF
QG
QH
GND
VCC
SN74LV595A . . . RGY PACKAGE
(TOP VIEW)
SN54LV595A . . . J OR W PACKAGE
SN74LV595A . . . D, DB, NS,
OR PW PACKAGE
(TOP VIEW)
QH′
D
D
QB
D
Operation
Shift Register Has Direct Clear
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
D
D
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
8-Bit Serial-In, Parallel-Out Shift
GND
D
D Ioff Supports Partial-Power-Down Mode
GND
NC
QH ′
D 2-V to 5.5-V VCC Operation
D Max tpd of 7.1 ns at 5 V
D Typical VOLP (Output Ground Bounce)
NC − No internal connection
description/ordering information
The ’LV595A devices are 8-bit shift registers designed for 2-V to 5.5-V VCC operation.
ORDERING INFORMATION
QFN − RGY
SN74LV595ARGYR
Tube of 40
SN74LV595AD
Reel of 2500
SN74LV595ADR
SOP − NS
Reel of 2000
SN74LV595ANSR
74LV595A
SSOP − DB
Reel of 2000
SN74LV595ADBR
LV595A
Tube of 90
SN74LV595APW
Reel of 2000
SN74LV595APWR
Reel of 250
SN74LV595APWT
CDIP − J
Tube of 25
SNJ54LV595AJ
SNJ54LV595AJ
CFP − W
Tube of 150
SNJ54LV595AW
SNJ54LV595AW
LCCC − FK
Tube of 55
SNJ54LV595AFK
TSSOP − PW
−55°C
−55
C to 125
125°C
C
TOP-SIDE
MARKING
Reel of 1000
SOIC − D
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
LV595A
LV595A
LV595A
SNJ54LV595AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
!"#$%& "!&'& (
&)!*$'!& "#**%& ' !) +#,-"'!& '%. *!#" "!&)!*$ !
+%")"'!& +%* % %*$ !) %/' &*#$%& '&'* 0'**'&1.
*!#"!& +*!"%&2 !% &! &%"%'*-1 &"-#% %&2 !) '-+'*'$%%*.
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1
SCLS414N − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.
The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage
register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output
for cascading. When the output-enable (OE) input is high, all outputs except QH′ are in the high-impedance
state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
2
SER
SRCLK
X
X
X
X
X
X
L
SRCLR
FUNCTION
RCLK
OE
X
X
H
X
X
L
Outputs QA−QH are disabled.
Outputs QA−QH are enabled.
L
X
X
Shift register is cleared.
↑
H
X
X
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X
X
X
↑
X
Shift-register data is stored in the storage register.
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SCLS414N − APRIL 1998 − REVISED APRIL 2005
logic diagram (positive logic)
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
1D Q
C1
R
3D
C3 Q
15
2D Q
C2
R
3D
C3 Q
1
2D Q
C2
R
3D
C3 Q
2
2D Q
C2
R
3D
C3 Q
3
2D Q
C2
R
3D
C3 Q
4
2D Q
C2
R
3D
C3 Q
5
2D Q
C2
R
3D
C3 Q
6
2D Q
C2
R
3D
C3 Q
7
9
QA
QB
QC
QD
QE
QF
QG
QH
QH′
Pin numbers shown are for the D, DB, J, NS, PW, RGY, and W packages.
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3
SCLS414N − APRIL 1998 − REVISED APRIL 2005
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
QA
QB
QC
QD
QE
QF
QG
QH
QH′
NOTE:
4
ÎÎÎÎ
implies that the output is in 3-State mode.
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SCLS414N − APRIL 1998 − REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
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SCLS414N − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV595A
VCC
VIH
Supply voltage
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
IOL
∆t/∆v
High-level output current
Low-level output current
Input transition rise or fall rate
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
SN74LV595A
MIN
MAX
2
5.5
1.5
MIN
MAX
2
5.5
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
0.5
0
High or low state
0
3-state
0
VCC × 0.3
5.5
VCC
5.5
V
0.5
VCC × 0.3
VCC × 0.3
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
V
1.5
VCC × 0.7
VCC × 0.7
VCC = 2 V
VCC = 2.3 V to 2.7 V
UNIT
VCC × 0.3
VCC × 0.3
0
0
0
VCC × 0.3
5.5
V
V
VCC
5.5
V
µA
VCC = 2 V
VCC = 2.3 V to 2.7 V
−50
−50
−2
−2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
−8
−8
−16
−16
VCC = 2 V
VCC = 2.3 V to 2.7 V
50
50
2
2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
8
8
16
16
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
200
200
100
100
VCC = 4.5 V to 5.5 V
20
20
mA
µA
mA
ns/V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
( &)!*$'!& "!&"%*& +*!#" & % )!*$'3% !*
%2& +'% !) %3%-!+$%&. ('*'"%*" '' '& !%*
+%")"'!& '*% %2& 2!'-. %/' &*#$%& *%%*3% % *2 !
"'&2% !* "!&&#% %% +*!#" 0!# &!"%.
6
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV595A
PARAMETER
TEST CONDITIONS
IOH = −50 µA
IOH = −2 mA
VOH
QH′
QA−QH
QH′
QA−QH
QH′
QA−QH
QH′
QA−QH
MIN
2 V to 5.5 V
2.3 V
IOH = −6 mA
IOH = −8 mA
IOH = −12 mA
IOH = −16 mA
TYP
2.48
2.48
2.48
2.48
3.8
3.8
3.8
3.8
0.1
0.4
0.4
0.44
0.44
0.44
0.44
0.55
0.55
4.5 V
Ci
VI = VCC or GND
UNIT
V
0.1
IOL = 12 mA
IOL = 16 mA
VI = VCC or GND,
VI or VO = 0 to 5.5 V
MAX
2.3 V
3V
ICC
Ioff
TYP
2 V to 5.5 V
IOL = 6 mA
IOL = 8 mA
VI = 5.5 V or GND
VO = VCC or GND,
MIN
VCC−0.1
2
4.5 V
II
IOZ
SN74LV595A
MAX
VCC−0.1
2
3V
IOL = 50 µA
IOL = 2 mA
VOL
VCC
V
0.55
0.55
0 to 5.5 V
±1
±1
µA
QA−QH
5.5 V
±5
±5
µA
IO = 0
5.5 V
20
20
µA
0
5
5
µA
3.3 V
3.5
3.5
pF
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
MAX
MIN
7
7.5
7.5
RCLK high or low
7
7.5
7.5
SRCLR low
6
6.5
6.5
5.5
5.5
5.5
SRCLK↑ before RCLK↑†
Setup time
MIN
SN74LV595A
SRCLK high or low
SER before SRCLK↑
tsu
SN54LV595A
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
8
9
9
8.5
9.5
9.5
4
4
4
MAX
UNIT
ns
ns
th
Hold time
SER after SRCLK↑
1.5
1.5
1.5
ns
† This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
( &)!*$'!& "!&"%*& +*!#" & % )!*$'3% !*
%2& +'% !) %3%-!+$%&. ('*'"%*" '' '& !%*
+%")"'!& '*% %2& 2!'-. %/' &*#$%& *%%*3% % *2 !
"'&2% !* "!&&#% %% +*!#" 0!# &!"%.
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SCLS414N − APRIL 1998 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
MAX
SN74LV595A
MIN
5.5
5.5
5.5
RCLK high or low
5.5
5.5
5.5
5
5
5
SER before SRCLK↑
Setup time
MIN
SRCLK high or low
SRCLR low
tsu
SN54LV595A
3.5
3.5
3.5
SRCLK↑ before RCLK↑†
8
8.5
8.5
SRCLR low before RCLK↑
8
9
9
SRCLR high (inactive) before SRCLK↑
3
3
3
MAX
UNIT
ns
ns
th
Hold time
SER after SRCLK↑
1.5
1.5
1.5
ns
† This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
Setup time
MIN
MAX
SN74LV595A
MIN
SRCLK high or low
5
5
RCLK high or low
5
5
5
5.2
5.2
5.2
SER before SRCLK↑
3
3
3
SRCLK↑ before RCLK↑†
5
5
5
SRCLR low before RCLK↑
5
5
5
2.5
2.5
2.5
SRCLR low
tsu
SN54LV595A
SRCLR high (inactive) before SRCLK↑
MAX
UNIT
5
ns
ns
th
Hold time
SER after SRCLK↑
2
2
2
ns
† This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
( &)!*$'!& "!&"%*& +*!#" & % )!*$'3% !*
%2& +'% !) %3%-!+$%&. ('*'"%*" '' '& !%*
+%")"'!& '*% %2& 2!'-. %/' &*#$%& *%%*3% % *2 !
"'&2% !* "!&&#% %% +*!#" 0!# &!"%.
8
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SCLS414N − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
RCLK
SRCLK
QH′
H
tPHL
SRCLR
QH′
tPZH
tPZL
OE
QA−QH
tPHZ
tPLZ
OE
QA−QH
tPLH
tPHL
RCLK
QA−QH
tPLH
tPHL
SRCLK
QH′
H
tPHL
SRCLR
QH′
tPZH
tPZL
tPHZ
tPLZ
OE
OE
TA = 25°C
TYP
MAX
temperature
SN54LV595A
MIN
CL = 15 pF
65*
80*
45*
45
CL = 50 pF
60
70
40
40
CL = 15 pF
MIN
MAX
MIN
MAX
8.4*
14.2*
1*
15.8*
1
15.8
8.4*
14.2*
1*
15.8*
1
15.8
9.4*
19.6*
1*
22.2*
1
22.2
9.4*
19.6*
1*
22.2*
1
22.2
8.7*
14.6*
1*
16.3*
1
16.3
8.2*
13.9*
1*
15*
1
15
18.1*
1*
20.3*
1
20.3
8.3*
13.7*
1*
15.6*
1
15.6
QA−QH
QA−QH
UNIT
MHz
10.9*
CL = 50 pF
range,
SN74LV595A
LOAD
CAPACITANCE
QA−QH
tPLH
tPHL
free-air
9.2*
15.2*
1*
16.7*
1
16.7
11.2
17.2
1
19.3
1
19.3
11.2
17.2
1
19.3
1
19.3
13.1
22.5
1
25.5
1
25.5
13.1
22.5
1
25.5
1
25.5
12.4
18.8
1
21.1
1
21.1
10.8
17
1
18.3
1
18.3
13.4
21
1
23
1
23
12.2
18.3
1
19.5
1
19.5
14
20.9
1
22.6
1
22.6
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
( &)!*$'!& "!&"%*& +*!#" & % )!*$'3% !*
%2& +'% !) %3%-!+$%&. ('*'"%*" '' '& !%*
+%")"'!& '*% %2& 2!'-. %/' &*#$%& *%%*3% % *2 !
"'&2% !* "!&&#% %% +*!#" 0!# &!"%.
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SCLS414N − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
RCLK
SRCLK
QH′
H
tPHL
SRCLR
QH′
tPZH
tPZL
OE
QA−QH
tPHZ
tPLZ
OE
QA−QH
tPLH
tPHL
SRCLK
QH′
H
tPHL
SRCLR
QH′
tPHZ
tPLZ
OE
OE
80*
120*
70*
70
CL = 50 pF
55
105
50
50
CL = 50 pF
QA−QH
QA−QH
MIN
MAX
1*
13.5*
1
13.5
6*
11.9*
1*
13.5*
1
13.5
6.6*
13*
1*
15*
1
15
6.6*
13*
1*
15*
1
15
6.2*
12.8*
1*
13.7*
1
13.7
6*
11.5*
1*
13.5*
1
13.5
7.8*
11.5*
1*
13.5*
1
13.5
6.1*
14.7*
1*
15.2*
1
15.2
6.3*
14.7*
1*
15.2*
1
15.2
7.9
15.4
1
17
1
17
7.9
15.4
1
17
1
17
9.2
16.5
1
18.5
1
18.5
9.2
16.5
1
18.5
1
18.5
9
16.3
1
17.2
1
17.2
7.8
15
1
17
1
17
9.6
15
1
17
1
17
8.1
15.7
1
16.2
1
16.2
9.3
15.7
1
16.2
1
16.2
• DALLAS, TEXAS 75265
UNIT
MHz
11.9*
( &)!*$'!& "!&"%*& +*!#" & % )!*$'3% !*
%2& +'% !) %3%-!+$%&. ('*'"%*" '' '& !%*
+%")"'!& '*% %2& 2!'-. %/' &*#$%& *%%*3% % *2 !
"'&2% !* "!&&#% %% +*!#" 0!# &!"%.
POST OFFICE BOX 655303
MAX
6*
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
10
MIN
range,
SN74LV595A
CL = 15 pF
QA−QH
RCLK
SN54LV595A
MIN
CL = 15 pF
tPLH
tPHL
tPZH
tPZL
TA = 25°C
TYP
MAX
temperature
LOAD
CAPACITANCE
QA−QH
tPLH
tPHL
free-air
ns
ns
SCLS414N − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
RCLK
SRCLK
QH′
H
tPHL
SRCLR
QH′
tPZH
tPZL
OE
QA−QH
tPHZ
tPLZ
OE
RCLK
QA−QH
tPLH
tPHL
SRCLK
QH′
H
tPHL
SRCLR
QH′
tPHZ
tPLZ
OE
135*
170*
115*
115
CL = 50 pF
120
140
95
95
CL = 15 pF
CL = 50 pF
QA−QH
MIN
MAX
range,
SN74LV595A
CL = 15 pF
QA−QH
OE
SN54LV595A
MIN
QA−QH
tPLH
tPHL
tPZH
tPZL
TA = 25°C
TYP
MAX
temperature
LOAD
CAPACITANCE
QA−QH
tPLH
tPHL
free-air
MIN
MAX
UNIT
MHz
4.3*
7.4*
1*
8.5*
1
8.5
4.3*
7.4*
1*
8.5*
1
8.5
4.5*
8.2*
1*
9.4*
1
9.4
4.5*
8.2*
1*
9.4*
1
9.4
4.5*
8*
1*
9.1*
1
9.1
4.3*
8.6*
1*
10*
1
10
5.4*
8.6*
1*
10*
1
10
2.4*
6*
1*
7.1*
1
7.1
2.7*
5.1*
1*
7.2*
1
7.2
5.6
9.4
1
10.5
1
10.5
5.6
9.4
1
10.5
1
10.5
6.4
10.2
1
11.4
1
11.4
6.4
10.2
1
11.4
1
11.4
6.4
10
1
11.1
1
11.1
5.7
10.6
1
12
1
12
6.8
10.6
1
12
1
12
3.5
10.3
1
11
1
11
3.4
10.3
1
11
1
11
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6)
SN74LV595A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
VOL(V)
Quiet output, maximum dynamic VOL
0.3
V
Quiet output, minimum dynamic VOL
−0.2
V
VOH(V)
VIH(D)
Quiet output, minimum dynamic VOH
2.8
V
High-level dynamic input voltage
2.31
V
VIL(D)
Low-level dynamic input voltage
NOTE 6: Characteristics are for surface-mount packages only.
0.99
V
VCC
3.3 V
TYP
UNIT
5V
114
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
f = 10 MHz
111
pF
( &)!*$'!& "!&"%*& +*!#" & % )!*$'3% !*
%2& +'% !) %3%-!+$%&. ('*'"%*" '' '& !%*
+%")"'!& '*% %2& 2!'-. %/' &*#$%& *%%*3% % *2 !
"'&2% !* "!&&#% %% +*!#" 0!# &!"%.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SCLS414N − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
0V
VOH
50% VCC
VOL
50% VCC
50% VCC
tPZL
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
VOH
50% VCC
VOL
VCC
Output
Control
tPLZ
≈VCC
50% VCC
tPHZ
tPZH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LV595AD
ACTIVE
SOIC
D
16
SN74LV595ADBR
ACTIVE
SSOP
DB
SN74LV595ADBRE4
ACTIVE
SSOP
SN74LV595ADE4
ACTIVE
SN74LV595ADR
40
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DB
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV595ADRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV595ANSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV595ANSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV595APWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV595APWRE4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV595APWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV595APWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV595APWTE4
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV595APWTG4
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV595ARGYR
ACTIVE
QFN
RGY
16
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74LV595ARGYRG4
ACTIVE
QFN
RGY
16
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
40
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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