SCLS411I − APRIL 1998 − REVISED APRIL 2005 19 2 3 18 4 17 16 5 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE 1D 2D 3D 4D 5D 6D 7D 8D 1 20 19 1Q 18 2Q 2 3 17 3Q 16 4Q 4 5 15 5Q 14 6Q 6 7 SN54LV573A . . . FK PACKAGE (TOP VIEW) 2D 1D OE VCC VCC 20 1 SN74LV573A . . . RGY PACKAGE (TOP VIEW) 3D 4D 5D 6D 7D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 13 7Q 12 8Q 8 9 10 11 LE OE 1D 2D 3D 4D 5D 6D 7D 8D GND Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) 2Q 3Q 4Q 5Q 6Q 8D GND LE 8Q 7Q SN54LV573A . . . J OR W PACKAGE SN74LV573A . . . DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) D OE D D <0.8 V at VCC = 3.3 V , TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V , TA = 25°C Support Mixed-Mode Voltage Operation on All Ports GND D D Ioff Supports Partial-Power-Down Mode 1Q D 2-V to 5.5-V VCC Operation D Max tpd of 8 ns at 5 V D Typical VOLP (Output Ground Bounce) description/ordering information ORDERING INFORMATION QFN − RGY TOP-SIDE MARKING Reel of 1000 SN74LV573ARGYR Tube of 25 SN74LV573ADW Reel of 2000 SN74LV573ADWR SOP − NS Reel of 2000 SN74LV573ANSR 74LV573A SSOP − DB Reel of 2000 SN74LV573ADBR LV573A Tube of 70 SN74LV573APW Reel of 2000 SN74LV573APWR Reel of 250 SN74LV573APWT Reel of 2000 SN74LV573ADGVR LV573A SOIC − DW −40°C to 85°C TSSOP − PW TVSOP − DGV −55°C −55 C to 125 125°C C ORDERABLE PART NUMBER PACKAGE† TA LV573A LV573A LV573A VFBGA − GQN Reel of 1000 SN74LV573AGQNR LV573A CDIP − J Tube of 20 SNJ54LV573AJ SNJ54LV573AJ CFP − W Tube of 85 SNJ54LV573AW SNJ54LV573AW LCCC − FK Tube of 55 SNJ54LV573AFK SNJ54LV573AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2005, Texas Instruments Incorporated !"# #$# #%&!$# &&"# $ % '()$# $"* & #%&! '"%$# '"& " "&! % "+$ #&!"# $#$& ,$&&$#-* &# '&"#. " # #""$&)- #)" "#. % $)) '$&$!""&* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS411I − APRIL 1998 − REVISED APRIL 2005 description/ordering information (continued) The ’LV573A devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. GQN PACKAGE (TOP VIEW) 1 2 3 terminal assignments 4 1 2 3 4 A A 1D OE 1Q B B 3D 3Q VCC 2D C C 5D 4D 5Q 4Q D D 7D 7Q 6D 6Q E E GND 8D LE 8Q FUNCTION TABLE (each latch) INPUTS 2 OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2Q SCLS411I − APRIL 1998 − REVISED APRIL 2005 logic diagram (positive logic) OE LE 1 11 C1 1D 2 19 1D 1Q To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, FK, J, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W (see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W (see Note 3): GQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCLS411I − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 5) VCC VIH VI Input voltage VO Output voltage ∆t/∆v VCC = 2 V VCC = 2.3 V to 2.7 V High-level input voltage Low-level input voltage IOL SN74LV573A MIN MAX MIN MAX 2 5.5 2 5.5 Supply voltage VIL IOH SN54LV573A VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low-level output current Input transition rise or fall rate 0.5 0 0 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 0 High-level output current V 0.5 VCC × 0.3 VCC × 0.3 3-state V 1.5 VCC × 0.7 VCC × 0.7 High or low state UNIT 0 VCC 5.5 VCC × 0.3 5.5 0 0 V V VCC 5.5 V µA VCC = 2 V VCC = 2.3 V to 2.7 V −50 −50 −2 −2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V −8 −8 −16 −16 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 8 8 16 16 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 200 200 100 100 VCC = 4.5 V to 5.5 V 20 20 mA µA mA ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV573A PARAMETER VOH VOL TEST CONDITIONS IOH = −50 µA IOH = −2 mA VI = VCC or GND, VI or VO = 0 to 5.5 V Ci VI = VCC or GND IO = 0 MIN 3V 2.48 2.48 4.5 V 3.8 TYP MAX UNIT V 3.8 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V ±5 ±5 µA 5.5 V 20 20 µA 0 5 5 µA 3.3 V 1.8 #%&!$# #"&# '& # " %&!$/" & ".# '$" % "/")'!"#* $&$"& $$ $# "& '"%$# $&" ".# .$)* "+$ #&!"# &""&/" " &. $#." & ##" "" '& , #"* 4 MAX VCC−0.1 2 2 V to 5.5 V IOL = 8 mA IOL = 16 mA ICC Ioff TYP SN74LV573A VCC−0.1 2 2.3 V IOL = 50 µA IOL = 2 mA VI = 5.5 V or GND VO = VCC or GND MIN 2 V to 5.5 V IOH = −8 mA IOH = −16 mA II IOZ VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1.8 V pF SCLS411I − APRIL 1998 − REVISED APRIL 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX PARAMETER SN54LV573A MIN MAX SN74LV573A MIN MAX UNIT tw Pulse duration LE high 6.5 6.5 6.5 ns tsu Setup time Data before LE↓ 5 5 5 ns th Hold time Data after LE↓ 2 2 2 ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX PARAMETER SN54LV573A MIN MAX SN74LV573A MIN MAX UNIT tw Pulse duration LE high 5 5 5 ns tsu Setup time Data before LE↓ 3.5 3.5 3.5 ns th Hold time Data after LE↓ 1.5 1.5 1.5 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX PARAMETER tw Pulse duration LE high tsu Setup time th Hold time SN54LV573A MIN MAX SN74LV573A MIN MAX UNIT 5 5 5 ns Data before LE↓ 3.5 3.5 3.5 ns Data after LE↓ 1.5 1.5 1.5 ns switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) D Q LE Q LOAD CAPACITANCE MIN TA = 25°C TYP MAX CL = 15 pF SN54LV573A SN74LV573A MIN MAX MIN MAX 8.9* 15.8* 1* 18* 1 18 9.6* 16.2* 1* 19* 1 19 9.3* 16.2* 1* 19* 1 19 ten OE Q tdis OE Q 6.7* 12.6* 1* 15* 1 15 D Q 10.9 18.7 1 21 1 21 LE Q 11.6 19.1 1 23 1 23 ten OE Q 11.4 19 1 22 1 22 tdis OE Q 8.6 17.3 1 19 1 19 tpd CL = 50 pF tsk(o) 2 UNIT ns ns 2 * On products compliant to MIL-PRF-38535, this parameter is not production tested. #%&!$# #"&# '& # " %&!$/" & ".# '$" % "/")'!"#* $&$"& $$ $# "& '"%$# $&" ".# .$)* "+$ #&!"# &""&/" " &. $#." & ##" "" '& , #"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCLS411I − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) D Q LOAD CAPACITANCE MIN TA = 25°C TYP MAX SN54LV573A SN74LV573A MIN MAX MIN MAX 13* 1 13 6.2* 11* 1* 6.8* 11.9* 1* 14* 1 14 6.6* 11.5* 1* 13.5* 1 13.5 LE Q ten OE Q tdis OE Q 4.9* 11* 1* 13* 1 13 D Q 7.7 14.5 1 16.5 1 16.5 LE Q 8.2 15.4 1 17.5 1 17.5 ten OE Q 8 15 1 17 1 17 tdis OE Q 6.2 14.5 1 16.5 1 16.5 tpd CL = 15 pF CL = 50 pF tsk(o) 1.5 UNIT ns ns 1.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) D Q LE Q LOAD CAPACITANCE TA = 25°C MIN TYP MAX CL = 15 pF SN54LV573A SN74LV573A MIN MAX MIN MAX 4.3* 6.8* 1* 8* 1 8 4.7* 7.7* 1* 9* 1 9 4.7* 7.7* 1* 9* 1 9 ten OE Q tdis OE Q 3.5* 7.7* 1* 9* 1 9 D Q 5.3 8.8 1 10 1 10 LE Q 5.7 9.7 1 11 1 11 ten OE Q 5.7 9.7 1 11 1 11 tdis OE Q 4.2 9.7 1 11 1 11 tpd CL = 50 pF tsk(o) 1 UNIT ns ns 1 * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6) SN74LV573A PARAMETER MIN MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.6 0.8 V VOL(V) Quiet output, minimum dynamic VOL −0.5 −0.8 V VOH(V) Quiet output, minimum dynamic VOH 2.9 VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage V 2.31 V 0.99 NOTE 6: Characteristics are for surface-mount packages only. #%&!$# #"&# '& # " %&!$/" & ".# '$" % "/")'!"#* $&$"& $$ $# "& '"%$# $&" ".# .$)* "+$ #&!"# &""&/" " &. $#." & ##" "" '& , #"* 6 TYP POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V SCLS411I − APRIL 1998 − REVISED APRIL 2005 operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS D to Q Cpd Power dissipation capacitance Outputs enabled CL = 50 pF, LE to Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz VCC 3.3 V TYP UNIT 16 5V 18 3.3 V 18.2 5V 21.3 pF 7 SCLS411I − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL VOH 50% VCC VOL 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 50% VCC tPZL tPHL tPHL Out-of-Phase Output 0V VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing SN74LV573ADBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573AGQNR ACTIVE GQN 20 1000 SNPB Level-1-240C-UNLIM SN74LV573ANSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573APWT ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573APWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV573ARGYR ACTIVE QFN RGY 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74LV573ARGYRG4 ACTIVE QFN RGY 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74LV573AZQNR ACTIVE ZQN 20 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM BGA MI CROSTA R JUNI OR BGA MI CROSTA R JUNI OR Pins Package Eco Plan (2) Qty (1) TBD Lead/Ball Finish MSL Peak Temp (3) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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