HT1609L 2×40 Channel LCD Driver Features • • • Operating voltage: 2.7V~5.2V Bias voltage: static~1/5 bias LCD driving voltage: 3.0V~5.0V • • 2×40 internal LCD drivers available LCD driver with serial/parallel conversion function • • Remote controllers Calculators Applications • • Electronic dictionaries Portable computers General Description The HT1609L is an LCD driver LSI with 2×40 output channels using CMOS technology. It is equipped with two sets of 40-bit bidirectional shift registers, 40-bit data latches, 40-bit LCD drivers, and logic control circuits. from an LCD controller into parallel data and send out LCD driving waveforms to the LCD panel. The HT1609L is designed for general purpose LCD drivers. It can drive both static and dynamic drive LCDs. The LSI can be used as segment driver. The HT1609L can convert serial data received Block Diagram 1 25th Aug ’98 HT1609L Pin Assignment 2 25th Aug ’98 HT1609L Pad Assignment Chip size: 162 × 102 (mil)2 * The IC substrate should be connected to VDD in the PCB layout artwork. 3 25th Aug ’98 HT1609L Pad Coordinates Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 X –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –75.27 –70.34 –65.49 –60.65 –55.80 –50.96 –46.11 –41.27 –36.42 –31.58 –26.73 –21.89 –17.04 –12.20 –7.35 –2.51 2.34 7.18 12.03 16.87 21.72 26.56 31.41 36.25 41.10 45.94 50.79 55.63 60.48 65.32 70.17 Unit: mil Y 44.20 39.01 33.83 28.65 23.46 18.27 13.09 7.91 2.63 –2.55 –7.61 –12.66 –17.85 –23.12 –28.31 –33.58 –38.76 –43.99 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 –45.73 Pad No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 X 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 70.17 65.32 60.48 55.63 50.79 45.94 41.10 36.25 31.41 26.56 21.72 16.87 12.03 7.18 2.34 –2.51 –7.35 –12.20 –17.04 –21.89 –26.73 –31.58 –36.42 –41.27 –46.11 –50.96 –55.80 –60.65 –65.49 –70.34 4 Y –43.31 –38.25 –33.19 –28.14 –23.08 –18.02 –12.96 –7.91 –2.85 2.21 7.27 12.32 17.38 22.44 27.50 32.56 37.61 42.67 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 25th Aug ’98 HT1609L Pad Description Pad No. Pad Name I/O Description 1 Y0 O LCD driver output for channel 1 2 VEE — LCD power supply 3~6 V1~V4 I LCD bias supply voltage for LCD driver 7 VSS — Power supply (ground) 8 CLK1 I Clock to latch serial data on the falling edge (Note 1) 9 SHF1 I Shift direction selection of channel 1 shift register (Note 2) 10 SHF2 I Shift direction selection of channel 2 shift register (Note 2) 11 VDD — Power supply ( positive ) 12 CLK2 I Clock to shift serial data on the falling edge 13 DL1 I/O Data input/output of channel 1 shift register 14 DR1 I/O Data input/output of channel 1 shift register 15 DL2 I/O Data input/output of channel 2 shift register 16 DR2 I/O Data input/output of channel 2 shift register 17 ALT I Alternate signal input for LCD driving waveform 18~57 Y40~Y79 O LCD driver outputs for channel 2 58~96 Y39~Y1 O LCD driver outputs for channel 1 (Note 1) Note 1: Data is processed on the clock falling or rising edge as shown in the following table. 5 25th Aug ’98 HT1609L The output levels of channel 1 and 2 are decided by the combination of ALT and latched data. Refer to the following table: Latched Data ALT Channel 1 (Y0~Y39) Channel 2 (Y40~Y79) H (Selected) H V1 V1 L V2 V2 L (Non-selected) H V3 V3 L V4 V4 Note 2 : Shift direction of channel 1 and 2 Shift Direction of Channel 1 (Channel 2) SHF1 (SHF2) Shift Direction DL1 (DL2) DR1 (DR2) H Y39 to Y0 (Y79 to Y40) OUT IN L Y0 to Y39 (Y40 to Y79) IN OUT Absolute Maximum Ratings* Supply Voltage .............................. –0.3V to 5.5V Storage Temperature................. –50°C to 125°C Input Voltage..................VSS–0.3V to VDD+0.3V Operating Temperature............... –20°C to 70°C *Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. 6 25th Aug ’98 HT1609L Ta=25°C D.C. Characteristics Symbol Parameter Test Conditions VDD Conditions — Min. Typ. Max. Unit 2.7 — 5.2 V — 100 300 µA VDD Operating Voltage — IDD Operating Current 5V ISTB Standby Current 5V — — 1 5 µA VIL “L” Input Voltage 5V — — — 1 V VIH “H” Input Voltage 5V — 4 — — V VOL “L” Output Voltage 5V IOL=+0.4mA — — 0.4 V VOH “H” Output Voltage 5V IOH=–0.4mA 4.6 — — V VLCD LCD Driving Voltage — VDD–VEE 3 — 5.0 V No load Ta=25°C A.C. Characteristics Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit fCLK2 Data Shift Frequency 5V — — — 400 kHz tWCKH Clock High Level Width 5V — 800 — — ns tWCKL Clock Low Level Width 5V — 800 — — ns tSU Data Setup Time 5V — 300 — — ns tDH Data Hold Time 5V — 300 — — ns tDD Data Delay Time 5V — — — 500 ns tSUC1 Clock Setup Time 5V CLK2 → CLK1 500 — — ns tSUC2 Clock Setup Time 5V CLK1 → CLK 2 500 — — ns tR/tF Clock Rise/Fall Time 5V — — — 200 ns 7 25th Aug ’98 HT1609L Functional Description The HT1609L is an LCD driver LSI with 2×40 segment output channel. It operates with a controller, such as HT163A, or another segment driver LSI HT1608, HT1608L and HT1609L. Y79 (refer to Note 2). Data input/output The DL1, DR1, DL2, DR2 are data input or output option function. When SHF1 (SHF2) is connected to VDD, the 40th bit data of the 1st (2nd) 40-bit shift register outputs from DL1 (DL2) ; when SHF1 (SHF2) is connected to VSS or open , the 1~40 (41~80) bits data from LCD controller enter into the 1st (2nd) 40-bit shift through DL1 (DL2). Clock The CLK1 is the clock to latch data on the falling edge. It latches the data input from the bidirectional shift register at the falling edge of CLK1 and transfers its outputs to the LCD driver circuit. The CLK2 is the clock to shift data on the falling edge. It shifts the serial data at the falling of CLK2 and transfers the output of each bit of the register to the latch circuit (refer to Note 1). When SHF1 (SHF2) is connected to VDD, the 1~40 (41~80) bit data from the LCD controller enter into the 1st (2nd)40-bit shift register through DR1 (DR2); when SHF1 (SHF2) is connected to VSS or open , the 40th bit shift register outputs from DR1 (DR2) (refer to Note 2). Bidirectional shift register The HT1609L supplies two sets of 40-bit shift register, which controls the shift direction by SHF1 & SHF2. The SHF1 controls the 1st 40bit shift register, and SHF2 controls the 2nd 40-bit shift register. When SHF1 is connected to VDD, the 1st shift direction is from Y39 to Y0; when SHF1 is connected to VSS, the shift direction changes from Y0 to Y39. When SHF2 is connected to VDD, the 2nd shift direction is from Y79 to Y40; when SHF2 is connected to VSS, the shift direction changes from Y40 to LCD driver circuit Select one of the four levels of voltage V1, V2, V3,and V4 for driving an LCD and transfer it to the output terminals according to the combination of alternate signal (ALT) and the data in the latch circuit (refer to Note 1). 8 25th Aug ’98 HT1609L Static driver has to be twice the frequency of CLK1. ALT has to be synchronized on the falling edge of CLK1. When the HT1609L is used as a static driver, data is transferred on the falling edge of CLK2 and latched on the falling edge of CLK1. The frequency of CLK1 becomes the frame frequency of the LCD driver. The frequency of ALT The power supply for the LCD driver is used by shortening V1, V4 or V2, V3. The application circuit connections are shown below: Timing Diagrams 9 25th Aug ’98 HT1609L Application Circuits 10 25th Aug ’98