NT3882 Dot Matrix LCD 40-Channel Driver Features Provides a 40 channel LCD driver Internal serial to parallel conversion circuits: 20-bit shift register X 2 40-bit latch X 1 40-bit 4 level driver X 1 Logic circuit supply voltage range: 4.5V - 5.5V LCD driving voltage range (VDD - VEE): 3.5V to 11V Applicable LCD duty cycle: 1/2 to 1/16 Interfaces with a NT3881C/D LCD controller LCD bias voltage can be supplied externally Available in 64-pin QFP and in CHIP FORM General Description The NT3882 is a dot matrix LCD 40 channel driver fabricated by low power CMOS technology. This IC consists of two 20-bit shift registers, a 40-bit latch, and a 40-bit 4 level LCD driver. The NT3882 converts serial data which is received from the LCD controller (NT3881C/D) to parallel data and then outputs LCD driving waveforms to drive LCD. Expansion of charactertype liquid crystal display can be easily obtained according to the number and structure of characters. Pin Configuration Pad Configuration N C S 3 4 S 3 3 S 3 2 S 3 1 S 3 0 N C S 3 5 S 3 6 S 3 7 S 3 8 S 3 9 S 4 0 64 63 62 61 60 59 58 57 56 55 54 53 52 NC 1 51 V2 S29 2 50 NC S28 3 49 NC S27 4 48 V3 S26 5 47 NC S25 6 46 V EE S24 7 45 NC S23 8 44 NC S22 9 43 NC S21 10 42 M S20 11 41 S19 12 40 S18 13 39 DL2 S17 14 38 DR1 S16 15 37 DL1 S15 16 36 S14 17 S13 18 S12 19 NT3882F 20 21 22 23 24 25 26 27 28 29 30 31 32 S 9 S 1 0 S 1 1 S 8 S 7 V N C S 6 S 5 S 4 S 3 S 2 S 1 D S28 3 S27 4 S26 5 S25 6 S24 7 S23 8 S22 9 S21 10 S20 11 NC S19 12 DR2 S18 13 S17 14 S16 15 GND S15 16 35 CL2 S14 17 34 CL1 S13 18 33 NC S 2 9 S 3 4 S 3 3 S 3 2 S 3 1 S 3 0 S 3 5 S 3 6 S 3 7 S 3 8 S 3 9 S 4 0 2 63 62 61 60 59 57 56 55 54 53 52 NT3882H 51 V2 48 V3 46 V EE 42 M 40 DR2 39 DL2 38 DR1 37 DL1 36 GND 35 CL2 34 CL1 32 S1 25 19 20 21 22 23 24 S 1 2 S 9 S 1 0 S 1 1 S 8 S 7 V D 27 28 29 30 31 S 6 S 5 S 4 S 3 S 2 D D 1 V2.0 November, 1999 NT3882 Block Diagram S1 S2 S19 S20 S21 S22 S39 S40 V DD V2 40-Bit 4-Level LDC Drivers V3 V EE M 40-Bit Latch CL1 DL2 CL2 20-Bit Shift Register 20-Bit Shift Register DR1 DL2 2 DR2 GND NT3882 Pin and Pad Descriptions Pin No. Pad No. Designation I/O External Connection 2- 24, 27 - 32, 52 - 57, 59 - 63 27 - 32, 2 - 24, 52 - 57, 59 - 63 S29 - S7, S6 - S1, S40 - S35, S30 - S34 25 25 34 O LCD panel Segment signal output pins VDD P Power supply Power for logic circuits 34 CL1 I Controller Clock to latch serial data 35 35 CL2 I Controller Clock to shift serial data 36 36 GND P Power Supply 0V 37 37 DL1 I Controlleror NT3882 Data input of 1 - 20 bits from controller 38 38 DR1 O NT3882 Data output of 20 bit shift register 39 39 DL2 I Controlleror NT3882 Data input of 21 - 40 bits from controller 40 40 DR2 O NT3882 Data output of 40 bit shift register 42 42 M I Controller Alternate signal for LCD drivers 46, 48, 51 46, 48, 51 VEE, V3, V2 P Power Supply Power for LCD drivers - NC - - No connection 1, 26, 33, 41, 43 - 45, 47, 49, 50, 58, 64 Description Functional Description NT3882 is a dot matrix LCD segment driver LSI. It operates with the controller, such as NT3881C/D, and/or another segment driver LSI NT3882. NT3882 receives serial data from the controller or another NT3882, converts it to parallel data and then supplies the LCD driving waveforms to the LCD panel. 4. DR1 The 20th bit data of first 20-bit shift register output from DR1. The data shifted out from DR1 after 20 bit delay are synchronized with the clock pulse (CL2). By connecting DR1 to DL2, two 20-bit shift registers can be cascaded to one 40-bit shift register. 1. CL1 This signal is used for latching the shift register contents. When CL1 is set at high, the shift register contents are transferred to the 40-bit 4level LCD driver. When CL1 is set at low, the last display output data (S1 to S40) is held. 5. DL2 2. CL2 Clock pulse inputs for the two 20-bit shift registers. The data is shifted to a 40-bit latch at the falling edge of CL2. The clock singal CL2 must be active when operating to refresh shift registers' contents. The 40th bit data of the second 20-bit shift register output is from DR2. The data shifted out from DR2 after a 20-bit delay is synchronized with the clock pulse (CL2). By connecting DR2 to the next NT3882 DL1, the cascade construction is obtained to drive a wider LCD panel. 3. DL1 7. S1 to S40 The 1 - 20 bit data from LCD controller is fed into the first 20-bit shift register through DL1. These 40 bits represent the 40 data bits in the 40-bit latch. One of VDD, V2, V3 and VEE is selected as a LCD driving voltage source according to the combination of latched data level and the alternate signal (M). The 21 - 40 bit data from the LCD controller is fed into the second 20-bit shift register through DL2. 6. DR2 3 NT3882 The truth table is listed as follows: Latched Data M Output level of S1 to S40 1(High) 1(High) VEE (Selected) 0(Low) VDD 0(Low) 1(High) V3 (Nonselected) 0(Low) V2 Absolute Maximum Ratings* *Comments Power Supply Voltage (VDD-GND) . . . . . . . -0.3V to 7.0V Power Supply Voltage (VDD-VEE) . . . . . . . . . . . . . . . . . . Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposed to the absolute maximum rating conditions for extended periods may affect device reliability. . . . . . . . . . . . . . . . . . . . . . . . VDD - 13.5V to VDD + 0.3V Input Voltage . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V Operating Temperature . . . . . . . . . . . . . -20qC to + 75qC Storage Temperature . . . . . . . . . . . . . .-55qC to + 125qC DC Electrical Characteristics (VDD = 5.0V, GND = 0V, VEE = 0V, TA = 25qC) Symbol VIH Parameter Terminal Min. Typ. Max. Unit Input Voltage CL1, CL2 0.7 X VDD - VDD V DL1, DL2 0 - 0.3 X VDD V DR1, DR2 VDD - 0.4 - - V IOH = -0.4mA - - 0.4 V IOL = 0.4mA - - 1.1 V ION = 0.1mA for one of Sj 105 V ION = 0.05mA for each of Sj VIL VOH Output Voltage VOL VD1 Vi-Sj Voltage VD2 Descending Note 1 Conditions IIL Input Leakage Current CL1, CL2 DL1, DL2 -5 - 5 PA VIN = 0 or VDD IVL Vi Leakage Current V2, V3, VEE -10 - 10 PA S1 to S40 open IDD Power Supply Current Note 2 - - 200 PA fCL1 = 1KH fCL2 = 400KHz Note 1: Vi - Sj (Vi = VDD, V2, V3, VEE; j = 1 to 40) equivalent circuit. 1Kmax. Vi 1Kmax. Power Switch Data Swtich Sj Note 2: Input/output current is excluded. When the input is at the intermediate level with CMOS, some excessive current will flow through the input circuit to the power supply. To avoid this, the input level must be fixed at a high or low state. 4 NT3882 AC Characteristics (VDD = 5.0V, GND = 0V, VEE = 0V, TA = 25qC) Symbol Parameter fCL2 Data Shift Frequency tCWH Clock Width tCWL Terminal Min. Typ. Max. Unit CL2 - - 400 KHz High CL1, CL2 800 - - ns Low CL2 800 - - ns tDH Data Hold Time DL1, DL2 300 - - ns tSUD Data Set-up Time DL1, DL2 300 - - ns tSUC1 Clock Set-up Time (CL2 o CL1) CL1, CL2 500 - - ns tSUC2 Clock Set-up Time (CL1 o CL2) CL1, CL2 500 - - ns tCL Clock Rise/Fall Time CL1, CL2 - - 200 ns tPD Data Delay Time - 75 - 500 ns Timing Waveforms V IH CL2 t CWL V IL t CL t CWH t CL t DH t SUD DL1,DL2 t SUC1 t PD V OH DR1,DR2 V OL t SUC2 t SUC2 CL1 t CL t CWH 5 t CL NT3882 Application Circuit (for reference only) LCD PANEL C1 - C16 S1 - S1 S40 - S40 S1 - S40 DL1 D CL2 DR2 DL1 DL2 CL2 NT3882 CL1 DR2 DL2 NT3882 CL1 DR1 DR1 M M V DD GND V2 V3 V DD V EE GND V2 V3 V EE CL2 CL1 NT3881D M V DD GND V1 V2 V3 V4 V5 VR R R C R R C C R C C GND or other negative voltage 6 NT3882 Bonding Diagram S28 3 S27 4 S26 5 S25 6 S24 7 S23 8 S22 9 S21 10 S20 11 S19 12 S18 13 S17 14 S16 15 S15 16 S14 17 S13 18 S 2 9 S 3 4 S 3 3 S 3 2 S 3 1 S 3 0 S 3 5 S 3 6 S 3 7 S 3 8 S 3 9 S 4 0 2 63 62 61 60 59 57 56 55 54 53 52 NT3882H Y 51 V2 48 V3 46 V EE 42 M 40 DR2 39 DL2 38 DR1 37 DL1 36 GND 35 CL2 34 CL1 32 S1 X (0,0) 25 19 20 21 22 23 24 S 1 2 S 9 S 1 0 S 1 1 S 8 S 7 V 2235 Pm D 27 28 29 30 31 S 6 S 5 S 4 S 3 S 2 D * Connecting IC substrate to VDD or keeping floating is recommended. * Pad window area120Pm X 100Pm. 7 2514 Pm NT3882 Bonding Dimensions unit: Pm Pad No. Designation X Y Pad No. Designation X Y 2 S29 -729 1148 29 S4 621 -1148 3 S28 -985 1125 30 S3 771 -1148 4 S27 -985 975 31 S2 921 -1148 5 S26 -985 825 32 S1 985 -859 6 S25 -985 675 34 CL1 985 -705 7 S24 -985 525 35 CL2 985 -555 8 S23 -985 375 36 GND 985 -373 9 S22 -985 225 37 DL1 985 -204 10 S21 -985 75 38 DR1 985 -54 11 S20 -985 -75 39 DL2 985 96 12 S19 -985 -225 40 DR2 985 246 13 S18 -985 -375 42 M 985 396 14 S17 -985 -525 46 VEE 985 562 15 S16 -985 -675 48 V3 985 722 16 S15 -985 -825 51 V2 985 882 17 S14 -985 -975 52 S40 921 1148 18 S13 -985 -1125 53 S39 771 1148 19 S12 -729 -1148 54 S38 621 1148 20 S9 -579 -1148 55 S37 471 1148 21 S10 -429 -1148 56 S36 321 1148 22 S11 -279 -1148 57 S35 171 1148 23 S8 -129 -1148 59 S30 21 1148 24 S7 21 -1148 60 S31 -129 1148 25 VDD 171 -1090 61 S32 -279 1148 27 S6 321 -1148 62 S33 -429 1148 28 S5 471 -1148 63 S34 -579 1148 Ordering Information Part No. Package NT3882H CHIP FORM NT3882F 64L QFP 8 NT3882 Package Information QFP 64L Outline Dimensions unit: inches/mm ÉÅ Å ¶² ²º ´´ Æ ² ³± ã ´³ ÈÅ D Ôææ Åæõâêí Ç Ôæâõêïè Ñíâïæ y Â Í Â² ³ ä ÈÅ ÿ ÿ æ ÈÆ ¶³ ÉÆ ·µ Ͳ Symbol Dimensions in inches Dimensions in mm A 0.130 Max. 3.30 Max. A1 0.004 Min. 0.10 Min. A2 0.112 ± 0.005 2.85 ± 0.13 b 0.016 +0.004 -0.002 0.40 +0.10 -0.05 c 0.006 +0.004 -0.002 0.15 +0.10 -0.05 D 0.551 ± 0.005 14.00 ± 0.13 E 0.787 ± 0.005 20.00 ± 0.13 e 0.039 ± 0.006 1.00 ± 0.15 GD 0.693 NOM. 17.60 NOM. GE 0.929 NOM. 23.60 NOM. HD 0.740 ± 0.012 18.80 ± 0.31 HE 0.976 ± 0.012 24.79 ± 0.31 L 0.047 ± 0.008 1.19 ± 0.20 L1 0.095 ± 0.008 2.41 ± 0.20 y 0.006 Max. 0.15 Max. T 0q ~ 12q 0q ~ 12q Notes: 1. Dimensions D & E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only. 9 Åæõâêí Ç