NT3883 Dot Matrix LCD 80-Channel Driver Features Provides 80-channel LCD driver Internal serial to parallel conversion circuits: 40-bit bi-direction shift register 2 80-bit latch 1 80-bit 4-level driver 1 Logic circuit supply voltage range: 4.5V - 5.5V LCD driving voltage range (VDD - VEE): 3.5V to 11V Applicable LCD duty cycle: 1/2 to 1/16 Interfaces with a NT3881B/C/D LCD controller LCD bias voltage can be supplied externally Available in 100-pin QFP and in CHIP FORM General Description as NT3881B/C/D, to parallel data and outputs LCD driving waveforms to drive LCD. Expansion of character-type liquid crystal display can be easily obtained according to the number and structure of characters. The NT3883 is a dot matrix LCD 80-channel driver fabricated by low power CMOS technology. This IC consists of two 40-bit bi-directional shift registers, 80-bit latch and 80-bit 4-level LCD driver. The NT3883 converts serial data that are received from the LCD controller, such Pin Configuration S S S S S S S S S S S S S S S S S S S S 3 3 3 3 3 3 3 3 3 4 8 7 7 7 7 7 7 7 7 7 1 2 3 4 5 6 7 8 9 0 0 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NT3883F 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 N V V V V G C S S N N N C D D D D M N N C E D 3 2 N L L L C C C L L R L R C C 2 1 1 2 2 D 1 1 2 E D 1 V2.1 November, 1999 NT3883 Pad Configuration S 3 2 S 3 4 S 3 3 S 3 5 S 3 6 S 3 7 S 3 9 S 3 8 S 4 0 S 8 0 S 7 9 S 7 8 S 7 6 S 7 7 S 7 5 S 7 4 S 7 2 S 7 3 S31 100 81 S71 S30 1 80 S70 S29 2 79 S69 S28 3 78 S68 S27 4 77 S67 S26 5 76 S66 S25 6 75 S65 S24 7 74 S64 S23 8 73 S63 S22 9 72 S62 S21 10 71 S61 S20 11 70 S60 S19 12 69 S59 S18 13 68 S58 S17 14 67 S57 S16 15 66 S56 S15 16 65 S55 S14 17 64 S54 S13 18 63 S53 S12 19 62 S52 S11 20 61 S51 S10 21 60 S50 S9 22 59 S49 S8 23 58 S48 S7 24 57 S47 S6 25 56 S46 S5 26 55 S45 S4 27 54 S44 S3 28 53 S43 S2 29 52 S42 S1 30 51 S41 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 NT3883H 31 33 V V E D E D 34 V 3 35 36 V 2 G N D 37 G L 1 38 39 S L 1 S L 2 2 43 C L 2 44 D L 1 45 D R 1 46 47 48 D L 2 D R 2 M NT3883 Block Diagram S1 S2 S39 S40 S41 S42 S79 S80 V DD V2 80-Bit 4-Level LCD Drivers V3 V EE M 80-Bit Latch CL1 DL2 CL2 First 40-Bit Shift Register SL1 Second 40-Bit Shift Register DR1 DL2 3 SL2 DR2 GND NT3883 Absolute Maximum Ratings* *Comments Power Supply Voltage (VDD-GND) . . . . . . -0.3V to 7.0V Power Supply Voltage (VDD-VEE) . . . . . . . . . . . . . . . . . . Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to the absolute maximum rating conditions for extended periods may affect device reliability. . . . . . . . . . . . . . . . . . . . . . .VDD - 13.5V to VDD + 0.3V Input Voltage . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Operating Temperature . . . . . . . . . . -20qC to + 75q C Storage Temperature . . . . . . . . . . . . . -55qC to + 125qC DC Electrical Characteristics (VDD = 5.0V, GND = 0V, VEE = 0V, TA = 25qC) Parameter Input Voltage Symbol Terminal Min. Typ. Max. Unit VIH CL1, CL2, DL1, DL2 *1 0.7 VDD - VDD V 0 - 0.3 VDD V DR1, DR2 *1 VDD - 0.4 - - V IOH = -0.4mA - - 0.4 V IOL = +0.4mA - - 1.1 V ION = 0.1mA for one of Sj - - 1.5 V ION = 0.05mA for each of Sj VIL Output Voltage VOH VOL Vi - Sj Voltage VD1 Descending VD2 *2 Conditions Input Leakage Current IIL CL1, CL2 DL1, DL2*1 -5 - 5 PA VIN = 0 or VDD Vi Leakage Current IVL V2, V3, VEE -10 - 10 PA S1 to S80 open Power Supply Current IDD *3 - - 500 PA fCL1 = 1KHz fCL2 = 1MHz Note *1: SL1 and SL2 determine The Input or Output of DL1, DL2, DR1 and DR2 and the configuration is as follows. Terminal SL1 = High SL1 = Low SL2 = High SL2 = Low DL1 Output Input - - DR1 Input Output - - DL2 - - Output Input DR2 - - Input Output *2: Vi – Sj (Vi = VDD, V2, V3, VEE; j = 1 to 80) equivalent circuit (for reference) *3: Input/output current is excluded. When the input is at the intermediate level with CMOS, some excessive 1Kmax. 10Kmax. Vi Power Switch Data Swtich Sj Current will flow through the input circuit to power supply. To avoid this, the input level must be fixed at high or low state. 4 NT3883 AC Characteristics (VDD = 5.0V, GND = 0V, VEE = 0V, TA = 25qC) Symbol Terminal Min. Typ. Max. Unit fCL2 CL2 - - 400 KHz High tCWH CL1, CL2 800 - - ns Low Parameter Data Shift Frequency Clock Width tCWL CL2 800 - - ns Data Hold Time tDH DL1~2, DR1~2 300 - - ns Data Set-up Time tSUD DL1~2, DR1~2 300 - - ns Clock Set-up Time(CL2 CL1) tSUC1 CL1, CL2 500 - - ns tSUC2 CL1, CL2 500 - - ns Clock Rise/Fall Time tCL CL1, CL2 - - 200 ns Data Delay Time tPD - - - 500 ns ( Clock Set-up Time(CL1(CL2) Timing Waveforms V IH CL2 t CWL V IL t CL t CWH t CL t DH DL1, DL2 t SUD t SUC1 t PD V OH DR1, DR2 V OL t SUC2 t SUC2 CL1 t CL t CWH 5 t CL NT3883 Pin and Pad Descriptions Pin No. Pad No. Designation I/O External Connection Description 1~30, 51~100 1~30, 51~100 S1~S30, S80~S31 O LCD panel 33 33 VDD P Power supply Power for logic circuits 36 36 GND P Power supply 0V 37 37 CL1 I Controller 38 38 SL1 I MPU Segment signal output pins Clock to latch serial data Shift left control for 1st 40-bit shift register (see NOTE*4) 39 39 SL2 I MPU Shift left control for 1st 40-bit shift register (see NOTE*4) 43 43 CL2 I Controller 44 44 DL1 I/O Controller or NT3882A/NT3 883 Data input/output of 1st 40-bit shift register Controller or NT3882A/NT3 883 Data input/output of 1st 40-bit shift register Controller or NT3882A/NT3 883 Data input/output of 2nd 40-bit shift register Controller or NT3882A/NT3 883 Data input/output of 2nd 40-bit shift register 45 46 47 45 DR1 46 I/O DL2 47 I/O DR2 I/O Clock to shift serial data 48 48 M I Controller 31, 34, 35 31, 34, 35 VEE, V3, V2 P Power supply 32, 40, 41, 42, 49,50 - NC - - (see NOTE*4) (see NOTE*4) (see NOTE*4) (see NOTE*4) Alternate signal for LCD drivers Power for LCD drivers No connection NOTE *4: Relation of SL1, SL2, DL1, DR1, DL2 and DR2 SL1 SL2 Shift Direction DL1 DR1 DL2 DR2 1(High) - Left(S40 to S1) Output Input - - 0(Low) - Right(S1 to S40) Input Output - - - 1(High) Left(S80 to S41) - - Output Input - 0(Low) Right(S41 to S80) - - Input Output 6 NT3883 Functional Description NT3883 is a dot matrix LCD segment driver LSI. It operates with the controller, such as NT3881B/C/D, and/or another segment driver LSI NT3882A/3883. NT3883 receives serial data from the controller or another NT3883, converts it to parallel data and then supplies the LCD driving waveforms to the LCD panel. 5. DL2 st th st th Data input/output of the 41 - 80 register. When SL2 is connected to GND, the data from LCD controller is fed st th into the 41 - 80 register through DL2 serially. If SL2 is connected to VDD, the DL2 becomes the output of the st th 41 - 80 register. 1. CL1 6. DR2 This signal is used for latching the shift register contents. When CL1 is set at high, the shift register contents are transferred to the 80-bit 4level LCD driver. When CL1 is set at low, the last display output data (S1 to S80) is held. Data input/output of the 41 - 80 register. When SL2 is th st th connected to GND, the 80 bit of the 41 - 80 register output from DR2. By connecting DR2 to DL1 of next NT3882A/3883, the cascade structure is obtained to drive a wider LCD panel. If SL2 is connected to VDD, the st th DR2 becomes the input of the 41 - 80 register, in this case, the data may come from the next NT3882A/3883. 2. CL2 Clock pulse inputs for the two 40-bit shift registers. The data is shifted to an 80-bit latch at the falling edge of CL2. The clock signal CL2 must be active when operating to refresh shift registers' contents. 7. SL1 st 3. DL1 st th The shift direction of S1 to S40, i.e. 1 to 40 shift register, is selected by SL1. The detail function description is listed in Note*4 of Page5. th Data input/output of the 1 - 40 register. When SL1 is connected to GND or open, the data from LCD controller st th is fed into the 1 - 40 register through DL1 serially. If SL1 is connected to VDD, the DL1 becomes the output of st th the 1 - 40 register. 8. SL2 st th The shift direction of S41 to S80, i.e. 41 to 80 shift register, is selected by SL2. The detail function description is listed in Note*4 of Page5. 9. S1 to S80 4. DR1 st LCD driver output pins. These 80 bits represent the 80 data bits in the 80-bit latch and one of VDD, V2, V3 and VEE is selected as a LCD driving voltage source according to the combination of latched data level and the alternate signal (M). The truth table is listed as follows: th Data input/output of the 1 - 40 register. When SL1 is th st th connected to GND, the 20 bit of the 1 - 40 register output from DR1. By connecting DR1 to DL2, two 40-bit shift registers cascaded to one 80-bit shift register. If SL1 is connected to VDD, the DR1 becomes the input of st th the 1 - 40 register, in this case, the data may come from DL2. Latched Data M Output Level of S1 to S80 1(High) 1(High) VEE (Selected) 0(Low) VDD 0(Low) 1(High) V3 (Non-selected) 0(Low) V2 7 NT3883 Application Circuit (for reference only) 20 Chars x 4 Lines LCD PANEL C1 - C16 S1 - S1 S40 - S80 S1 - S80 DL1 D CL2 DR2 DL1 DL2 CL2 NT3883 CL1 DR2 DL2 NT3883 CL1 DR1 DR1 M M V DD GND V2 V3 V DD V EE GND V2 V3 V EE CL2 CL1 NT3881D M V DD GND V1 V2 V3 V4 V5 VR R R C R R C C R C C GND or other negative voltage 8 NT3883 Bonding Diagram S 3 2 S 3 3 S 3 4 S 3 5 S 3 6 S 3 7 S 3 8 S 3 9 S 4 0 S 8 0 S 7 9 S 7 8 S 7 7 S 7 6 S 7 5 S 7 4 S 7 3 S 7 2 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 S31 100 81 S71 S30 1 80 S70 S29 2 79 S69 S28 3 78 S68 S27 4 77 S67 S26 5 76 S66 S25 6 75 S65 S24 7 74 S64 S23 8 73 S63 S22 9 72 S62 S21 10 71 S61 S20 11 70 S60 S19 12 69 S59 S18 13 68 S58 S17 14 67 S57 S16 15 66 S56 S15 16 65 S55 S14 17 64 S54 S13 18 63 S53 S12 19 62 S52 S11 20 61 S51 S10 21 60 S50 S9 22 59 S49 S8 23 58 S48 S7 24 57 S47 S6 25 56 S46 S5 26 55 S45 S4 27 54 S44 S3 28 53 S43 S2 29 52 S42 S1 30 51 S41 NT3883H Y X (0,0) 31 33 34 35 36 37 38 39 43 44 45 46 47 48 V E E V D D V 3 V 2 G N D G L 1 S L 1 S L 2 C L 2 D L 1 D R 1 D L 2 D R 2 M 3 9 4 0 Pm 2 5 9 0 Pm * Connecting IC substrate to VDD or keeping floating is recommended. * Pad window area 100Pm 100Pm. 9 NT3883 Bonding Dimensions Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 34 35 36 37 38 39 43 44 45 46 47 48 51 52 53 Designation S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 VEE VDD V3 V2 GND CL1 SL1 SL2 CL2 DL1 DR1 DL2 DR2 M S41 S42 S43 X -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1184 -945 -807 -670 -520 -353 -204 -54 95 245 395 545 695 845 995 1185 1195 1195 Y 1677 1557 1437 1317 1197 1077 957 837 717 597 477 357 237 117 -2 -122 -242 -362 -482 -602 -722 -842 -962 -1082 -1202 -1322 -1442 -1562 -1682 -1812 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1812 -1682 -1562 Pad No. 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 Designation S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 X 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1185 995 875 755 635 515 395 275 155 35 -84 -204 -324 -444 -564 -684 -805 -925 -1045 -1184 unit: Pm Y -1442 -1311 -1202 -1082 -962 -842 -722 -602 -482 -362 -242 -122 -2 117 237 357 477 597 717 837 957 1077 1197 1317 1437 1557 1677 1811 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1811 NT3883 Ordering Information Part No. Package NT3883H CHIP FORM NT3883F 100L QFP 11 NT3883 Package Information QFP 100L Outline Dimensions unit: inches/mm HD D 64 24 41 E 1 e b 40 y A L A1 D A2 GD See Detail F Seating Plane ~ ~ GD c 25 GE 65 HE 80 L1 Detail F Symbol Dimensions in inches Dimensions in mm A 0.130 Max. 3.30 Max. A1 0.004 Min. 0.10 Min. A2 0.112±0.005 2.85±0.13 b 0.014 +0.004 -0.002 0.35 +0.10 -0.05 c 0.006 +0.004 -0.002 0.15 +0.10 -0.05 D 0.551±0.005 14.00±0.13 E 0.787±0.005 20.00±0.13 e 0.031±0.006 0.80±0.15 GD 0.693 NOM. 17.60 NOM. GE 0.929 NOM. 23.60 NOM. HD 0.740±0.012 18.80±0.31 HE 0.976±0.012 24.79±0.31 L 0.047±0.008 1.19±0.20 L1 0.095±0.008 2.41±0.20 y 0.006 Max. 0.15 Max. T 0q ~ 12q 0q ~ 12q Notes: 1. Dimensions D & E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only 12