HT6116-70 CMOS 2K×8-Bit SRAM Features • • • • • • • • • Single 5V power supply Low power consumption – Operating: 400mW (Typ.) – Standby: 5µW (Typ.) 70ns (Max.) high speed access time Power down by pin CS TTL compatible interface levels • Fully static operation Memory expansion by pin OE Common I/O using tri-state outputs Pin-compatible with standard 2K×8 bits of EPROM/MASK ROM 24-pin DIP/SDIP/SOP package General Description The HT6116-70 is a 16384-bit static random access memory. It is organized with 2048 words of 8 bits in length, and operates with a single 5V power supply. The IC is built with a high performance CMOS 0.8µm process in order to obtain a low standby current and high reliability. The IC contains six-transistor full CMOS mem- ory cells and TTL compatible inputs and outputs, which are easily interface with common system bus structures. The Data bus of the HT6116-70 is designed as a tri-state type. The IC is in the standby mode if the CS pin is set to “high”. Pin Assignment Block Diagram 1 3rd July ’97 HT6116-70 Pin Description Pin No. Pin Name I/O 8~1, 23, 22, 19 A0~A7 A8, A9, A10 9~11 13~17 D0~D2 D3~D7 12 VSS I Negative power supply, usually connected to the ground 18 CS I Chip select signal pin When this signal is high, the chip is in the standby mode. The chip is in the active mode, if CS is low. 20 OE I Output enable signal pin 21 WE I Write enable signal pin 24 VDD I Positive power supply I I/O Description Address inputs Data inputs and outputs Absolute Maximum Ratings* Supply Voltage ............................–0.3V to +7.0V Storage Temperature...............–50°C to +125°C Input Voltage................. VSS–0.3V to VDD+0.3V Operating Temperature.............–40°C to +85°C *Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability. D.C. Characteristics Symbol Parameter (Ta=25°C) Test Conditions VDD Conditions Min. Typ. Max. Unit VDD Operating Voltage — — 4.5 5.0 5.5 V ILI Input Leakage Current 5V VIN=0 to VDD — 0.1 10 µA ILO Output Leakage Current 5V VO=0 to VDD — 0.1 10 µA 5V VIH=2.2V, VIL=0.8V In write mode, tWC=1µs. — 45 90 mA 5V VIH=2.2V, VIL=0.8V In read mode, tRC=1µs. — 80 90 mA 5V VIH=2.2V, VIL=0.8V (TTL Input) — 0.8 1.5 mA 5V VIH=4.8V, VIL=0.2V (CMOS Input) — 0.1 3 µA IDD ISTB Operating Current Standby Current 2 3rd July ’97 HT6116-70 Symbol VIH Parameter Input Voltage Test Conditions Conditions VDD 5V — 2.2 2 5.3 Unit V –0.3 0.2 0.8 V IOH Output Source Current 5V VOH=4.5V –1.2 –6.2 — mA IOL Output Sink Current 5V VOL=0.5V 4.8 14.5 — mA VIL 5V Min. Typ. Max. A.C. Test Conditions Item Condition Input pulse high level VIH=3V Input pulse low level VIL=0V Input and output reference level 1.5V Output load See Figures below 3 3rd July ’97 HT6116-70 A.C. Characteristics (VDD=5V±10%, GND=0V, Ta=–40°C to +85°C) Read cycle Symbol Parameter Min. Typ. Max. Unit tRC Read Cycle Time 70 36 — ns tAA Address Access Time — 35 70 ns tACS Chip Select Access Time — 35 70 ns tOE Output Enable to Output Valid — 12 40 ns tOH Output Hold from Address Change 10 12 — ns tCLZ Chip Enable to Output in Low-Z 10 — — ns tOLZ Output Enable to Output in Low-Z 10 — — ns tOHZ Output Disable to Output in High–Z 0 — 30 ns tCHZ Chip Disable to Output in High-Z 0 — 30 ns Note: 1. A read occurs during the overlap of a low CS and a high WE 2. tCHZ and tOHZ are specified by the time when data out is floating (VDD=5V±10%, GND=0V, Ta=–40°C to +85°C) Write cycle Symbol Parameter Min. Typ. Max. Unit tWC Write Cycle Time 70 36 — ns tDW Data Set up Time 20 18 — ns tDH Data Hold Time from Write Time 5 0 — ns tAW Address Valid to End of Write 50 15 — ns tAS Address Setup Time 20 14 tWP Write Pulse Width 25 0 — ns tWR Write Recovery Time 5 — — ns tCW Chip Selection to End of Write 35 — — ns tOW Output Active from End of Write 5 — — ns tOHZ Output Disable to Output in High-Z 0 — 40 ns tWHZ Write to Output in High-Z 0 — 50 ns ns Note: 1. A write cycle occurs during the overlap of a low CS and a low WE 2. OE may be both high and low in a write cycle 3. tAS is specified from CS or WE, whichever occurs last 4. tWP is an overlap time of a low CS and a low WE 5. tWR, tDW and tDH is specified from CS or WE, whichever occurs first 6. tWHZ is specified by the time when DATA OUT is floating, not defined by output level 7. When I/O pins are data output mode, don’t force inverse signals to those pins 4 3rd July ’97 HT6116-70 Functional Description The HT6116-70 is a 2K×8 bit SRAM. When the CS pin of the chip is set to “low”, data can be written in or read from eight data pins; otherwise, the chip is in the standby mode. During a write cycle, the data pins are defined as the input state by setting the WE pin to low. Data should be ready before the rising edge of the WE pin according to the timing of the writing cycle. While in the read cycle, the WE pin is set to high and the OE pin is set to low to define the data pins as the output state. All data pins are defined as a three-state type, controlled by the OE pin. In both cycles (namely, write and read cycles), the locations are defined by the address pins A0~A10. The following table illustrates the relations of WE, OE, CS and their corresponding mode. CS OE WE Mode H X X Standby High–Z L L H Read Dout L H H Read High–Z L X L Write Din where D0~D7 X stands for “don’t care”. H stands for high level L stands for low level. Timing Diagrams Read cycle (1) 5 3rd July ’97 HT6116-70 Read cycle (1, 2, 4) Read cycle (1, 3, 4) Notes: (1) WE is high during the Read cycle (2) Device is continuously enabled, CS=VIL (3) Address is valid prior to or coincident with the CS transition low. (4) OE=VIL (5) Transition is measured±500mV from the steady state. 6 3rd July ’97 HT6116-70 Write cycle 1 (1) Write cycle 2 (1, 6) Notes: (1) WE must be high during all address transitions. (2) A write occurs during the overlap (tWP) of a low CS and a low WE. (3) tWR is measured from the earlier of CS or WE going high to the end of the write cycle. (4) During this period, I/O pins are in the output state, so the input signals of the opposite phase to the outputs must not be applied. (5) If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state. 7 3rd July ’97 HT6116-70 (6) OE is continuously low (OE=VIL). (7) DOUT is at the same phase of the write data of this write cycle. (8) DOUT is the read data of the next address. (9) If CS is low during this period, I/O pins are in the output state; then the data input signals of the opposite phase to the outputs must not be applied to them. (10) Transition is measured ± 500mV from the steady state. (Ta=–40°C to +85°C) Data Rentention Characteristics Symbol Parameter Conditions Min. Max. Unit VDR VDD for Data Retention CS ≥ VDD-0.2V 2 5.5 V ICCDR Data Retention Current VDD=3V, CS ≥ VDD-0.2V VIN ≥ VDD-0.2V or VIN ≤ 0.2V — 50 µA tCDR Chip Disable Data Retention Time See Retention Timing 0 — ns tR Operation Recovery Time tRC* — ns See Retention Timing *tRC=Read Cycle Time Low VDD Data Retention Timing 8 3rd July ’97 HT6116-70 Characteristic Curves 9 3rd July ’97 HT6116-70 10 3rd July ’97