MOSEL V62C51864

MOSEL VITELIC
PRELIMINARY
V62C51864
8K X 8 STATIC RAM
Features
Description
■ High-speed: 35, 70 ns
■ Ultra low DC operating current of 5mA (max.)
■ Low Power Dissipation:
– TTL Standby: 2 mA (Max.)
– CMOS Standby: 15 mA (Max.)
■ Fully static operation
■ All inputs and outputs directly compatible
■ Three state outputs
■ Ultra low data retention current (VCC = 2V)
■ Single 5V ± 10% Power Supply
■ Packages
– 28-pin 600 mil PDIP
– 28-pin 330 mil SOP (450 mil pin-to-pin)
The V62C51864 is a 65,536-bit static random
access memory organized as 8,192 words by 8
bits. It is built with MOSEL VITELIC’s high
performance CMOS process. Inputs and threestate outputs are TTL compatible and allow for
direct interfacing with common system bus
structures.
Functional Block Diagram
A0
VCC
Row
Decoder
GND
512 x 128
Memory Array
A8
I/O0
Column I/O
Input
Data
Circuit
Column Decoder
I/O7
A9
CE2
CE1
OE
WE
A12
Control
Circuit
51864 01
Device Usage Chart
Operating
Temperature
Range
P
F
35
70
L
LL
Temperature
Mark
0°C to 70°C
•
•
•
•
•
•
Blank
–40°C to +85°C
•
•
•
•
•
•
I
V62C51864 Rev. 2.1 June 1998
Package Outline
Access Time (ns)
1
Power
V62C51864
MOSEL VITELIC
Pin Descriptions
WE
Write Enable Input
An active LOW input, WE input controls read and
write operations. When CE1 and WE inputs are
both LOW with CE2 HIGH, the data present on the
I/O pins will be written into the selected memory
location.
A0 –A12
Address Inputs
These 13 address inputs select one of the 8,192 x
8-bit words in the RAM.
CE1, CE2 Chip Enable Inputs
CE1 is active LOW and CE2 is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
I/O0 –I/O7 Data Input/Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
Output Enable Input
OE
The Output Enable input is active LOW. When OE
is LOW with CE1 LOW, CE2 HIGH, and WE HIGH,
data of the selected memory location will be
available on the I/O pins. When OE is HIGH, the I/O
pins will be in the high impedance state.
VCC
Power Supply
GND
Ground
Pin Configuration
28-Pin Plastic DIP/SOP
Top View
NC
1
28
VCC
A12
2
27
WE
A7
3
26
CE2
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CE1
A0
10
19
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
13
16
I/O4
GND
14
15
I/O3
51864 02
V62C51864 Rev. 2.1 June 1998
2
V62C51864
MOSEL VITELIC
Part Number Information
V
MOSEL-VITELIC
MANUFACTURED
62
C
51
8
64
–
TEMP.
SRAM
FAMILY
OPERATING
VOLTAGE
DENSITY
SPEED
PKG
BLANK = 0¡C to 70¡C
I = -40¡C to +85¡C
64K
62 = STANDARD
C = CMOS PROCESS
P = 600 mil PDIP
F = 330 mil SOP (450 mil pin-to-pin)
PWR.
35 ns
70 ns
51 = 5V
ORGANIZATION
8 = 8-bit
L = LOW POWER
LL = DOUBLE LOW POWER
51864 05
Absolute Maximum Ratings (1)
Symbol
Parameter
Commercial
Industrial
VCC
Supply Voltage
-0.5 to +7
-0.5 to +7
V
VN
Input Voltage
-0.5 to +7
-0.5 to +7
V
VDQ
Input/Output Voltage Applied
V + 0.5
CC
TBIAS
Temperature Under Bias
-10 to +125
-65 to +135
°C
TSTG
Storage Temperature
-55 to +125
-65 to +150
°C
VCC + 0.5
Units
V
NOTE:
1.
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance*
Truth Table
TA = 25°C, f = 1.0MHz
Symbol
Parameter
Conditions
Max.
CIN
Input Capacitance
V
IN = 0V
6
COUT
Output Capacitance
V
I/O = 0V
8
WE
X
X
X
High Z
X
L
X
X
High Z
Output Disable
L
H
H
H
High Z
Read
L
H
L
H
DOUT
Write
L
H
X
L
DIN
CE1
CE2
pF
Standby
H
pF
Standby
NOTE:
* This parameter is guaranteed and not tested.
NOTE:
X = Don’t Care, L = LOW, H = HIGH
V62C51864 Rev. 2.1 June 1998
3
I/O
Operation
OE
Mode
Unit
V62C51864
MOSEL VITELIC
DC Electrical Characteristics (over all temperature ranges, VCC = 5V ± 10%)
Symbol
Min.
Typ.
Max.
Units
VIL
(1,2)
Input LOW Voltage
-0.5
—
0.8
V
VIH
(1)
Input HIGH Voltage
2.2
—
6
V
IIL
Input Leakage Current
V
CC
= Max, VIN = 0V to VCC
-5
—
5
mA
IOL
Output Leakage Current
V
CC
= Max, CE = VIH, VOUT = 0V to VCC
-5
—
5
mA
VOL
Output LOW Voltage
V
CC = Min, IOL = 2.1mA
—
—
0.4
V
VOH
Output HIGH Voltage
V
CC = Min, IOH = -1mA
2.4
—
—
V
Symbol
ICC
Parameter
Test Conditions
Power Com.(4) Ind.(4)
Units
READ
5
6
mA
WRITE
0
50
60
70
mA
L
3
4
mA
LL
2
3
L
60
70
LL
15
30
Parameter
Operating Power Supply Current, CE
1 = VIL, CE2 = VIH,
Output Open, V
=
Max.,
f
=
0
CC
ICC1
Average Operating Current, CE
1 = VIL, CE2 = VIH, Output Open,
VCC = Max., f = fMAX(3)
ISB
TTL Standby Current
CE1 ³ VIH, CE2 £ VIL, VCC = Max.
CMOS Standby Current, CE
1 ³ VCC – 0.2V, CE2 £ 0.2V,
VIN ³ VCC – 0.2V or VIN £ 0.2V, VCC = Max.
ISB1
NOTES:
1.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2.
VIL (Min.) = -3.0V for pulse width < 20ns.
3.
4.
Key to Switching Waveforms
fMAX = 1/tRC.
Maximum values.
AC Test Conditions
WAVEFORM
Input Pulse Levels
0 to 3V
Input Rise and Fall Times
5 ns
Timing Reference Levels
1.5V
Output Load
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
“OFF” STATE
see below
AC Test Loads and Waveforms
+5V
1800 ½
I/O Pins
990 ½
CL = 30 pF*
* Includes scope and jig capacitance
51864 06
V62C51864 Rev. 2.1 June 1998
4
mA
V62C51864
MOSEL VITELIC
Data Retention Characteristics
Symbol
VDR
ICCDR
Parameter
VCC for Data Retention
tR
Typ.(2)
Max.
Units
2.0
—
5.5
V
L
—
0.5
50
mA
LL
—
0.5
10
L
—
—
70
LL
—
—
20
CE
1 ³ VCC – 0.2V, CE2 £ 0.2V,
VIN ³ VCC – 0.2V, or VIN £ 0.2V
Data Retention Current
CE1 ³ VDR – 0.2V, CE2 £ 0.2V,
VIN ³ VCC – 0.2V, or VIN £ 0.2V
Com’l
Ind.
tCDR
Min.
Power
Chip Deselect to Data Retention Time
0
t (1)
RC
Operation Recovery Time (see Retention Waveform)
—
—
NOTES:
1.
tRC = Read Cycle Time
2.
TA = +25°C.
Low VCC Data Retention Waveform (1) (CE1 Controlled)
Data Retention Mode
VCC
4.5V
VDR ³ 2V
tCDR
CE1
2.2V
4.5V
tR
CE1 ³ VCC – 0.2V
2.2V
51864 14
Low VCC Data Retention Waveform (2) (CE2 Controlled)
Data Retention Mode
VCC
4.5V
VDR ³ 2V
tCDR
CE2
V62C51864 Rev. 2.1 June 1998
2.2V
4.5V
tR
CE2 ² 0.2V
5
2.2V
51864 15
—
—
ns
ns
V62C51864
MOSEL VITELIC
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
Parameter
Name
-35
Parameter
-70
Min.
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
35
—
70
—
ns
tAA
Address Access Time
—
35
—
70
ns
tACS1
Chip Enable Access Time
—
35
—
70
ns
tACS2
Chip Enable Access Time
—
35
—
70
ns
tOE
Output Enable to Output Valid
—
15
—
30
ns
tCLZ1
Chip Enable to Output in Low Z
5
—
5
—
ns
tCLZ2
Chip Enable to Output in Low Z
5
—
5
—
ns
tOLZ
Output Enable to Output in Low Z
5
—
5
—
ns
tCHZ
Chip Disable to Output in High Z
0
20
0
20
ns
tOHZ
Output Disable to Output in High Z
0
20
0
20
ns
tOH
Output Hold from Address Change
5
—
5
—
ns
Write Cycle
Parameter
Name
-35
Parameter
-70
Min.
Max.
Min.
Max.
Unit
35
—
70
—
ns
tWC
Write Cycle Time
tCW
Chip Enable to End of Write
35
tAS
Address Setup Time
0
tAW
Address Valid to End of Write
35
tWP
Write Pulse Width
25
—
50
—
ns
tWR
Write Recovery Time
0
—
0
—
ns
tWHZ
Write to Output High-Z
0
20
tDW
Data Setup to End of Write
25
tDH
Data Hold from End of Write
0
—
0
—
ns
tOW
Output Active from End of Write
5
—
5
—
ns
V62C51864 Rev. 2.1 June 1998
6
—
—
—
—
70
0
70
0
30
—
—
—
ns
ns
ns
25
ns
—
ns
V62C51864
MOSEL VITELIC
Switching Waveforms (Read Cycle)
Read Cycle 1(1, 2)
tRC
ADDRESS
tAA
OE
tOE
tOLZ
tOH
tOHZ(5)
I/O
51864 11
Read Cycle 2(1, 2, 4)
tRC
ADDRESS
tAA
tOH
tOH
I/O
51864 09
Read Cycle 3(1, 3, 4)
ADDRESS
CE1
tACS1
CE2
I/O
tACS2
tCLZ1
tCHZ(5)
(5)
tCLZ2(5)
51864 10
NOTES:
1.
WE = VIH.
2.
CE1 = VIL and CE2 = VIH.
3.
Address valid prior to or coincident with CE
1 transition LOW and/or CE
2 transition HIGH.
4.
OE = VIL.
5.
Transition is measured±500mV from steady state with C
L = 5pF. This parameter is guaranteed and not 100% tested.
V62C51864 Rev. 2.1 June 1998
7
V62C51864
MOSEL VITELIC
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)(4)
tWC
ADDRESS
tWR(2)
(6)
tCW
CE1
tAW
CE2
tCW(6)
tAS
WE
tWP(1)
OUTPUT
tDW
tWHZ
tDH
INPUT
51864 12
Write Cycle 2 (CE Controlled)(4)
tWC
ADDRESS
tWR(2)
tCW(6)
(4)
CE1
tAW
tCW(6)
CE2
tAS
WE
OUTPUT
High-Z
tDW
tDH
(5)
INPUT
51864 13
NOTES:
and CE2 active and WElow. Both signals must be active to
1.
The internal write time of the memory is defined by the overlap of 1CE
initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to
the second transition edge of the signal that terminates the write.
2.
tWR is measured from the earlier of CE
1 or WE going HIGH, or CE2 going LOW at the end of the write cycle.
3.
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4.
OE = VIL or VIH. However it is recommended to keep OE
at VIH during write cycle to avoid bus contention.
5.
If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
6.
tCW is measured from CE1 going LOW or CE2 going HIGH to the end of write.
V62C51864 Rev. 2.1 June 1998
8
V62C51864
MOSEL VITELIC
Package Diagrams
28-pin 600 mil Plastic DIP
15¡ MAX
0.543 ±0.010
[13.79 ±0.254]
INDEX
+0.008
1.407 –0.012
+0.203
35.56 –0.305
0.600 [15.24] TYP
0.010 ±0.002
[0.254 ± 0.51]
+0.020
0.039 –0.022
+0.508
0.991 –0.559
0.062 [1.57] MAX
0.195 [4.95] MAX
0.118 [3.00] MIN
Units in inches [mm]
0.020 [0.508] MIN
0.100 [2.54] TYP.
0.060 +0.020
–0.022
0.152 +0.508
–0.559
0.018 ±0.003
[0.457 ±0.076]
28-pin 330 mil SOP
Units in inches [mm]
0 MIN
(STAND OFF)
0.339 ± 0.008
[8.61 ± 0.203]
0.402 ±0.012
[10.21 ± 0.203]
0.465 ± 0.012
[11.81 ± 0.305]
0.031 ± 0.008
[0.787 ± 0.203]
INDEX
0.006 ± 0.002
[0.152 ± 0.051]
0.713 [18.11] TYP
0.112 [0.285] MAX
"A"
0.098 ± 0.005
[2.49 ± 0.127]
0.008 [0.203]
View "A"
0.050 [1.27] TYP
0.018 ± 0.004
[0.457 ± 0.102]
0.024 [0.610]
0.008 [0.203] MAX
0.027 [0.686] MAX
V62C51864 Rev. 2.1 June 1998
9
MOSEL VITELIC
WORLDWIDE OFFICES
V62C51864
U.S.A.
TAIWAN
JAPAN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
WBG MARINE WEST 25F
6, NAKASE 2-CHOME
MIHAMA-KU, CHIBA-SHI
CHIBA 261-71
PHONE: 81-43-299-6000
FAX: 81-43-299-6555
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 852-2665-4883
FAX: 852-2664-7535
1 CREATION ROAD I
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-578-3344
FAX: 886-3-579-2838
GERMANY
(CONTINENTAL
EUROPE & ISRAEL )
71083 HERRENBERG
BENZSTR. 32
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
IRELAND & UK
BLOCK A UNIT 2
BROOMFIELD BUSINESS PARK
MALAHIDE
CO. DUBLIN, IRELAND
PHONE: +353 1 8038020
FAX: +353 1 8038049
U.S. SALES OFFICES
NORTHWESTERN
SOUTHWESTERN
CENTRAL & SOUTHEASTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
SUITE 200
5150 E. PACIFIC COAST HWY.
LONG BEACH, CA 90804
PHONE: 562-498-3314
FAX: 562-597-2174
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 972-690-1402
FAX: 972-690-0341
NORTHEASTERN
SUITE 436
20 TRAFALGAR SQUARE
NASHUA, NH 03063
PHONE: 603-889-4393
FAX: 603-889-9347
© Copyright 1998, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
6/98
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461